Commit | Line | Data |
---|---|---|
ea291c98 TK |
1 | /* |
2 | * Device Tree Source for AM33xx clock data | |
3 | * | |
4 | * Copyright (C) 2013 Texas Instruments, Inc. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | */ | |
10 | &scrm_clocks { | |
11 | sys_clkin_ck: sys_clkin_ck { | |
12 | #clock-cells = <0>; | |
13 | compatible = "ti,mux-clock"; | |
14 | clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>; | |
15 | ti,bit-shift = <22>; | |
16 | reg = <0x0040>; | |
17 | }; | |
18 | ||
19 | adc_tsc_fck: adc_tsc_fck { | |
20 | #clock-cells = <0>; | |
21 | compatible = "fixed-factor-clock"; | |
22 | clocks = <&sys_clkin_ck>; | |
23 | clock-mult = <1>; | |
24 | clock-div = <1>; | |
25 | }; | |
26 | ||
27 | dcan0_fck: dcan0_fck { | |
28 | #clock-cells = <0>; | |
29 | compatible = "fixed-factor-clock"; | |
30 | clocks = <&sys_clkin_ck>; | |
31 | clock-mult = <1>; | |
32 | clock-div = <1>; | |
33 | }; | |
34 | ||
35 | dcan1_fck: dcan1_fck { | |
36 | #clock-cells = <0>; | |
37 | compatible = "fixed-factor-clock"; | |
38 | clocks = <&sys_clkin_ck>; | |
39 | clock-mult = <1>; | |
40 | clock-div = <1>; | |
41 | }; | |
42 | ||
43 | mcasp0_fck: mcasp0_fck { | |
44 | #clock-cells = <0>; | |
45 | compatible = "fixed-factor-clock"; | |
46 | clocks = <&sys_clkin_ck>; | |
47 | clock-mult = <1>; | |
48 | clock-div = <1>; | |
49 | }; | |
50 | ||
51 | mcasp1_fck: mcasp1_fck { | |
52 | #clock-cells = <0>; | |
53 | compatible = "fixed-factor-clock"; | |
54 | clocks = <&sys_clkin_ck>; | |
55 | clock-mult = <1>; | |
56 | clock-div = <1>; | |
57 | }; | |
58 | ||
59 | smartreflex0_fck: smartreflex0_fck { | |
60 | #clock-cells = <0>; | |
61 | compatible = "fixed-factor-clock"; | |
62 | clocks = <&sys_clkin_ck>; | |
63 | clock-mult = <1>; | |
64 | clock-div = <1>; | |
65 | }; | |
66 | ||
67 | smartreflex1_fck: smartreflex1_fck { | |
68 | #clock-cells = <0>; | |
69 | compatible = "fixed-factor-clock"; | |
70 | clocks = <&sys_clkin_ck>; | |
71 | clock-mult = <1>; | |
72 | clock-div = <1>; | |
73 | }; | |
74 | ||
75 | sha0_fck: sha0_fck { | |
76 | #clock-cells = <0>; | |
77 | compatible = "fixed-factor-clock"; | |
78 | clocks = <&sys_clkin_ck>; | |
79 | clock-mult = <1>; | |
80 | clock-div = <1>; | |
81 | }; | |
82 | ||
83 | aes0_fck: aes0_fck { | |
84 | #clock-cells = <0>; | |
85 | compatible = "fixed-factor-clock"; | |
86 | clocks = <&sys_clkin_ck>; | |
87 | clock-mult = <1>; | |
88 | clock-div = <1>; | |
89 | }; | |
90 | ||
91 | rng_fck: rng_fck { | |
92 | #clock-cells = <0>; | |
93 | compatible = "fixed-factor-clock"; | |
94 | clocks = <&sys_clkin_ck>; | |
95 | clock-mult = <1>; | |
96 | clock-div = <1>; | |
97 | }; | |
98 | ||
99 | ehrpwm0_gate_tbclk: ehrpwm0_gate_tbclk { | |
100 | #clock-cells = <0>; | |
101 | compatible = "ti,composite-no-wait-gate-clock"; | |
102 | clocks = <&dpll_per_m2_ck>; | |
103 | ti,bit-shift = <0>; | |
104 | reg = <0x0664>; | |
105 | }; | |
106 | ||
107 | ehrpwm0_tbclk: ehrpwm0_tbclk { | |
108 | #clock-cells = <0>; | |
109 | compatible = "ti,composite-clock"; | |
110 | clocks = <&ehrpwm0_gate_tbclk>; | |
111 | }; | |
112 | ||
113 | ehrpwm1_gate_tbclk: ehrpwm1_gate_tbclk { | |
114 | #clock-cells = <0>; | |
115 | compatible = "ti,composite-no-wait-gate-clock"; | |
116 | clocks = <&dpll_per_m2_ck>; | |
117 | ti,bit-shift = <1>; | |
118 | reg = <0x0664>; | |
119 | }; | |
120 | ||
121 | ehrpwm1_tbclk: ehrpwm1_tbclk { | |
122 | #clock-cells = <0>; | |
123 | compatible = "ti,composite-clock"; | |
124 | clocks = <&ehrpwm1_gate_tbclk>; | |
125 | }; | |
126 | ||
127 | ehrpwm2_gate_tbclk: ehrpwm2_gate_tbclk { | |
128 | #clock-cells = <0>; | |
129 | compatible = "ti,composite-no-wait-gate-clock"; | |
130 | clocks = <&dpll_per_m2_ck>; | |
131 | ti,bit-shift = <2>; | |
132 | reg = <0x0664>; | |
133 | }; | |
134 | ||
135 | ehrpwm2_tbclk: ehrpwm2_tbclk { | |
136 | #clock-cells = <0>; | |
137 | compatible = "ti,composite-clock"; | |
138 | clocks = <&ehrpwm2_gate_tbclk>; | |
139 | }; | |
140 | }; | |
141 | &prcm_clocks { | |
142 | clk_32768_ck: clk_32768_ck { | |
143 | #clock-cells = <0>; | |
144 | compatible = "fixed-clock"; | |
145 | clock-frequency = <32768>; | |
146 | }; | |
147 | ||
148 | clk_rc32k_ck: clk_rc32k_ck { | |
149 | #clock-cells = <0>; | |
150 | compatible = "fixed-clock"; | |
151 | clock-frequency = <32000>; | |
152 | }; | |
153 | ||
154 | virt_19200000_ck: virt_19200000_ck { | |
155 | #clock-cells = <0>; | |
156 | compatible = "fixed-clock"; | |
157 | clock-frequency = <19200000>; | |
158 | }; | |
159 | ||
160 | virt_24000000_ck: virt_24000000_ck { | |
161 | #clock-cells = <0>; | |
162 | compatible = "fixed-clock"; | |
163 | clock-frequency = <24000000>; | |
164 | }; | |
165 | ||
166 | virt_25000000_ck: virt_25000000_ck { | |
167 | #clock-cells = <0>; | |
168 | compatible = "fixed-clock"; | |
169 | clock-frequency = <25000000>; | |
170 | }; | |
171 | ||
172 | virt_26000000_ck: virt_26000000_ck { | |
173 | #clock-cells = <0>; | |
174 | compatible = "fixed-clock"; | |
175 | clock-frequency = <26000000>; | |
176 | }; | |
177 | ||
178 | tclkin_ck: tclkin_ck { | |
179 | #clock-cells = <0>; | |
180 | compatible = "fixed-clock"; | |
181 | clock-frequency = <12000000>; | |
182 | }; | |
183 | ||
184 | dpll_core_ck: dpll_core_ck { | |
185 | #clock-cells = <0>; | |
186 | compatible = "ti,am3-dpll-core-clock"; | |
187 | clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; | |
188 | reg = <0x0490>, <0x045c>, <0x0468>; | |
189 | }; | |
190 | ||
191 | dpll_core_x2_ck: dpll_core_x2_ck { | |
192 | #clock-cells = <0>; | |
193 | compatible = "ti,am3-dpll-x2-clock"; | |
194 | clocks = <&dpll_core_ck>; | |
195 | }; | |
196 | ||
197 | dpll_core_m4_ck: dpll_core_m4_ck { | |
198 | #clock-cells = <0>; | |
199 | compatible = "ti,divider-clock"; | |
200 | clocks = <&dpll_core_x2_ck>; | |
201 | ti,max-div = <31>; | |
202 | reg = <0x0480>; | |
203 | ti,index-starts-at-one; | |
204 | }; | |
205 | ||
206 | dpll_core_m5_ck: dpll_core_m5_ck { | |
207 | #clock-cells = <0>; | |
208 | compatible = "ti,divider-clock"; | |
209 | clocks = <&dpll_core_x2_ck>; | |
210 | ti,max-div = <31>; | |
211 | reg = <0x0484>; | |
212 | ti,index-starts-at-one; | |
213 | }; | |
214 | ||
215 | dpll_core_m6_ck: dpll_core_m6_ck { | |
216 | #clock-cells = <0>; | |
217 | compatible = "ti,divider-clock"; | |
218 | clocks = <&dpll_core_x2_ck>; | |
219 | ti,max-div = <31>; | |
220 | reg = <0x04d8>; | |
221 | ti,index-starts-at-one; | |
222 | }; | |
223 | ||
224 | dpll_mpu_ck: dpll_mpu_ck { | |
225 | #clock-cells = <0>; | |
226 | compatible = "ti,am3-dpll-clock"; | |
227 | clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; | |
228 | reg = <0x0488>, <0x0420>, <0x042c>; | |
229 | }; | |
230 | ||
231 | dpll_mpu_m2_ck: dpll_mpu_m2_ck { | |
232 | #clock-cells = <0>; | |
233 | compatible = "ti,divider-clock"; | |
234 | clocks = <&dpll_mpu_ck>; | |
235 | ti,max-div = <31>; | |
236 | reg = <0x04a8>; | |
237 | ti,index-starts-at-one; | |
238 | }; | |
239 | ||
240 | dpll_ddr_ck: dpll_ddr_ck { | |
241 | #clock-cells = <0>; | |
242 | compatible = "ti,am3-dpll-no-gate-clock"; | |
243 | clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; | |
244 | reg = <0x0494>, <0x0434>, <0x0440>; | |
245 | }; | |
246 | ||
247 | dpll_ddr_m2_ck: dpll_ddr_m2_ck { | |
248 | #clock-cells = <0>; | |
249 | compatible = "ti,divider-clock"; | |
250 | clocks = <&dpll_ddr_ck>; | |
251 | ti,max-div = <31>; | |
252 | reg = <0x04a0>; | |
253 | ti,index-starts-at-one; | |
254 | }; | |
255 | ||
256 | dpll_ddr_m2_div2_ck: dpll_ddr_m2_div2_ck { | |
257 | #clock-cells = <0>; | |
258 | compatible = "fixed-factor-clock"; | |
259 | clocks = <&dpll_ddr_m2_ck>; | |
260 | clock-mult = <1>; | |
261 | clock-div = <2>; | |
262 | }; | |
263 | ||
264 | dpll_disp_ck: dpll_disp_ck { | |
265 | #clock-cells = <0>; | |
266 | compatible = "ti,am3-dpll-no-gate-clock"; | |
267 | clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; | |
268 | reg = <0x0498>, <0x0448>, <0x0454>; | |
269 | }; | |
270 | ||
271 | dpll_disp_m2_ck: dpll_disp_m2_ck { | |
272 | #clock-cells = <0>; | |
273 | compatible = "ti,divider-clock"; | |
274 | clocks = <&dpll_disp_ck>; | |
275 | ti,max-div = <31>; | |
276 | reg = <0x04a4>; | |
277 | ti,index-starts-at-one; | |
278 | ti,set-rate-parent; | |
279 | }; | |
280 | ||
281 | dpll_per_ck: dpll_per_ck { | |
282 | #clock-cells = <0>; | |
283 | compatible = "ti,am3-dpll-no-gate-j-type-clock"; | |
284 | clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; | |
285 | reg = <0x048c>, <0x0470>, <0x049c>; | |
286 | }; | |
287 | ||
288 | dpll_per_m2_ck: dpll_per_m2_ck { | |
289 | #clock-cells = <0>; | |
290 | compatible = "ti,divider-clock"; | |
291 | clocks = <&dpll_per_ck>; | |
292 | ti,max-div = <31>; | |
293 | reg = <0x04ac>; | |
294 | ti,index-starts-at-one; | |
295 | }; | |
296 | ||
297 | dpll_per_m2_div4_wkupdm_ck: dpll_per_m2_div4_wkupdm_ck { | |
298 | #clock-cells = <0>; | |
299 | compatible = "fixed-factor-clock"; | |
300 | clocks = <&dpll_per_m2_ck>; | |
301 | clock-mult = <1>; | |
302 | clock-div = <4>; | |
303 | }; | |
304 | ||
305 | dpll_per_m2_div4_ck: dpll_per_m2_div4_ck { | |
306 | #clock-cells = <0>; | |
307 | compatible = "fixed-factor-clock"; | |
308 | clocks = <&dpll_per_m2_ck>; | |
309 | clock-mult = <1>; | |
310 | clock-div = <4>; | |
311 | }; | |
312 | ||
313 | cefuse_fck: cefuse_fck { | |
314 | #clock-cells = <0>; | |
315 | compatible = "ti,gate-clock"; | |
316 | clocks = <&sys_clkin_ck>; | |
317 | ti,bit-shift = <1>; | |
318 | reg = <0x0a20>; | |
319 | }; | |
320 | ||
321 | clk_24mhz: clk_24mhz { | |
322 | #clock-cells = <0>; | |
323 | compatible = "fixed-factor-clock"; | |
324 | clocks = <&dpll_per_m2_ck>; | |
325 | clock-mult = <1>; | |
326 | clock-div = <8>; | |
327 | }; | |
328 | ||
329 | clkdiv32k_ck: clkdiv32k_ck { | |
330 | #clock-cells = <0>; | |
331 | compatible = "fixed-factor-clock"; | |
332 | clocks = <&clk_24mhz>; | |
333 | clock-mult = <1>; | |
334 | clock-div = <732>; | |
335 | }; | |
336 | ||
337 | clkdiv32k_ick: clkdiv32k_ick { | |
338 | #clock-cells = <0>; | |
339 | compatible = "ti,gate-clock"; | |
340 | clocks = <&clkdiv32k_ck>; | |
341 | ti,bit-shift = <1>; | |
342 | reg = <0x014c>; | |
343 | }; | |
344 | ||
345 | l3_gclk: l3_gclk { | |
346 | #clock-cells = <0>; | |
347 | compatible = "fixed-factor-clock"; | |
348 | clocks = <&dpll_core_m4_ck>; | |
349 | clock-mult = <1>; | |
350 | clock-div = <1>; | |
351 | }; | |
352 | ||
353 | pruss_ocp_gclk: pruss_ocp_gclk { | |
354 | #clock-cells = <0>; | |
355 | compatible = "ti,mux-clock"; | |
356 | clocks = <&l3_gclk>, <&dpll_disp_m2_ck>; | |
357 | reg = <0x0530>; | |
358 | }; | |
359 | ||
360 | mmu_fck: mmu_fck { | |
361 | #clock-cells = <0>; | |
362 | compatible = "ti,gate-clock"; | |
363 | clocks = <&dpll_core_m4_ck>; | |
364 | ti,bit-shift = <1>; | |
365 | reg = <0x0914>; | |
366 | }; | |
367 | ||
368 | timer1_fck: timer1_fck { | |
369 | #clock-cells = <0>; | |
370 | compatible = "ti,mux-clock"; | |
371 | clocks = <&sys_clkin_ck>, <&clkdiv32k_ick>, <&tclkin_ck>, <&clk_rc32k_ck>, <&clk_32768_ck>; | |
372 | reg = <0x0528>; | |
373 | }; | |
374 | ||
375 | timer2_fck: timer2_fck { | |
376 | #clock-cells = <0>; | |
377 | compatible = "ti,mux-clock"; | |
378 | clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; | |
379 | reg = <0x0508>; | |
380 | }; | |
381 | ||
382 | timer3_fck: timer3_fck { | |
383 | #clock-cells = <0>; | |
384 | compatible = "ti,mux-clock"; | |
385 | clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; | |
386 | reg = <0x050c>; | |
387 | }; | |
388 | ||
389 | timer4_fck: timer4_fck { | |
390 | #clock-cells = <0>; | |
391 | compatible = "ti,mux-clock"; | |
392 | clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; | |
393 | reg = <0x0510>; | |
394 | }; | |
395 | ||
396 | timer5_fck: timer5_fck { | |
397 | #clock-cells = <0>; | |
398 | compatible = "ti,mux-clock"; | |
399 | clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; | |
400 | reg = <0x0518>; | |
401 | }; | |
402 | ||
403 | timer6_fck: timer6_fck { | |
404 | #clock-cells = <0>; | |
405 | compatible = "ti,mux-clock"; | |
406 | clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; | |
407 | reg = <0x051c>; | |
408 | }; | |
409 | ||
410 | timer7_fck: timer7_fck { | |
411 | #clock-cells = <0>; | |
412 | compatible = "ti,mux-clock"; | |
413 | clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; | |
414 | reg = <0x0504>; | |
415 | }; | |
416 | ||
417 | usbotg_fck: usbotg_fck { | |
418 | #clock-cells = <0>; | |
419 | compatible = "ti,gate-clock"; | |
420 | clocks = <&dpll_per_ck>; | |
421 | ti,bit-shift = <8>; | |
422 | reg = <0x047c>; | |
423 | }; | |
424 | ||
425 | dpll_core_m4_div2_ck: dpll_core_m4_div2_ck { | |
426 | #clock-cells = <0>; | |
427 | compatible = "fixed-factor-clock"; | |
428 | clocks = <&dpll_core_m4_ck>; | |
429 | clock-mult = <1>; | |
430 | clock-div = <2>; | |
431 | }; | |
432 | ||
433 | ieee5000_fck: ieee5000_fck { | |
434 | #clock-cells = <0>; | |
435 | compatible = "ti,gate-clock"; | |
436 | clocks = <&dpll_core_m4_div2_ck>; | |
437 | ti,bit-shift = <1>; | |
438 | reg = <0x00e4>; | |
439 | }; | |
440 | ||
441 | wdt1_fck: wdt1_fck { | |
442 | #clock-cells = <0>; | |
443 | compatible = "ti,mux-clock"; | |
444 | clocks = <&clk_rc32k_ck>, <&clkdiv32k_ick>; | |
445 | reg = <0x0538>; | |
446 | }; | |
447 | ||
448 | l4_rtc_gclk: l4_rtc_gclk { | |
449 | #clock-cells = <0>; | |
450 | compatible = "fixed-factor-clock"; | |
451 | clocks = <&dpll_core_m4_ck>; | |
452 | clock-mult = <1>; | |
453 | clock-div = <2>; | |
454 | }; | |
455 | ||
456 | l4hs_gclk: l4hs_gclk { | |
457 | #clock-cells = <0>; | |
458 | compatible = "fixed-factor-clock"; | |
459 | clocks = <&dpll_core_m4_ck>; | |
460 | clock-mult = <1>; | |
461 | clock-div = <1>; | |
462 | }; | |
463 | ||
464 | l3s_gclk: l3s_gclk { | |
465 | #clock-cells = <0>; | |
466 | compatible = "fixed-factor-clock"; | |
467 | clocks = <&dpll_core_m4_div2_ck>; | |
468 | clock-mult = <1>; | |
469 | clock-div = <1>; | |
470 | }; | |
471 | ||
472 | l4fw_gclk: l4fw_gclk { | |
473 | #clock-cells = <0>; | |
474 | compatible = "fixed-factor-clock"; | |
475 | clocks = <&dpll_core_m4_div2_ck>; | |
476 | clock-mult = <1>; | |
477 | clock-div = <1>; | |
478 | }; | |
479 | ||
480 | l4ls_gclk: l4ls_gclk { | |
481 | #clock-cells = <0>; | |
482 | compatible = "fixed-factor-clock"; | |
483 | clocks = <&dpll_core_m4_div2_ck>; | |
484 | clock-mult = <1>; | |
485 | clock-div = <1>; | |
486 | }; | |
487 | ||
488 | sysclk_div_ck: sysclk_div_ck { | |
489 | #clock-cells = <0>; | |
490 | compatible = "fixed-factor-clock"; | |
491 | clocks = <&dpll_core_m4_ck>; | |
492 | clock-mult = <1>; | |
493 | clock-div = <1>; | |
494 | }; | |
495 | ||
496 | cpsw_125mhz_gclk: cpsw_125mhz_gclk { | |
497 | #clock-cells = <0>; | |
498 | compatible = "fixed-factor-clock"; | |
499 | clocks = <&dpll_core_m5_ck>; | |
500 | clock-mult = <1>; | |
501 | clock-div = <2>; | |
502 | }; | |
503 | ||
504 | cpsw_cpts_rft_clk: cpsw_cpts_rft_clk { | |
505 | #clock-cells = <0>; | |
506 | compatible = "ti,mux-clock"; | |
507 | clocks = <&dpll_core_m5_ck>, <&dpll_core_m4_ck>; | |
508 | reg = <0x0520>; | |
509 | }; | |
510 | ||
511 | gpio0_dbclk_mux_ck: gpio0_dbclk_mux_ck { | |
512 | #clock-cells = <0>; | |
513 | compatible = "ti,mux-clock"; | |
514 | clocks = <&clk_rc32k_ck>, <&clk_32768_ck>, <&clkdiv32k_ick>; | |
515 | reg = <0x053c>; | |
516 | }; | |
517 | ||
518 | gpio0_dbclk: gpio0_dbclk { | |
519 | #clock-cells = <0>; | |
520 | compatible = "ti,gate-clock"; | |
521 | clocks = <&gpio0_dbclk_mux_ck>; | |
522 | ti,bit-shift = <18>; | |
523 | reg = <0x0408>; | |
524 | }; | |
525 | ||
526 | gpio1_dbclk: gpio1_dbclk { | |
527 | #clock-cells = <0>; | |
528 | compatible = "ti,gate-clock"; | |
529 | clocks = <&clkdiv32k_ick>; | |
530 | ti,bit-shift = <18>; | |
531 | reg = <0x00ac>; | |
532 | }; | |
533 | ||
534 | gpio2_dbclk: gpio2_dbclk { | |
535 | #clock-cells = <0>; | |
536 | compatible = "ti,gate-clock"; | |
537 | clocks = <&clkdiv32k_ick>; | |
538 | ti,bit-shift = <18>; | |
539 | reg = <0x00b0>; | |
540 | }; | |
541 | ||
542 | gpio3_dbclk: gpio3_dbclk { | |
543 | #clock-cells = <0>; | |
544 | compatible = "ti,gate-clock"; | |
545 | clocks = <&clkdiv32k_ick>; | |
546 | ti,bit-shift = <18>; | |
547 | reg = <0x00b4>; | |
548 | }; | |
549 | ||
550 | lcd_gclk: lcd_gclk { | |
551 | #clock-cells = <0>; | |
552 | compatible = "ti,mux-clock"; | |
553 | clocks = <&dpll_disp_m2_ck>, <&dpll_core_m5_ck>, <&dpll_per_m2_ck>; | |
554 | reg = <0x0534>; | |
555 | ti,set-rate-parent; | |
556 | }; | |
557 | ||
558 | mmc_clk: mmc_clk { | |
559 | #clock-cells = <0>; | |
560 | compatible = "fixed-factor-clock"; | |
561 | clocks = <&dpll_per_m2_ck>; | |
562 | clock-mult = <1>; | |
563 | clock-div = <2>; | |
564 | }; | |
565 | ||
566 | gfx_fclk_clksel_ck: gfx_fclk_clksel_ck { | |
567 | #clock-cells = <0>; | |
568 | compatible = "ti,mux-clock"; | |
569 | clocks = <&dpll_core_m4_ck>, <&dpll_per_m2_ck>; | |
570 | ti,bit-shift = <1>; | |
571 | reg = <0x052c>; | |
572 | }; | |
573 | ||
574 | gfx_fck_div_ck: gfx_fck_div_ck { | |
575 | #clock-cells = <0>; | |
576 | compatible = "ti,divider-clock"; | |
577 | clocks = <&gfx_fclk_clksel_ck>; | |
578 | reg = <0x052c>; | |
579 | ti,max-div = <2>; | |
580 | }; | |
581 | ||
582 | sysclkout_pre_ck: sysclkout_pre_ck { | |
583 | #clock-cells = <0>; | |
584 | compatible = "ti,mux-clock"; | |
585 | clocks = <&clk_32768_ck>, <&l3_gclk>, <&dpll_ddr_m2_ck>, <&dpll_per_m2_ck>, <&lcd_gclk>; | |
586 | reg = <0x0700>; | |
587 | }; | |
588 | ||
589 | clkout2_div_ck: clkout2_div_ck { | |
590 | #clock-cells = <0>; | |
591 | compatible = "ti,divider-clock"; | |
592 | clocks = <&sysclkout_pre_ck>; | |
593 | ti,bit-shift = <3>; | |
594 | ti,max-div = <8>; | |
595 | reg = <0x0700>; | |
596 | }; | |
597 | ||
598 | dbg_sysclk_ck: dbg_sysclk_ck { | |
599 | #clock-cells = <0>; | |
600 | compatible = "ti,gate-clock"; | |
601 | clocks = <&sys_clkin_ck>; | |
602 | ti,bit-shift = <19>; | |
603 | reg = <0x0414>; | |
604 | }; | |
605 | ||
606 | dbg_clka_ck: dbg_clka_ck { | |
607 | #clock-cells = <0>; | |
608 | compatible = "ti,gate-clock"; | |
609 | clocks = <&dpll_core_m4_ck>; | |
610 | ti,bit-shift = <30>; | |
611 | reg = <0x0414>; | |
612 | }; | |
613 | ||
614 | stm_pmd_clock_mux_ck: stm_pmd_clock_mux_ck { | |
615 | #clock-cells = <0>; | |
616 | compatible = "ti,mux-clock"; | |
617 | clocks = <&dbg_sysclk_ck>, <&dbg_clka_ck>; | |
618 | ti,bit-shift = <22>; | |
619 | reg = <0x0414>; | |
620 | }; | |
621 | ||
622 | trace_pmd_clk_mux_ck: trace_pmd_clk_mux_ck { | |
623 | #clock-cells = <0>; | |
624 | compatible = "ti,mux-clock"; | |
625 | clocks = <&dbg_sysclk_ck>, <&dbg_clka_ck>; | |
626 | ti,bit-shift = <20>; | |
627 | reg = <0x0414>; | |
628 | }; | |
629 | ||
630 | stm_clk_div_ck: stm_clk_div_ck { | |
631 | #clock-cells = <0>; | |
632 | compatible = "ti,divider-clock"; | |
633 | clocks = <&stm_pmd_clock_mux_ck>; | |
634 | ti,bit-shift = <27>; | |
635 | ti,max-div = <64>; | |
636 | reg = <0x0414>; | |
637 | ti,index-power-of-two; | |
638 | }; | |
639 | ||
640 | trace_clk_div_ck: trace_clk_div_ck { | |
641 | #clock-cells = <0>; | |
642 | compatible = "ti,divider-clock"; | |
643 | clocks = <&trace_pmd_clk_mux_ck>; | |
644 | ti,bit-shift = <24>; | |
645 | ti,max-div = <64>; | |
646 | reg = <0x0414>; | |
647 | ti,index-power-of-two; | |
648 | }; | |
649 | ||
650 | clkout2_ck: clkout2_ck { | |
651 | #clock-cells = <0>; | |
652 | compatible = "ti,gate-clock"; | |
653 | clocks = <&clkout2_div_ck>; | |
654 | ti,bit-shift = <7>; | |
655 | reg = <0x0700>; | |
656 | }; | |
657 | }; | |
658 | ||
659 | &prcm_clockdomains { | |
660 | clk_24mhz_clkdm: clk_24mhz_clkdm { | |
661 | compatible = "ti,clockdomain"; | |
662 | clocks = <&clkdiv32k_ick>; | |
663 | }; | |
664 | }; |