[deliverable/linux.git] / arch / arm / boot / dts / am4372.dtsi

/*
 * Device Tree Source for AM4372 SoC
 *
 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
 *
 * This file is licensed under the terms of the GNU General Public License
 * version 2.  This program is licensed "as is" without any warranty of any
 * kind, whether express or implied.
 */

#include <dt-bindings/interrupt-controller/arm-gic.h>

#include "skeleton.dtsi"

/ {
	compatible = "ti,am4372", "ti,am43";
	interrupt-parent = <&gic>;


	aliases {
		i2c0 = &i2c0;
		i2c1 = &i2c1;
		i2c2 = &i2c2;
		serial0 = &uart0;
		ethernet0 = &cpsw_emac0;
		ethernet1 = &cpsw_emac1;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		cpu@0 {
			compatible = "arm,cortex-a9";
			device_type = "cpu";
			reg = <0>;
		};
	};

	gic: interrupt-controller@48241000 {
		compatible = "arm,cortex-a9-gic";
		interrupt-controller;
		#interrupt-cells = <3>;
		reg = <0x48241000 0x1000>,
		      <0x48240100 0x0100>;
	};

	l2-cache-controller@48242000 {
		compatible = "arm,pl310-cache";
		reg = <0x48242000 0x1000>;
		cache-unified;
		cache-level = <2>;
	};

	am43xx_pinmux: pinmux@44e10800 {
		compatible = "pinctrl-single";
		reg = <0x44e10800 0x31c>;
		#address-cells = <1>;
		#size-cells = <0>;
		pinctrl-single,register-width = <32>;
		pinctrl-single,function-mask = <0xffffffff>;
	};

	ocp {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;
		ti,hwmods = "l3_main";

		prcm: prcm@44df0000 {
			compatible = "ti,am4-prcm";
			reg = <0x44df0000 0x11000>;

			prcm_clocks: clocks {
				#address-cells = <1>;
				#size-cells = <0>;
			};

			prcm_clockdomains: clockdomains {
			};
		};

		scrm: scrm@44e10000 {
			compatible = "ti,am4-scrm";
			reg = <0x44e10000 0x2000>;

			scrm_clocks: clocks {
				#address-cells = <1>;
				#size-cells = <0>;
			};

			scrm_clockdomains: clockdomains {
			};
		};

		edma: edma@49000000 {
			compatible = "ti,edma3";
			ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2";
			reg =	<0x49000000 0x10000>,
				<0x44e10f90 0x10>;
			interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
			#dma-cells = <1>;
			dma-channels = <64>;
			ti,edma-regions = <4>;
			ti,edma-slots = <256>;
		};

		uart0: serial@44e09000 {
			compatible = "ti,am4372-uart","ti,omap2-uart";
			reg = <0x44e09000 0x2000>;
			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "uart1";
		};

		uart1: serial@48022000 {
			compatible = "ti,am4372-uart","ti,omap2-uart";
			reg = <0x48022000 0x2000>;
			interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "uart2";
			status = "disabled";
		};

		uart2: serial@48024000 {
			compatible = "ti,am4372-uart","ti,omap2-uart";
			reg = <0x48024000 0x2000>;
			interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "uart3";
			status = "disabled";
		};

		uart3: serial@481a6000 {
			compatible = "ti,am4372-uart","ti,omap2-uart";
			reg = <0x481a6000 0x2000>;
			interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "uart4";
			status = "disabled";
		};

		uart4: serial@481a8000 {
			compatible = "ti,am4372-uart","ti,omap2-uart";
			reg = <0x481a8000 0x2000>;
			interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "uart5";
			status = "disabled";
		};

		uart5: serial@481aa000 {
			compatible = "ti,am4372-uart","ti,omap2-uart";
			reg = <0x481aa000 0x2000>;
			interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "uart6";
			status = "disabled";
		};

		mailbox: mailbox@480C8000 {
			compatible = "ti,omap4-mailbox";
			reg = <0x480C8000 0x200>;
			interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "mailbox";
			ti,mbox-num-users = <4>;
			ti,mbox-num-fifos = <8>;
			ti,mbox-names = "wkup_m3";
			ti,mbox-data = <0 0 0 0>;
			status = "disabled";
		};

		timer1: timer@44e31000 {
			compatible = "ti,am4372-timer-1ms","ti,am335x-timer-1ms";
			reg = <0x44e31000 0x400>;
			interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
			ti,timer-alwon;
			ti,hwmods = "timer1";
		};

		timer2: timer@48040000  {
			compatible = "ti,am4372-timer","ti,am335x-timer";
			reg = <0x48040000  0x400>;
			interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "timer2";
		};

		timer3: timer@48042000 {
			compatible = "ti,am4372-timer","ti,am335x-timer";
			reg = <0x48042000 0x400>;
			interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "timer3";
			status = "disabled";
		};

		timer4: timer@48044000 {
			compatible = "ti,am4372-timer","ti,am335x-timer";
			reg = <0x48044000 0x400>;
			interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
			ti,timer-pwm;
			ti,hwmods = "timer4";
			status = "disabled";
		};

		timer5: timer@48046000 {
			compatible = "ti,am4372-timer","ti,am335x-timer";
			reg = <0x48046000 0x400>;
			interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
			ti,timer-pwm;
			ti,hwmods = "timer5";
			status = "disabled";
		};

		timer6: timer@48048000 {
			compatible = "ti,am4372-timer","ti,am335x-timer";
			reg = <0x48048000 0x400>;
			interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
			ti,timer-pwm;
			ti,hwmods = "timer6";
			status = "disabled";
		};

		timer7: timer@4804a000 {
			compatible = "ti,am4372-timer","ti,am335x-timer";
			reg = <0x4804a000 0x400>;
			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
			ti,timer-pwm;
			ti,hwmods = "timer7";
			status = "disabled";
		};

		timer8: timer@481c1000 {
			compatible = "ti,am4372-timer","ti,am335x-timer";
			reg = <0x481c1000 0x400>;
			interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "timer8";
			status = "disabled";
		};

		timer9: timer@4833d000 {
			compatible = "ti,am4372-timer","ti,am335x-timer";
			reg = <0x4833d000 0x400>;
			interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "timer9";
			status = "disabled";
		};

		timer10: timer@4833f000 {
			compatible = "ti,am4372-timer","ti,am335x-timer";
			reg = <0x4833f000 0x400>;
			interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "timer10";
			status = "disabled";
		};

		timer11: timer@48341000 {
			compatible = "ti,am4372-timer","ti,am335x-timer";
			reg = <0x48341000 0x400>;
			interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "timer11";
			status = "disabled";
		};

		counter32k: counter@44e86000 {
			compatible = "ti,am4372-counter32k","ti,omap-counter32k";
			reg = <0x44e86000 0x40>;
			ti,hwmods = "counter_32k";
		};

		rtc@44e3e000 {
			compatible = "ti,am4372-rtc","ti,da830-rtc";
			reg = <0x44e3e000 0x1000>;
			interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH
				      GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "rtc";
			status = "disabled";
		};

		wdt@44e35000 {
			compatible = "ti,am4372-wdt","ti,omap3-wdt";
			reg = <0x44e35000 0x1000>;
			interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "wd_timer2";
		};

		gpio0: gpio@44e07000 {
			compatible = "ti,am4372-gpio","ti,omap4-gpio";
			reg = <0x44e07000 0x1000>;
			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
			ti,hwmods = "gpio1";
			status = "disabled";
		};

		gpio1: gpio@4804c000 {
			compatible = "ti,am4372-gpio","ti,omap4-gpio";
			reg = <0x4804c000 0x1000>;
			interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
			ti,hwmods = "gpio2";
			status = "disabled";
		};

		gpio2: gpio@481ac000 {
			compatible = "ti,am4372-gpio","ti,omap4-gpio";
			reg = <0x481ac000 0x1000>;
			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
			ti,hwmods = "gpio3";
			status = "disabled";
		};

		gpio3: gpio@481ae000 {
			compatible = "ti,am4372-gpio","ti,omap4-gpio";
			reg = <0x481ae000 0x1000>;
			interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
			ti,hwmods = "gpio4";
			status = "disabled";
		};

		gpio4: gpio@48320000 {
			compatible = "ti,am4372-gpio","ti,omap4-gpio";
			reg = <0x48320000 0x1000>;
			interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
			ti,hwmods = "gpio5";
			status = "disabled";
		};

		gpio5: gpio@48322000 {
			compatible = "ti,am4372-gpio","ti,omap4-gpio";
			reg = <0x48322000 0x1000>;
			interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
			ti,hwmods = "gpio6";
			status = "disabled";
		};

		i2c0: i2c@44e0b000 {
			compatible = "ti,am4372-i2c","ti,omap4-i2c";
			reg = <0x44e0b000 0x1000>;
			interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "i2c1";
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		i2c1: i2c@4802a000 {
			compatible = "ti,am4372-i2c","ti,omap4-i2c";
			reg = <0x4802a000 0x1000>;
			interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "i2c2";
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		i2c2: i2c@4819c000 {
			compatible = "ti,am4372-i2c","ti,omap4-i2c";
			reg = <0x4819c000 0x1000>;
			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "i2c3";
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		spi0: spi@48030000 {
			compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
			reg = <0x48030000 0x400>;
			interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "spi0";
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		mmc1: mmc@48060000 {
			compatible = "ti,omap4-hsmmc";
			reg = <0x48060000 0x1000>;
			ti,hwmods = "mmc1";
			ti,dual-volt;
			ti,needs-special-reset;
			dmas = <&edma 24
				&edma 25>;
			dma-names = "tx", "rx";
			interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
			status = "disabled";
		};

		mmc2: mmc@481d8000 {
			compatible = "ti,omap4-hsmmc";
			reg = <0x481d8000 0x1000>;
			ti,hwmods = "mmc2";
			ti,needs-special-reset;
			dmas = <&edma 2
				&edma 3>;
			dma-names = "tx", "rx";
			interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
			status = "disabled";
		};

		mmc3: mmc@47810000 {
			compatible = "ti,omap4-hsmmc";
			reg = <0x47810000 0x1000>;
			ti,hwmods = "mmc3";
			ti,needs-special-reset;
			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
			status = "disabled";
		};

		spi1: spi@481a0000 {
			compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
			reg = <0x481a0000 0x400>;
			interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "spi1";
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		spi2: spi@481a2000 {
			compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
			reg = <0x481a2000 0x400>;
			interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "spi2";
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		spi3: spi@481a4000 {
			compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
			reg = <0x481a4000 0x400>;
			interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "spi3";
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		spi4: spi@48345000 {
			compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
			reg = <0x48345000 0x400>;
			interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "spi4";
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		mac: ethernet@4a100000 {
			compatible = "ti,am4372-cpsw","ti,cpsw";
			reg = <0x4a100000 0x800
			       0x4a101200 0x100>;
			interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH
				      GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH
				      GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH
				      GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
			#address-cells = <1>;
			#size-cells = <1>;
			ti,hwmods = "cpgmac0";
			status = "disabled";
			cpdma_channels = <8>;
			ale_entries = <1024>;
			bd_ram_size = <0x2000>;
			no_bd_ram = <0>;
			rx_descs = <64>;
			mac_control = <0x20>;
			slaves = <2>;
			active_slave = <0>;
			cpts_clock_mult = <0x80000000>;
			cpts_clock_shift = <29>;
			ranges;

			davinci_mdio: mdio@4a101000 {
				compatible = "ti,am4372-mdio","ti,davinci_mdio";
				reg = <0x4a101000 0x100>;
				#address-cells = <1>;
				#size-cells = <0>;
				ti,hwmods = "davinci_mdio";
				bus_freq = <1000000>;
				status = "disabled";
			};

			cpsw_emac0: slave@4a100200 {
				/* Filled in by U-Boot */
				mac-address = [ 00 00 00 00 00 00 ];
			};

			cpsw_emac1: slave@4a100300 {
				/* Filled in by U-Boot */
				mac-address = [ 00 00 00 00 00 00 ];
			};
		};

		epwmss0: epwmss@48300000 {
			compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
			reg = <0x48300000 0x10>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;
			ti,hwmods = "epwmss0";
			status = "disabled";

			ecap0: ecap@48300100 {
				compatible = "ti,am4372-ecap","ti,am33xx-ecap";
				reg = <0x48300100 0x80>;
				ti,hwmods = "ecap0";
				status = "disabled";
			};

			ehrpwm0: ehrpwm@48300200 {
				compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
				reg = <0x48300200 0x80>;
				ti,hwmods = "ehrpwm0";
				status = "disabled";
			};
		};

		epwmss1: epwmss@48302000 {
			compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
			reg = <0x48302000 0x10>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;
			ti,hwmods = "epwmss1";
			status = "disabled";

			ecap1: ecap@48302100 {
				compatible = "ti,am4372-ecap","ti,am33xx-ecap";
				reg = <0x48302100 0x80>;
				ti,hwmods = "ecap1";
				status = "disabled";
			};

			ehrpwm1: ehrpwm@48302200 {
				compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
				reg = <0x48302200 0x80>;
				ti,hwmods = "ehrpwm1";
				status = "disabled";
			};
		};

		epwmss2: epwmss@48304000 {
			compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
			reg = <0x48304000 0x10>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;
			ti,hwmods = "epwmss2";
			status = "disabled";

			ecap2: ecap@48304100 {
				compatible = "ti,am4372-ecap","ti,am33xx-ecap";
				reg = <0x48304100 0x80>;
				ti,hwmods = "ecap2";
				status = "disabled";
			};

			ehrpwm2: ehrpwm@48304200 {
				compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
				reg = <0x48304200 0x80>;
				ti,hwmods = "ehrpwm2";
				status = "disabled";
			};
		};

		epwmss3: epwmss@48306000 {
			compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
			reg = <0x48306000 0x10>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;
			ti,hwmods = "epwmss3";
			status = "disabled";

			ehrpwm3: ehrpwm@48306200 {
				compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
				reg = <0x48306200 0x80>;
				ti,hwmods = "ehrpwm3";
				status = "disabled";
			};
		};

		epwmss4: epwmss@48308000 {
			compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
			reg = <0x48308000 0x10>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;
			ti,hwmods = "epwmss4";
			status = "disabled";

			ehrpwm4: ehrpwm@48308200 {
				compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
				reg = <0x48308200 0x80>;
				ti,hwmods = "ehrpwm4";
				status = "disabled";
			};
		};

		epwmss5: epwmss@4830a000 {
			compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
			reg = <0x4830a000 0x10>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;
			ti,hwmods = "epwmss5";
			status = "disabled";

			ehrpwm5: ehrpwm@4830a200 {
				compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
				reg = <0x4830a200 0x80>;
				ti,hwmods = "ehrpwm5";
				status = "disabled";
			};
		};

		sham: sham@53100000 {
			compatible = "ti,omap5-sham";
			ti,hwmods = "sham";
			reg = <0x53100000 0x300>;
			dmas = <&edma 36>;
			dma-names = "rx";
			interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
		};

		aes: aes@53501000 {
			compatible = "ti,omap4-aes";
			ti,hwmods = "aes";
			reg = <0x53501000 0xa0>;
			interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
			dmas = <&edma 6
				&edma 5>;
			dma-names = "tx", "rx";
		};

		des: des@53701000 {
			compatible = "ti,omap4-des";
			ti,hwmods = "des";
			reg = <0x53701000 0xa0>;
			interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
			dmas = <&edma 34
				&edma 33>;
			dma-names = "tx", "rx";
		};

		mcasp0: mcasp@48038000 {
			compatible = "ti,am33xx-mcasp-audio";
			ti,hwmods = "mcasp0";
			reg = <0x48038000 0x2000>,
			      <0x46000000 0x400000>;
			reg-names = "mpu", "dat";
			interrupts = <80>, <81>;
			interrupts-names = "tx", "rx";
			status = "disabled";
			dmas = <&edma 8>,
			       <&edma 9>;
			dma-names = "tx", "rx";
		};

		mcasp1: mcasp@4803C000 {
			compatible = "ti,am33xx-mcasp-audio";
			ti,hwmods = "mcasp1";
			reg = <0x4803C000 0x2000>,
			      <0x46400000 0x400000>;
			reg-names = "mpu", "dat";
			interrupts = <82>, <83>;
			interrupts-names = "tx", "rx";
			status = "disabled";
			dmas = <&edma 10>,
			       <&edma 11>;
			dma-names = "tx", "rx";
		};
	};
};

/include/ "am43xx-clocks.dtsi"
Commit	Line	Data
6cfd8117 AM	1	/*
	2	* Device Tree Source for AM4372 SoC
	3	*
	4	* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
	5	*
	6	* This file is licensed under the terms of the GNU General Public License
	7	* version 2. This program is licensed "as is" without any warranty of any
	8	* kind, whether express or implied.
	9	*/
	10
	11	#include <dt-bindings/interrupt-controller/arm-gic.h>
	12
	13	#include "skeleton.dtsi"
	14
	15	/ {
	16	compatible = "ti,am4372", "ti,am43";
	17	interrupt-parent = <&gic>;
	18
	19
	20	aliases {
6a968678 NM	21	i2c0 = &i2c0;
	22	i2c1 = &i2c1;
	23	i2c2 = &i2c2;
6cfd8117	24	serial0 = &uart0;
9e3269b8 LV	25	ethernet0 = &cpsw_emac0;
9e3269b8 LV	26	ethernet1 = &cpsw_emac1;
6cfd8117 AM	27	};
	28
	29	cpus {
738c7409 AM	30	#address-cells = <1>;
738c7409 AM	31	#size-cells = <0>;
6cfd8117 AM	32	cpu@0 {
6cfd8117 AM	33	compatible = "arm,cortex-a9";
738c7409 AM	34	device_type = "cpu";
738c7409 AM	35	reg = <0>;
6cfd8117 AM	36	};
	37	};
	38
	39	gic: interrupt-controller@48241000 {
	40	compatible = "arm,cortex-a9-gic";
	41	interrupt-controller;
	42	#interrupt-cells = <3>;
	43	reg = <0x48241000 0x1000>,
	44	<0x48240100 0x0100>;
	45	};
	46
9e3269b8 LV	47	l2-cache-controller@48242000 {
	48	compatible = "arm,pl310-cache";
	49	reg = <0x48242000 0x1000>;
	50	cache-unified;
	51	cache-level = <2>;
	52	};
	53
	54	am43xx_pinmux: pinmux@44e10800 {
	55	compatible = "pinctrl-single";
	56	reg = <0x44e10800 0x31c>;
	57	#address-cells = <1>;
	58	#size-cells = <0>;
	59	pinctrl-single,register-width = <32>;
	60	pinctrl-single,function-mask = <0xffffffff>;
	61	};
	62
6cfd8117 AM	63	ocp {
	64	compatible = "simple-bus";
	65	#address-cells = <1>;
	66	#size-cells = <1>;
	67	ranges;
9e3269b8 LV	68	ti,hwmods = "l3_main";
9e3269b8 LV	69
6a679208 TK	70	prcm: prcm@44df0000 {
	71	compatible = "ti,am4-prcm";
	72	reg = <0x44df0000 0x11000>;
	73
	74	prcm_clocks: clocks {
	75	#address-cells = <1>;
	76	#size-cells = <0>;
	77	};
	78
	79	prcm_clockdomains: clockdomains {
	80	};
	81	};
	82
	83	scrm: scrm@44e10000 {
	84	compatible = "ti,am4-scrm";
	85	reg = <0x44e10000 0x2000>;
	86
	87	scrm_clocks: clocks {
	88	#address-cells = <1>;
	89	#size-cells = <0>;
	90	};
	91
	92	scrm_clockdomains: clockdomains {
	93	};
	94	};
	95
9e3269b8 LV	96	edma: edma@49000000 {
	97	compatible = "ti,edma3";
	98	ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2";
	99	reg = <0x49000000 0x10000>,
	100	<0x44e10f90 0x10>;
	101	interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
	102	<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
	103	<GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
	104	#dma-cells = <1>;
	105	dma-channels = <64>;
	106	ti,edma-regions = <4>;
	107	ti,edma-slots = <256>;
	108	};
6cfd8117 AM	109
	110	uart0: serial@44e09000 {
	111	compatible = "ti,am4372-uart","ti,omap2-uart";
	112	reg = <0x44e09000 0x2000>;
	113	interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
73456012 AM	114	ti,hwmods = "uart1";
	115	};
	116
	117	uart1: serial@48022000 {
	118	compatible = "ti,am4372-uart","ti,omap2-uart";
	119	reg = <0x48022000 0x2000>;
	120	interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
	121	ti,hwmods = "uart2";
	122	status = "disabled";
	123	};
	124
	125	uart2: serial@48024000 {
	126	compatible = "ti,am4372-uart","ti,omap2-uart";
	127	reg = <0x48024000 0x2000>;
	128	interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
	129	ti,hwmods = "uart3";
	130	status = "disabled";
	131	};
	132
	133	uart3: serial@481a6000 {
	134	compatible = "ti,am4372-uart","ti,omap2-uart";
	135	reg = <0x481a6000 0x2000>;
	136	interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
	137	ti,hwmods = "uart4";
	138	status = "disabled";
	139	};
	140
	141	uart4: serial@481a8000 {
	142	compatible = "ti,am4372-uart","ti,omap2-uart";
	143	reg = <0x481a8000 0x2000>;
	144	interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
	145	ti,hwmods = "uart5";
	146	status = "disabled";
	147	};
	148
	149	uart5: serial@481aa000 {
	150	compatible = "ti,am4372-uart","ti,omap2-uart";
	151	reg = <0x481aa000 0x2000>;
	152	interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
	153	ti,hwmods = "uart6";
	154	status = "disabled";
6cfd8117 AM	155	};
6cfd8117 AM	156
9e3269b8 LV	157	mailbox: mailbox@480C8000 {
	158	compatible = "ti,omap4-mailbox";
	159	reg = <0x480C8000 0x200>;
	160	interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
	161	ti,hwmods = "mailbox";
	162	ti,mbox-num-users = <4>;
	163	ti,mbox-num-fifos = <8>;
	164	ti,mbox-names = "wkup_m3";
	165	ti,mbox-data = <0 0 0 0>;
	166	status = "disabled";
	167	};
	168
6cfd8117 AM	169	timer1: timer@44e31000 {
	170	compatible = "ti,am4372-timer-1ms","ti,am335x-timer-1ms";
	171	reg = <0x44e31000 0x400>;
	172	interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
	173	ti,timer-alwon;
73456012	174	ti,hwmods = "timer1";
6cfd8117 AM	175	};
	176
	177	timer2: timer@48040000 {
	178	compatible = "ti,am4372-timer","ti,am335x-timer";
	179	reg = <0x48040000 0x400>;
	180	interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
73456012 AM	181	ti,hwmods = "timer2";
	182	};
	183
	184	timer3: timer@48042000 {
	185	compatible = "ti,am4372-timer","ti,am335x-timer";
	186	reg = <0x48042000 0x400>;
	187	interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
	188	ti,hwmods = "timer3";
	189	status = "disabled";
	190	};
	191
	192	timer4: timer@48044000 {
	193	compatible = "ti,am4372-timer","ti,am335x-timer";
	194	reg = <0x48044000 0x400>;
	195	interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
	196	ti,timer-pwm;
	197	ti,hwmods = "timer4";
	198	status = "disabled";
	199	};
	200
	201	timer5: timer@48046000 {
	202	compatible = "ti,am4372-timer","ti,am335x-timer";
	203	reg = <0x48046000 0x400>;
	204	interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
	205	ti,timer-pwm;
	206	ti,hwmods = "timer5";
	207	status = "disabled";
	208	};
	209
	210	timer6: timer@48048000 {
	211	compatible = "ti,am4372-timer","ti,am335x-timer";
	212	reg = <0x48048000 0x400>;
	213	interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
	214	ti,timer-pwm;
	215	ti,hwmods = "timer6";
	216	status = "disabled";
	217	};
	218
	219	timer7: timer@4804a000 {
	220	compatible = "ti,am4372-timer","ti,am335x-timer";
	221	reg = <0x4804a000 0x400>;
	222	interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
	223	ti,timer-pwm;
	224	ti,hwmods = "timer7";
	225	status = "disabled";
	226	};
	227
	228	timer8: timer@481c1000 {
	229	compatible = "ti,am4372-timer","ti,am335x-timer";
	230	reg = <0x481c1000 0x400>;
	231	interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
	232	ti,hwmods = "timer8";
	233	status = "disabled";
	234	};
	235
	236	timer9: timer@4833d000 {
	237	compatible = "ti,am4372-timer","ti,am335x-timer";
	238	reg = <0x4833d000 0x400>;
	239	interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
	240	ti,hwmods = "timer9";
	241	status = "disabled";
	242	};
	243
	244	timer10: timer@4833f000 {
245	compatible = "ti,am4372-timer","ti,am335x-timer";
246	reg = <0x4833f000 0x400>;
247	interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
248	ti,hwmods = "timer10";
249	status = "disabled";
250	};
251
252	timer11: timer@48341000 {
253	compatible = "ti,am4372-timer","ti,am335x-timer";
254	reg = <0x48341000 0x400>;
255	interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
256	ti,hwmods = "timer11";
257	status = "disabled";
6cfd8117 AM	258	};
	259
	260	counter32k: counter@44e86000 {
	261	compatible = "ti,am4372-counter32k","ti,omap-counter32k";
	262	reg = <0x44e86000 0x40>;
73456012 AM	263	ti,hwmods = "counter_32k";
	264	};
	265
	266	rtc@44e3e000 {
	267	compatible = "ti,am4372-rtc","ti,da830-rtc";
	268	reg = <0x44e3e000 0x1000>;
	269	interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH
	270	GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
	271	ti,hwmods = "rtc";
	272	status = "disabled";
	273	};
	274
	275	wdt@44e35000 {
	276	compatible = "ti,am4372-wdt","ti,omap3-wdt";
	277	reg = <0x44e35000 0x1000>;
	278	interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
	279	ti,hwmods = "wd_timer2";
73456012 AM	280	};
	281
	282	gpio0: gpio@44e07000 {
	283	compatible = "ti,am4372-gpio","ti,omap4-gpio";
	284	reg = <0x44e07000 0x1000>;
	285	interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
	286	gpio-controller;
	287	#gpio-cells = <2>;
	288	interrupt-controller;
	289	#interrupt-cells = <2>;
	290	ti,hwmods = "gpio1";
	291	status = "disabled";
	292	};
	293
	294	gpio1: gpio@4804c000 {
	295	compatible = "ti,am4372-gpio","ti,omap4-gpio";
	296	reg = <0x4804c000 0x1000>;
	297	interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
	298	gpio-controller;
	299	#gpio-cells = <2>;
	300	interrupt-controller;
	301	#interrupt-cells = <2>;
	302	ti,hwmods = "gpio2";
	303	status = "disabled";
	304	};
	305
	306	gpio2: gpio@481ac000 {
	307	compatible = "ti,am4372-gpio","ti,omap4-gpio";
	308	reg = <0x481ac000 0x1000>;
	309	interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
	310	gpio-controller;
	311	#gpio-cells = <2>;
	312	interrupt-controller;
	313	#interrupt-cells = <2>;
	314	ti,hwmods = "gpio3";
	315	status = "disabled";
	316	};
	317
	318	gpio3: gpio@481ae000 {
	319	compatible = "ti,am4372-gpio","ti,omap4-gpio";
	320	reg = <0x481ae000 0x1000>;
	321	interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
	322	gpio-controller;
	323	#gpio-cells = <2>;
	324	interrupt-controller;
	325	#interrupt-cells = <2>;
	326	ti,hwmods = "gpio4";
	327	status = "disabled";
	328	};
	329
	330	gpio4: gpio@48320000 {
	331	compatible = "ti,am4372-gpio","ti,omap4-gpio";
	332	reg = <0x48320000 0x1000>;
	333	interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
	334	gpio-controller;
	335	#gpio-cells = <2>;
	336	interrupt-controller;
	337	#interrupt-cells = <2>;
	338	ti,hwmods = "gpio5";
	339	status = "disabled";
	340	};
	341
	342	gpio5: gpio@48322000 {
	343	compatible = "ti,am4372-gpio","ti,omap4-gpio";
344	reg = <0x48322000 0x1000>;
345	interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
346	gpio-controller;
347	#gpio-cells = <2>;
348	interrupt-controller;
349	#interrupt-cells = <2>;
350	ti,hwmods = "gpio6";
351	status = "disabled";
352	};
353
354	i2c0: i2c@44e0b000 {
355	compatible = "ti,am4372-i2c","ti,omap4-i2c";
356	reg = <0x44e0b000 0x1000>;
357	interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
358	ti,hwmods = "i2c1";
359	#address-cells = <1>;
360	#size-cells = <0>;
361	status = "disabled";
362	};
363
364	i2c1: i2c@4802a000 {
365	compatible = "ti,am4372-i2c","ti,omap4-i2c";
366	reg = <0x4802a000 0x1000>;
367	interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
368	ti,hwmods = "i2c2";
369	#address-cells = <1>;
370	#size-cells = <0>;
371	status = "disabled";
372	};
373
374	i2c2: i2c@4819c000 {
375	compatible = "ti,am4372-i2c","ti,omap4-i2c";
376	reg = <0x4819c000 0x1000>;
377	interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
378	ti,hwmods = "i2c3";
379	#address-cells = <1>;
380	#size-cells = <0>;
381	status = "disabled";
382	};
383
384	spi0: spi@48030000 {
385	compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
386	reg = <0x48030000 0x400>;
387	interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
388	ti,hwmods = "spi0";
389	#address-cells = <1>;
390	#size-cells = <0>;
391	status = "disabled";
392	};
393
9e3269b8 LV	394	mmc1: mmc@48060000 {
	395	compatible = "ti,omap4-hsmmc";
	396	reg = <0x48060000 0x1000>;
	397	ti,hwmods = "mmc1";
	398	ti,dual-volt;
	399	ti,needs-special-reset;
	400	dmas = <&edma 24
	401	&edma 25>;
	402	dma-names = "tx", "rx";
	403	interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
	404	status = "disabled";
	405	};
	406
	407	mmc2: mmc@481d8000 {
	408	compatible = "ti,omap4-hsmmc";
	409	reg = <0x481d8000 0x1000>;
	410	ti,hwmods = "mmc2";
	411	ti,needs-special-reset;
	412	dmas = <&edma 2
	413	&edma 3>;
	414	dma-names = "tx", "rx";
	415	interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
	416	status = "disabled";
	417	};
	418
	419	mmc3: mmc@47810000 {
	420	compatible = "ti,omap4-hsmmc";
	421	reg = <0x47810000 0x1000>;
	422	ti,hwmods = "mmc3";
	423	ti,needs-special-reset;
	424	interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
	425	status = "disabled";
	426	};
	427
73456012 AM	428	spi1: spi@481a0000 {
	429	compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
	430	reg = <0x481a0000 0x400>;
	431	interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
	432	ti,hwmods = "spi1";
	433	#address-cells = <1>;
	434	#size-cells = <0>;
	435	status = "disabled";
	436	};
	437
	438	spi2: spi@481a2000 {
	439	compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
	440	reg = <0x481a2000 0x400>;
	441	interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
	442	ti,hwmods = "spi2";
	443	#address-cells = <1>;
	444	#size-cells = <0>;
	445	status = "disabled";
	446	};
	447
	448	spi3: spi@481a4000 {
	449	compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
	450	reg = <0x481a4000 0x400>;
	451	interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
	452	ti,hwmods = "spi3";
	453	#address-cells = <1>;
	454	#size-cells = <0>;
	455	status = "disabled";
	456	};
	457
	458	spi4: spi@48345000 {
	459	compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
	460	reg = <0x48345000 0x400>;
	461	interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
	462	ti,hwmods = "spi4";
	463	#address-cells = <1>;
	464	#size-cells = <0>;
	465	status = "disabled";
	466	};
	467
	468	mac: ethernet@4a100000 {
	469	compatible = "ti,am4372-cpsw","ti,cpsw";
	470	reg = <0x4a100000 0x800
	471	0x4a101200 0x100>;
	472	interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH
	473	GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH
	474	GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH
	475	GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
9e3269b8 LV	476	#address-cells = <1>;
9e3269b8 LV	477	#size-cells = <1>;
73456012 AM	478	ti,hwmods = "cpgmac0";
73456012 AM	479	status = "disabled";
9e3269b8 LV	480	cpdma_channels = <8>;
	481	ale_entries = <1024>;
	482	bd_ram_size = <0x2000>;
	483	no_bd_ram = <0>;
	484	rx_descs = <64>;
	485	mac_control = <0x20>;
	486	slaves = <2>;
	487	active_slave = <0>;
	488	cpts_clock_mult = <0x80000000>;
	489	cpts_clock_shift = <29>;
	490	ranges;
	491
	492	davinci_mdio: mdio@4a101000 {
	493	compatible = "ti,am4372-mdio","ti,davinci_mdio";
	494	reg = <0x4a101000 0x100>;
	495	#address-cells = <1>;
	496	#size-cells = <0>;
	497	ti,hwmods = "davinci_mdio";
	498	bus_freq = <1000000>;
	499	status = "disabled";
	500	};
	501
	502	cpsw_emac0: slave@4a100200 {
	503	/* Filled in by U-Boot */
	504	mac-address = [ 00 00 00 00 00 00 ];
	505	};
	506
	507	cpsw_emac1: slave@4a100300 {
	508	/* Filled in by U-Boot */
	509	mac-address = [ 00 00 00 00 00 00 ];
	510	};
73456012 AM	511	};
	512
	513	epwmss0: epwmss@48300000 {
	514	compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
	515	reg = <0x48300000 0x10>;
9e3269b8 LV	516	#address-cells = <1>;
	517	#size-cells = <1>;
	518	ranges;
73456012 AM	519	ti,hwmods = "epwmss0";
73456012 AM	520	status = "disabled";
9e3269b8 LV	521
	522	ecap0: ecap@48300100 {
	523	compatible = "ti,am4372-ecap","ti,am33xx-ecap";
	524	reg = <0x48300100 0x80>;
	525	ti,hwmods = "ecap0";
	526	status = "disabled";
	527	};
	528
	529	ehrpwm0: ehrpwm@48300200 {
	530	compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
	531	reg = <0x48300200 0x80>;
	532	ti,hwmods = "ehrpwm0";
	533	status = "disabled";
	534	};
73456012 AM	535	};
	536
	537	epwmss1: epwmss@48302000 {
	538	compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
	539	reg = <0x48302000 0x10>;
9e3269b8 LV	540	#address-cells = <1>;
	541	#size-cells = <1>;
	542	ranges;
73456012 AM	543	ti,hwmods = "epwmss1";
73456012 AM	544	status = "disabled";
9e3269b8 LV	545
	546	ecap1: ecap@48302100 {
	547	compatible = "ti,am4372-ecap","ti,am33xx-ecap";
	548	reg = <0x48302100 0x80>;
	549	ti,hwmods = "ecap1";
	550	status = "disabled";
	551	};
	552
	553	ehrpwm1: ehrpwm@48302200 {
	554	compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
	555	reg = <0x48302200 0x80>;
	556	ti,hwmods = "ehrpwm1";
	557	status = "disabled";
	558	};
73456012 AM	559	};
	560
	561	epwmss2: epwmss@48304000 {
	562	compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
	563	reg = <0x48304000 0x10>;
9e3269b8 LV	564	#address-cells = <1>;
	565	#size-cells = <1>;
	566	ranges;
73456012 AM	567	ti,hwmods = "epwmss2";
73456012 AM	568	status = "disabled";
9e3269b8 LV	569
	570	ecap2: ecap@48304100 {
	571	compatible = "ti,am4372-ecap","ti,am33xx-ecap";
	572	reg = <0x48304100 0x80>;
	573	ti,hwmods = "ecap2";
	574	status = "disabled";
	575	};
	576
	577	ehrpwm2: ehrpwm@48304200 {
	578	compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
	579	reg = <0x48304200 0x80>;
	580	ti,hwmods = "ehrpwm2";
	581	status = "disabled";
	582	};
73456012 AM	583	};
	584
	585	epwmss3: epwmss@48306000 {
	586	compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
	587	reg = <0x48306000 0x10>;
9e3269b8 LV	588	#address-cells = <1>;
	589	#size-cells = <1>;
	590	ranges;
73456012 AM	591	ti,hwmods = "epwmss3";
73456012 AM	592	status = "disabled";
9e3269b8 LV	593
	594	ehrpwm3: ehrpwm@48306200 {
	595	compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
	596	reg = <0x48306200 0x80>;
	597	ti,hwmods = "ehrpwm3";
	598	status = "disabled";
	599	};
73456012 AM	600	};
	601
	602	epwmss4: epwmss@48308000 {
	603	compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
	604	reg = <0x48308000 0x10>;
9e3269b8 LV	605	#address-cells = <1>;
	606	#size-cells = <1>;
	607	ranges;
73456012 AM	608	ti,hwmods = "epwmss4";
73456012 AM	609	status = "disabled";
9e3269b8 LV	610
	611	ehrpwm4: ehrpwm@48308200 {
	612	compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
	613	reg = <0x48308200 0x80>;
	614	ti,hwmods = "ehrpwm4";
	615	status = "disabled";
	616	};
73456012 AM	617	};
	618
	619	epwmss5: epwmss@4830a000 {
	620	compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
	621	reg = <0x4830a000 0x10>;
9e3269b8 LV	622	#address-cells = <1>;
	623	#size-cells = <1>;
	624	ranges;
73456012 AM	625	ti,hwmods = "epwmss5";
73456012 AM	626	status = "disabled";
9e3269b8 LV	627
	628	ehrpwm5: ehrpwm@4830a200 {
	629	compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
	630	reg = <0x4830a200 0x80>;
	631	ti,hwmods = "ehrpwm5";
	632	status = "disabled";
	633	};
	634	};
	635
	636	sham: sham@53100000 {
	637	compatible = "ti,omap5-sham";
	638	ti,hwmods = "sham";
	639	reg = <0x53100000 0x300>;
	640	dmas = <&edma 36>;
	641	dma-names = "rx";
	642	interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
6cfd8117	643	};
6e70a510 JF	644
	645	aes: aes@53501000 {
	646	compatible = "ti,omap4-aes";
	647	ti,hwmods = "aes";
	648	reg = <0x53501000 0xa0>;
	649	interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
9e3269b8 LV	650	dmas = <&edma 6
	651	&edma 5>;
	652	dma-names = "tx", "rx";
6e70a510	653	};
099f3a85 JF	654
	655	des: des@53701000 {
	656	compatible = "ti,omap4-des";
	657	ti,hwmods = "des";
	658	reg = <0x53701000 0xa0>;
	659	interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
9e3269b8 LV	660	dmas = <&edma 34
	661	&edma 33>;
	662	dma-names = "tx", "rx";
099f3a85	663	};
9e3269b8	664
b9c95bf4 PU	665	mcasp0: mcasp@48038000 {
	666	compatible = "ti,am33xx-mcasp-audio";
	667	ti,hwmods = "mcasp0";
	668	reg = <0x48038000 0x2000>,
	669	<0x46000000 0x400000>;
	670	reg-names = "mpu", "dat";
	671	interrupts = <80>, <81>;
	672	interrupts-names = "tx", "rx";
	673	status = "disabled";
	674	dmas = <&edma 8>,
	675	<&edma 9>;
	676	dma-names = "tx", "rx";
	677	};
	678
	679	mcasp1: mcasp@4803C000 {
	680	compatible = "ti,am33xx-mcasp-audio";
	681	ti,hwmods = "mcasp1";
	682	reg = <0x4803C000 0x2000>,
	683	<0x46400000 0x400000>;
	684	reg-names = "mpu", "dat";
	685	interrupts = <82>, <83>;
	686	interrupts-names = "tx", "rx";
	687	status = "disabled";
	688	dmas = <&edma 10>,
	689	<&edma 11>;
	690	dma-names = "tx", "rx";
	691	};
6cfd8117 AM	692	};
6cfd8117 AM	693	};
6a679208 TK	694
6a679208 TK	695	/include/ "am43xx-clocks.dtsi"