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DT: omap4/5: add binding for the wake-up generator
[deliverable/linux.git] / arch / arm / boot / dts / am4372.dtsi
CommitLineData
6cfd8117
AM		 1/*
2 * Device Tree Source for AM4372 SoC
3 *
4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
d2885dbb 11#include <dt-bindings/gpio/gpio.h>
6cfd8117
AM		 12#include <dt-bindings/interrupt-controller/arm-gic.h>
13
14#include "skeleton.dtsi"
15
16/ {
17 compatible = "ti,am4372", "ti,am43";
18 interrupt-parent = <&gic>;
19
20
21 aliases {
6a968678
NM		 22 i2c0 = &i2c0;
23 i2c1 = &i2c1;
24 i2c2 = &i2c2;
6cfd8117 25 serial0 = &uart0;
9e3269b8
LV		 26 ethernet0 = &cpsw_emac0;
27 ethernet1 = &cpsw_emac1;
6cfd8117
AM		 28 };
29
30 cpus {
738c7409
AM		 31 #address-cells = <1>;
32 #size-cells = <0>;
08ecb28a 33 cpu: cpu@0 {
6cfd8117 34 compatible = "arm,cortex-a9";
738c7409
AM		 35 device_type = "cpu";
36 reg = <0>;
8d766fa2
NM		 37
38 clocks = <&dpll_mpu_ck>;
39 clock-names = "cpu";
40
41 clock-latency = <300000>; /* From omap-cpufreq driver */
6cfd8117
AM		 42 };
43 };
44
45 gic: interrupt-controller@48241000 {
46 compatible = "arm,cortex-a9-gic";
47 interrupt-controller;
48 #interrupt-cells = <3>;
49 reg = <0x48241000 0x1000>,
50 <0x48240100 0x0100>;
51 };
52
9e3269b8
LV		 53 l2-cache-controller@48242000 {
54 compatible = "arm,pl310-cache";
55 reg = <0x48242000 0x1000>;
56 cache-unified;
57 cache-level = <2>;
58 };
59
3a51dec1
RQ		 60 am43xx_control_module: control_module@4a002000 {
61 compatible = "syscon";
62 reg = <0x44e10000 0x7f4>;
63 };
64
9e3269b8 65 am43xx_pinmux: pinmux@44e10800 {
d8c5bab6 66 compatible = "ti,am437-padconf", "pinctrl-single";
9e3269b8
LV		 67 reg = <0x44e10800 0x31c>;
68 #address-cells = <1>;
69 #size-cells = <0>;
d8c5bab6
NM		 70 #interrupt-cells = <1>;
71 interrupt-controller;
9e3269b8
LV		 72 pinctrl-single,register-width = <32>;
73 pinctrl-single,function-mask = <0xffffffff>;
74 };
75
6cfd8117 76 ocp {
2eeddb8a 77 compatible = "ti,am4372-l3-noc", "simple-bus";
6cfd8117
AM		 78 #address-cells = <1>;
79 #size-cells = <1>;
80 ranges;
9e3269b8 81 ti,hwmods = "l3_main";
2eeddb8a
AM		 82 reg = <0x44000000 0x400000
83 0x44800000 0x400000>;
84 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
85 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
9e3269b8 86
6a679208
TK		 87 prcm: prcm@44df0000 {
88 compatible = "ti,am4-prcm";
89 reg = <0x44df0000 0x11000>;
90
91 prcm_clocks: clocks {
92 #address-cells = <1>;
93 #size-cells = <0>;
94 };
95
96 prcm_clockdomains: clockdomains {
97 };
98 };
99
100 scrm: scrm@44e10000 {
101 compatible = "ti,am4-scrm";
102 reg = <0x44e10000 0x2000>;
103
104 scrm_clocks: clocks {
105 #address-cells = <1>;
106 #size-cells = <0>;
107 };
108
109 scrm_clockdomains: clockdomains {
110 };
111 };
112
9e3269b8
LV		 113 edma: edma@49000000 {
114 compatible = "ti,edma3";
115 ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2";
116 reg = <0x49000000 0x10000>,
117 <0x44e10f90 0x10>;
118 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
119 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
120 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
121 #dma-cells = <1>;
9e3269b8 122 };
6cfd8117
AM		 123
124 uart0: serial@44e09000 {
125 compatible = "ti,am4372-uart","ti,omap2-uart";
126 reg = <0x44e09000 0x2000>;
127 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
73456012
AM		 128 ti,hwmods = "uart1";
129 };
130
131 uart1: serial@48022000 {
132 compatible = "ti,am4372-uart","ti,omap2-uart";
133 reg = <0x48022000 0x2000>;
134 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
135 ti,hwmods = "uart2";
136 status = "disabled";
137 };
138
139 uart2: serial@48024000 {
140 compatible = "ti,am4372-uart","ti,omap2-uart";
141 reg = <0x48024000 0x2000>;
142 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
143 ti,hwmods = "uart3";
144 status = "disabled";
145 };
146
147 uart3: serial@481a6000 {
148 compatible = "ti,am4372-uart","ti,omap2-uart";
149 reg = <0x481a6000 0x2000>;
150 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
151 ti,hwmods = "uart4";
152 status = "disabled";
153 };
154
155 uart4: serial@481a8000 {
156 compatible = "ti,am4372-uart","ti,omap2-uart";
157 reg = <0x481a8000 0x2000>;
158 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
159 ti,hwmods = "uart5";
160 status = "disabled";
161 };
162
163 uart5: serial@481aa000 {
164 compatible = "ti,am4372-uart","ti,omap2-uart";
165 reg = <0x481aa000 0x2000>;
166 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
167 ti,hwmods = "uart6";
168 status = "disabled";
6cfd8117
AM		 169 };
170
9e3269b8
LV		 171 mailbox: mailbox@480C8000 {
172 compatible = "ti,omap4-mailbox";
173 reg = <0x480C8000 0x200>;
174 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
175 ti,hwmods = "mailbox";
24df0453 176 #mbox-cells = <1>;
9e3269b8
LV		 177 ti,mbox-num-users = <4>;
178 ti,mbox-num-fifos = <8>;
d27704d1
SA		 179 mbox_wkupm3: wkup_m3 {
180 ti,mbox-tx = <0 0 0>;
181 ti,mbox-rx = <0 0 3>;
182 };
9e3269b8
LV		 183 };
184
6cfd8117
AM		 185 timer1: timer@44e31000 {
186 compatible = "ti,am4372-timer-1ms","ti,am335x-timer-1ms";
187 reg = <0x44e31000 0x400>;
188 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
189 ti,timer-alwon;
73456012 190 ti,hwmods = "timer1";
6cfd8117
AM		 191 };
192
193 timer2: timer@48040000 {
194 compatible = "ti,am4372-timer","ti,am335x-timer";
195 reg = <0x48040000 0x400>;
196 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
73456012
AM		 197 ti,hwmods = "timer2";
198 };
199
200 timer3: timer@48042000 {
201 compatible = "ti,am4372-timer","ti,am335x-timer";
202 reg = <0x48042000 0x400>;
203 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
204 ti,hwmods = "timer3";
205 status = "disabled";
206 };
207
208 timer4: timer@48044000 {
209 compatible = "ti,am4372-timer","ti,am335x-timer";
210 reg = <0x48044000 0x400>;
211 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
212 ti,timer-pwm;
213 ti,hwmods = "timer4";
214 status = "disabled";
215 };
216
217 timer5: timer@48046000 {
218 compatible = "ti,am4372-timer","ti,am335x-timer";
219 reg = <0x48046000 0x400>;
220 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
221 ti,timer-pwm;
222 ti,hwmods = "timer5";
223 status = "disabled";
224 };
225
226 timer6: timer@48048000 {
227 compatible = "ti,am4372-timer","ti,am335x-timer";
228 reg = <0x48048000 0x400>;
229 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
230 ti,timer-pwm;
231 ti,hwmods = "timer6";
232 status = "disabled";
233 };
234
235 timer7: timer@4804a000 {
236 compatible = "ti,am4372-timer","ti,am335x-timer";
237 reg = <0x4804a000 0x400>;
238 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
239 ti,timer-pwm;
240 ti,hwmods = "timer7";
241 status = "disabled";
242 };
243
244 timer8: timer@481c1000 {
245 compatible = "ti,am4372-timer","ti,am335x-timer";
246 reg = <0x481c1000 0x400>;
247 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
248 ti,hwmods = "timer8";
249 status = "disabled";
250 };
251
252 timer9: timer@4833d000 {
253 compatible = "ti,am4372-timer","ti,am335x-timer";
254 reg = <0x4833d000 0x400>;
255 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
256 ti,hwmods = "timer9";
257 status = "disabled";
258 };
259
260 timer10: timer@4833f000 {
261 compatible = "ti,am4372-timer","ti,am335x-timer";
262 reg = <0x4833f000 0x400>;
263 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
264 ti,hwmods = "timer10";
265 status = "disabled";
266 };
267
268 timer11: timer@48341000 {
269 compatible = "ti,am4372-timer","ti,am335x-timer";
270 reg = <0x48341000 0x400>;
271 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
272 ti,hwmods = "timer11";
273 status = "disabled";
6cfd8117
AM		 274 };
275
276 counter32k: counter@44e86000 {
277 compatible = "ti,am4372-counter32k","ti,omap-counter32k";
278 reg = <0x44e86000 0x40>;
73456012
AM		 279 ti,hwmods = "counter_32k";
280 };
281
08ecb28a 282 rtc: rtc@44e3e000 {
73456012
AM		 283 compatible = "ti,am4372-rtc","ti,da830-rtc";
284 reg = <0x44e3e000 0x1000>;
285 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH
286 GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
287 ti,hwmods = "rtc";
288 status = "disabled";
289 };
290
08ecb28a 291 wdt: wdt@44e35000 {
73456012
AM		 292 compatible = "ti,am4372-wdt","ti,omap3-wdt";
293 reg = <0x44e35000 0x1000>;
294 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
295 ti,hwmods = "wd_timer2";
73456012
AM		 296 };
297
298 gpio0: gpio@44e07000 {
299 compatible = "ti,am4372-gpio","ti,omap4-gpio";
300 reg = <0x44e07000 0x1000>;
301 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
302 gpio-controller;
303 #gpio-cells = <2>;
304 interrupt-controller;
305 #interrupt-cells = <2>;
306 ti,hwmods = "gpio1";
307 status = "disabled";
308 };
309
310 gpio1: gpio@4804c000 {
311 compatible = "ti,am4372-gpio","ti,omap4-gpio";
312 reg = <0x4804c000 0x1000>;
313 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
314 gpio-controller;
315 #gpio-cells = <2>;
316 interrupt-controller;
317 #interrupt-cells = <2>;
318 ti,hwmods = "gpio2";
319 status = "disabled";
320 };
321
322 gpio2: gpio@481ac000 {
323 compatible = "ti,am4372-gpio","ti,omap4-gpio";
324 reg = <0x481ac000 0x1000>;
325 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
326 gpio-controller;
327 #gpio-cells = <2>;
328 interrupt-controller;
329 #interrupt-cells = <2>;
330 ti,hwmods = "gpio3";
331 status = "disabled";
332 };
333
334 gpio3: gpio@481ae000 {
335 compatible = "ti,am4372-gpio","ti,omap4-gpio";
336 reg = <0x481ae000 0x1000>;
337 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
338 gpio-controller;
339 #gpio-cells = <2>;
340 interrupt-controller;
341 #interrupt-cells = <2>;
342 ti,hwmods = "gpio4";
343 status = "disabled";
344 };
345
346 gpio4: gpio@48320000 {
347 compatible = "ti,am4372-gpio","ti,omap4-gpio";
348 reg = <0x48320000 0x1000>;
349 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
350 gpio-controller;
351 #gpio-cells = <2>;
352 interrupt-controller;
353 #interrupt-cells = <2>;
354 ti,hwmods = "gpio5";
355 status = "disabled";
356 };
357
358 gpio5: gpio@48322000 {
359 compatible = "ti,am4372-gpio","ti,omap4-gpio";
360 reg = <0x48322000 0x1000>;
361 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
362 gpio-controller;
363 #gpio-cells = <2>;
364 interrupt-controller;
365 #interrupt-cells = <2>;
366 ti,hwmods = "gpio6";
367 status = "disabled";
368 };
369
fd4a8a68
SA		 370 hwspinlock: spinlock@480ca000 {
371 compatible = "ti,omap4-hwspinlock";
372 reg = <0x480ca000 0x1000>;
373 ti,hwmods = "spinlock";
374 #hwlock-cells = <1>;
375 };
376
73456012
AM		 377 i2c0: i2c@44e0b000 {
378 compatible = "ti,am4372-i2c","ti,omap4-i2c";
379 reg = <0x44e0b000 0x1000>;
380 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
381 ti,hwmods = "i2c1";
382 #address-cells = <1>;
383 #size-cells = <0>;
384 status = "disabled";
385 };
386
387 i2c1: i2c@4802a000 {
388 compatible = "ti,am4372-i2c","ti,omap4-i2c";
389 reg = <0x4802a000 0x1000>;
390 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
391 ti,hwmods = "i2c2";
392 #address-cells = <1>;
393 #size-cells = <0>;
394 status = "disabled";
395 };
396
397 i2c2: i2c@4819c000 {
398 compatible = "ti,am4372-i2c","ti,omap4-i2c";
399 reg = <0x4819c000 0x1000>;
400 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
401 ti,hwmods = "i2c3";
402 #address-cells = <1>;
403 #size-cells = <0>;
404 status = "disabled";
405 };
406
407 spi0: spi@48030000 {
408 compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
409 reg = <0x48030000 0x400>;
410 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
411 ti,hwmods = "spi0";
412 #address-cells = <1>;
413 #size-cells = <0>;
414 status = "disabled";
415 };
416
9e3269b8
LV		 417 mmc1: mmc@48060000 {
418 compatible = "ti,omap4-hsmmc";
419 reg = <0x48060000 0x1000>;
420 ti,hwmods = "mmc1";
421 ti,dual-volt;
422 ti,needs-special-reset;
423 dmas = <&edma 24
424 &edma 25>;
425 dma-names = "tx", "rx";
426 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
427 status = "disabled";
428 };
429
430 mmc2: mmc@481d8000 {
431 compatible = "ti,omap4-hsmmc";
432 reg = <0x481d8000 0x1000>;
433 ti,hwmods = "mmc2";
434 ti,needs-special-reset;
435 dmas = <&edma 2
436 &edma 3>;
437 dma-names = "tx", "rx";
438 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
439 status = "disabled";
440 };
441
442 mmc3: mmc@47810000 {
443 compatible = "ti,omap4-hsmmc";
444 reg = <0x47810000 0x1000>;
445 ti,hwmods = "mmc3";
446 ti,needs-special-reset;
447 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
448 status = "disabled";
449 };
450
73456012
AM		 451 spi1: spi@481a0000 {
452 compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
453 reg = <0x481a0000 0x400>;
454 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
455 ti,hwmods = "spi1";
456 #address-cells = <1>;
457 #size-cells = <0>;
458 status = "disabled";
459 };
460
461 spi2: spi@481a2000 {
462 compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
463 reg = <0x481a2000 0x400>;
464 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
465 ti,hwmods = "spi2";
466 #address-cells = <1>;
467 #size-cells = <0>;
468 status = "disabled";
469 };
470
471 spi3: spi@481a4000 {
472 compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
473 reg = <0x481a4000 0x400>;
474 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
475 ti,hwmods = "spi3";
476 #address-cells = <1>;
477 #size-cells = <0>;
478 status = "disabled";
479 };
480
481 spi4: spi@48345000 {
482 compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
483 reg = <0x48345000 0x400>;
484 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
485 ti,hwmods = "spi4";
486 #address-cells = <1>;
487 #size-cells = <0>;
488 status = "disabled";
489 };
490
491 mac: ethernet@4a100000 {
492 compatible = "ti,am4372-cpsw","ti,cpsw";
493 reg = <0x4a100000 0x800
494 0x4a101200 0x100>;
495 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH
496 GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH
497 GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH
498 GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
9e3269b8
LV		 499 #address-cells = <1>;
500 #size-cells = <1>;
73456012 501 ti,hwmods = "cpgmac0";
de21b26e
GC		 502 clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>;
503 clock-names = "fck", "cpts";
73456012 504 status = "disabled";
9e3269b8
LV		 505 cpdma_channels = <8>;
506 ale_entries = <1024>;
507 bd_ram_size = <0x2000>;
508 no_bd_ram = <0>;
509 rx_descs = <64>;
510 mac_control = <0x20>;
511 slaves = <2>;
512 active_slave = <0>;
513 cpts_clock_mult = <0x80000000>;
514 cpts_clock_shift = <29>;
515 ranges;
516
517 davinci_mdio: mdio@4a101000 {
518 compatible = "ti,am4372-mdio","ti,davinci_mdio";
519 reg = <0x4a101000 0x100>;
520 #address-cells = <1>;
521 #size-cells = <0>;
522 ti,hwmods = "davinci_mdio";
523 bus_freq = <1000000>;
524 status = "disabled";
525 };
526
527 cpsw_emac0: slave@4a100200 {
528 /* Filled in by U-Boot */
529 mac-address = [ 00 00 00 00 00 00 ];
530 };
531
532 cpsw_emac1: slave@4a100300 {
533 /* Filled in by U-Boot */
534 mac-address = [ 00 00 00 00 00 00 ];
535 };
a9682cfb
M		 536
537 phy_sel: cpsw-phy-sel@44e10650 {
538 compatible = "ti,am43xx-cpsw-phy-sel";
539 reg= <0x44e10650 0x4>;
540 reg-names = "gmii-sel";
541 };
73456012
AM		 542 };
543
544 epwmss0: epwmss@48300000 {
545 compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
546 reg = <0x48300000 0x10>;
9e3269b8
LV		 547 #address-cells = <1>;
548 #size-cells = <1>;
549 ranges;
73456012
AM		 550 ti,hwmods = "epwmss0";
551 status = "disabled";
9e3269b8
LV		 552
553 ecap0: ecap@48300100 {
554 compatible = "ti,am4372-ecap","ti,am33xx-ecap";
aa842305 555 #pwm-cells = <3>;
9e3269b8
LV		 556 reg = <0x48300100 0x80>;
557 ti,hwmods = "ecap0";
558 status = "disabled";
559 };
560
561 ehrpwm0: ehrpwm@48300200 {
562 compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
aa842305 563 #pwm-cells = <3>;
9e3269b8
LV		 564 reg = <0x48300200 0x80>;
565 ti,hwmods = "ehrpwm0";
566 status = "disabled";
567 };
73456012
AM		 568 };
569
570 epwmss1: epwmss@48302000 {
571 compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
572 reg = <0x48302000 0x10>;
9e3269b8
LV		 573 #address-cells = <1>;
574 #size-cells = <1>;
575 ranges;
73456012
AM		 576 ti,hwmods = "epwmss1";
577 status = "disabled";
9e3269b8
LV		 578
579 ecap1: ecap@48302100 {
580 compatible = "ti,am4372-ecap","ti,am33xx-ecap";
aa842305 581 #pwm-cells = <3>;
9e3269b8
LV		 582 reg = <0x48302100 0x80>;
583 ti,hwmods = "ecap1";
584 status = "disabled";
585 };
586
587 ehrpwm1: ehrpwm@48302200 {
588 compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
aa842305 589 #pwm-cells = <3>;
9e3269b8
LV		 590 reg = <0x48302200 0x80>;
591 ti,hwmods = "ehrpwm1";
592 status = "disabled";
593 };
73456012
AM		 594 };
595
596 epwmss2: epwmss@48304000 {
597 compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
598 reg = <0x48304000 0x10>;
9e3269b8
LV		 599 #address-cells = <1>;
600 #size-cells = <1>;
601 ranges;
73456012
AM		 602 ti,hwmods = "epwmss2";
603 status = "disabled";
9e3269b8
LV		 604
605 ecap2: ecap@48304100 {
606 compatible = "ti,am4372-ecap","ti,am33xx-ecap";
aa842305 607 #pwm-cells = <3>;
9e3269b8
LV		 608 reg = <0x48304100 0x80>;
609 ti,hwmods = "ecap2";
610 status = "disabled";
611 };
612
613 ehrpwm2: ehrpwm@48304200 {
614 compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
aa842305 615 #pwm-cells = <3>;
9e3269b8
LV		 616 reg = <0x48304200 0x80>;
617 ti,hwmods = "ehrpwm2";
618 status = "disabled";
619 };
73456012
AM		 620 };
621
622 epwmss3: epwmss@48306000 {
623 compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
624 reg = <0x48306000 0x10>;
9e3269b8
LV		 625 #address-cells = <1>;
626 #size-cells = <1>;
627 ranges;
73456012
AM		 628 ti,hwmods = "epwmss3";
629 status = "disabled";
9e3269b8
LV		 630
631 ehrpwm3: ehrpwm@48306200 {
632 compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
aa842305 633 #pwm-cells = <3>;
9e3269b8
LV		 634 reg = <0x48306200 0x80>;
635 ti,hwmods = "ehrpwm3";
636 status = "disabled";
637 };
73456012
AM		 638 };
639
640 epwmss4: epwmss@48308000 {
641 compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
642 reg = <0x48308000 0x10>;
9e3269b8
LV		 643 #address-cells = <1>;
644 #size-cells = <1>;
645 ranges;
73456012
AM		 646 ti,hwmods = "epwmss4";
647 status = "disabled";
9e3269b8
LV		 648
649 ehrpwm4: ehrpwm@48308200 {
650 compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
aa842305 651 #pwm-cells = <3>;
9e3269b8
LV		 652 reg = <0x48308200 0x80>;
653 ti,hwmods = "ehrpwm4";
654 status = "disabled";
655 };
73456012
AM		 656 };
657
658 epwmss5: epwmss@4830a000 {
659 compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
660 reg = <0x4830a000 0x10>;
9e3269b8
LV		 661 #address-cells = <1>;
662 #size-cells = <1>;
663 ranges;
73456012
AM		 664 ti,hwmods = "epwmss5";
665 status = "disabled";
9e3269b8
LV		 666
667 ehrpwm5: ehrpwm@4830a200 {
668 compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
aa842305 669 #pwm-cells = <3>;
9e3269b8
LV		 670 reg = <0x4830a200 0x80>;
671 ti,hwmods = "ehrpwm5";
672 status = "disabled";
673 };
674 };
675
0f39f7b9
V		 676 tscadc: tscadc@44e0d000 {
677 compatible = "ti,am3359-tscadc";
678 reg = <0x44e0d000 0x1000>;
679 ti,hwmods = "adc_tsc";
680 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
681 clocks = <&adc_tsc_fck>;
682 clock-names = "fck";
683 status = "disabled";
684
685 tsc {
686 compatible = "ti,am3359-tsc";
687 };
688
689 adc {
690 #io-channel-cells = <1>;
691 compatible = "ti,am3359-adc";
692 };
693
694 };
695
9e3269b8
LV		 696 sham: sham@53100000 {
697 compatible = "ti,omap5-sham";
698 ti,hwmods = "sham";
699 reg = <0x53100000 0x300>;
700 dmas = <&edma 36>;
701 dma-names = "rx";
702 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
6cfd8117 703 };
6e70a510
JF		 704
705 aes: aes@53501000 {
706 compatible = "ti,omap4-aes";
707 ti,hwmods = "aes";
708 reg = <0x53501000 0xa0>;
709 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
9e3269b8
LV		 710 dmas = <&edma 6
711 &edma 5>;
712 dma-names = "tx", "rx";
6e70a510 713 };
099f3a85
JF		 714
715 des: des@53701000 {
716 compatible = "ti,omap4-des";
717 ti,hwmods = "des";
718 reg = <0x53701000 0xa0>;
719 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
9e3269b8
LV		 720 dmas = <&edma 34
721 &edma 33>;
722 dma-names = "tx", "rx";
099f3a85 723 };
9e3269b8 724
b9c95bf4
PU		 725 mcasp0: mcasp@48038000 {
726 compatible = "ti,am33xx-mcasp-audio";
727 ti,hwmods = "mcasp0";
728 reg = <0x48038000 0x2000>,
729 <0x46000000 0x400000>;
730 reg-names = "mpu", "dat";
731 interrupts = <80>, <81>;
ae107d06 732 interrupt-names = "tx", "rx";
b9c95bf4
PU		 733 status = "disabled";
734 dmas = <&edma 8>,
735 <&edma 9>;
736 dma-names = "tx", "rx";
737 };
738
739 mcasp1: mcasp@4803C000 {
740 compatible = "ti,am33xx-mcasp-audio";
741 ti,hwmods = "mcasp1";
742 reg = <0x4803C000 0x2000>,
743 <0x46400000 0x400000>;
744 reg-names = "mpu", "dat";
745 interrupts = <82>, <83>;
ae107d06 746 interrupt-names = "tx", "rx";
b9c95bf4
PU		 747 status = "disabled";
748 dmas = <&edma 10>,
749 <&edma 11>;
750 dma-names = "tx", "rx";
751 };
f68e355c
PG		 752
753 elm: elm@48080000 {
754 compatible = "ti,am3352-elm";
755 reg = <0x48080000 0x2000>;
756 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
757 ti,hwmods = "elm";
758 clocks = <&l4ls_gclk>;
759 clock-names = "fck";
760 status = "disabled";
761 };
762
763 gpmc: gpmc@50000000 {
764 compatible = "ti,am3352-gpmc";
765 ti,hwmods = "gpmc";
766 clocks = <&l3s_gclk>;
767 clock-names = "fck";
768 reg = <0x50000000 0x2000>;
769 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
770 gpmc,num-cs = <7>;
771 gpmc,num-waitpins = <2>;
772 #address-cells = <2>;
773 #size-cells = <1>;
774 status = "disabled";
775 };
a0ae47ea
GC		 776
777 am43xx_control_usb2phy1: control-phy@44e10620 {
778 compatible = "ti,control-phy-usb2-am437";
779 reg = <0x44e10620 0x4>;
780 reg-names = "power";
781 };
782
783 am43xx_control_usb2phy2: control-phy@0x44e10628 {
784 compatible = "ti,control-phy-usb2-am437";
785 reg = <0x44e10628 0x4>;
786 reg-names = "power";
787 };
788
789 ocp2scp0: ocp2scp@483a8000 {
790 compatible = "ti,omap-ocp2scp";
791 #address-cells = <1>;
792 #size-cells = <1>;
793 ranges;
794 ti,hwmods = "ocp2scp0";
795
796 usb2_phy1: phy@483a8000 {
797 compatible = "ti,am437x-usb2";
798 reg = <0x483a8000 0x8000>;
799 ctrl-module = <&am43xx_control_usb2phy1>;
800 clocks = <&usb_phy0_always_on_clk32k>,
801 <&usb_otg_ss0_refclk960m>;
802 clock-names = "wkupclk", "refclk";
803 #phy-cells = <0>;
804 status = "disabled";
805 };
806 };
807
808 ocp2scp1: ocp2scp@483e8000 {
809 compatible = "ti,omap-ocp2scp";
810 #address-cells = <1>;
811 #size-cells = <1>;
812 ranges;
813 ti,hwmods = "ocp2scp1";
814
815 usb2_phy2: phy@483e8000 {
816 compatible = "ti,am437x-usb2";
817 reg = <0x483e8000 0x8000>;
818 ctrl-module = <&am43xx_control_usb2phy2>;
819 clocks = <&usb_phy1_always_on_clk32k>,
820 <&usb_otg_ss1_refclk960m>;
821 clock-names = "wkupclk", "refclk";
822 #phy-cells = <0>;
823 status = "disabled";
824 };
825 };
826
827 dwc3_1: omap_dwc3@48380000 {
828 compatible = "ti,am437x-dwc3";
829 ti,hwmods = "usb_otg_ss0";
830 reg = <0x48380000 0x10000>;
831 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
832 #address-cells = <1>;
833 #size-cells = <1>;
834 utmi-mode = <1>;
835 ranges;
836
837 usb1: usb@48390000 {
838 compatible = "synopsys,dwc3";
4b143f0f 839 reg = <0x48390000 0x10000>;
a0ae47ea
GC		 840 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
841 phys = <&usb2_phy1>;
842 phy-names = "usb2-phy";
843 maximum-speed = "high-speed";
844 dr_mode = "otg";
845 status = "disabled";
60f0e628
FB		 846 snps,dis_u3_susphy_quirk;
847 snps,dis_u2_susphy_quirk;
a0ae47ea
GC		 848 };
849 };
850
851 dwc3_2: omap_dwc3@483c0000 {
852 compatible = "ti,am437x-dwc3";
853 ti,hwmods = "usb_otg_ss1";
854 reg = <0x483c0000 0x10000>;
855 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
856 #address-cells = <1>;
857 #size-cells = <1>;
858 utmi-mode = <1>;
859 ranges;
860
861 usb2: usb@483d0000 {
862 compatible = "synopsys,dwc3";
4b143f0f 863 reg = <0x483d0000 0x10000>;
a0ae47ea
GC		 864 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
865 phys = <&usb2_phy2>;
866 phy-names = "usb2-phy";
867 maximum-speed = "high-speed";
868 dr_mode = "otg";
869 status = "disabled";
60f0e628
FB		 870 snps,dis_u3_susphy_quirk;
871 snps,dis_u2_susphy_quirk;
a0ae47ea
GC		 872 };
873 };
2a1a5043
SP		 874
875 qspi: qspi@47900000 {
876 compatible = "ti,am4372-qspi";
877 reg = <0x47900000 0x100>;
878 #address-cells = <1>;
879 #size-cells = <0>;
880 ti,hwmods = "qspi";
881 interrupts = <0 138 0x4>;
882 num-cs = <4>;
883 status = "disabled";
884 };
741cac5f
SP		 885
886 hdq: hdq@48347000 {
887 compatible = "ti,am43xx-hdq";
888 reg = <0x48347000 0x1000>;
889 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
890 clocks = <&func_12m_clk>;
891 clock-names = "fck";
892 ti,hwmods = "hdq1w";
893 status = "disabled";
894 };
8c793367
SP		 895
896 dss: dss@4832a000 {
897 compatible = "ti,omap3-dss";
898 reg = <0x4832a000 0x200>;
899 status = "disabled";
900 ti,hwmods = "dss_core";
901 clocks = <&disp_clk>;
902 clock-names = "fck";
903 #address-cells = <1>;
904 #size-cells = <1>;
905 ranges;
906
08ecb28a 907 dispc: dispc@4832a400 {
8c793367
SP		 908 compatible = "ti,omap3-dispc";
909 reg = <0x4832a400 0x400>;
910 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
911 ti,hwmods = "dss_dispc";
912 clocks = <&disp_clk>;
913 clock-names = "fck";
914 };
915
916 rfbi: rfbi@4832a800 {
917 compatible = "ti,omap3-rfbi";
918 reg = <0x4832a800 0x100>;
919 ti,hwmods = "dss_rfbi";
920 clocks = <&disp_clk>;
921 clock-names = "fck";
922 };
923 };
8b9a2810
RN		 924
925 ocmcram: ocmcram@40300000 {
926 compatible = "mmio-sram";
927 reg = <0x40300000 0x40000>; /* 256k */
928 };
9e63b0d4
RQ		 929
930 dcan0: can@481cc000 {
931 compatible = "ti,am4372-d_can", "ti,am3352-d_can";
932 ti,hwmods = "d_can0";
933 clocks = <&dcan0_fck>;
934 clock-names = "fck";
935 reg = <0x481cc000 0x2000>;
936 syscon-raminit = <&am43xx_control_module 0x644 0>;
937 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
938 status = "disabled";
939 };
940
941 dcan1: can@481d0000 {
942 compatible = "ti,am4372-d_can", "ti,am3352-d_can";
943 ti,hwmods = "d_can1";
944 clocks = <&dcan1_fck>;
945 clock-names = "fck";
946 reg = <0x481d0000 0x2000>;
947 syscon-raminit = <&am43xx_control_module 0x644 1>;
948 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
949 status = "disabled";
950 };
9d0df0a6
BP		 951
952 vpfe0: vpfe@48326000 {
953 compatible = "ti,am437x-vpfe";
954 reg = <0x48326000 0x2000>;
955 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
956 ti,hwmods = "vpfe0";
957 status = "disabled";
958 };
959
960 vpfe1: vpfe@48328000 {
961 compatible = "ti,am437x-vpfe";
962 reg = <0x48328000 0x2000>;
963 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
964 ti,hwmods = "vpfe1";
965 status = "disabled";
966 };
6cfd8117
AM		 967 };
968};
6a679208
TK		 969
970/include/ "am43xx-clocks.dtsi"
Linux kernel - Deliverables
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