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ARM: dts: am437x-gp: switch i2c0 to 100KHz
[deliverable/linux.git] / arch / arm / boot / dts / am4372.dtsi
CommitLineData
6cfd8117
AM		 1/*
2 * Device Tree Source for AM4372 SoC
3 *
4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
d2885dbb 11#include <dt-bindings/gpio/gpio.h>
6cfd8117
AM		 12#include <dt-bindings/interrupt-controller/arm-gic.h>
13
14#include "skeleton.dtsi"
15
16/ {
17 compatible = "ti,am4372", "ti,am43";
18 interrupt-parent = <&gic>;
19
20
21 aliases {
6a968678
NM		 22 i2c0 = &i2c0;
23 i2c1 = &i2c1;
24 i2c2 = &i2c2;
6cfd8117 25 serial0 = &uart0;
9e3269b8
LV		 26 ethernet0 = &cpsw_emac0;
27 ethernet1 = &cpsw_emac1;
6cfd8117
AM		 28 };
29
30 cpus {
738c7409
AM		 31 #address-cells = <1>;
32 #size-cells = <0>;
08ecb28a 33 cpu: cpu@0 {
6cfd8117 34 compatible = "arm,cortex-a9";
738c7409
AM		 35 device_type = "cpu";
36 reg = <0>;
8d766fa2
NM		 37
38 clocks = <&dpll_mpu_ck>;
39 clock-names = "cpu";
40
41 clock-latency = <300000>; /* From omap-cpufreq driver */
6cfd8117
AM		 42 };
43 };
44
45 gic: interrupt-controller@48241000 {
46 compatible = "arm,cortex-a9-gic";
47 interrupt-controller;
48 #interrupt-cells = <3>;
49 reg = <0x48241000 0x1000>,
50 <0x48240100 0x0100>;
51 };
52
9e3269b8
LV		 53 l2-cache-controller@48242000 {
54 compatible = "arm,pl310-cache";
55 reg = <0x48242000 0x1000>;
56 cache-unified;
57 cache-level = <2>;
58 };
59
60 am43xx_pinmux: pinmux@44e10800 {
61 compatible = "pinctrl-single";
62 reg = <0x44e10800 0x31c>;
63 #address-cells = <1>;
64 #size-cells = <0>;
65 pinctrl-single,register-width = <32>;
66 pinctrl-single,function-mask = <0xffffffff>;
67 };
68
6cfd8117 69 ocp {
2eeddb8a 70 compatible = "ti,am4372-l3-noc", "simple-bus";
6cfd8117
AM		 71 #address-cells = <1>;
72 #size-cells = <1>;
73 ranges;
9e3269b8 74 ti,hwmods = "l3_main";
2eeddb8a
AM		 75 reg = <0x44000000 0x400000
76 0x44800000 0x400000>;
77 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
78 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
9e3269b8 79
6a679208
TK		 80 prcm: prcm@44df0000 {
81 compatible = "ti,am4-prcm";
82 reg = <0x44df0000 0x11000>;
83
84 prcm_clocks: clocks {
85 #address-cells = <1>;
86 #size-cells = <0>;
87 };
88
89 prcm_clockdomains: clockdomains {
90 };
91 };
92
93 scrm: scrm@44e10000 {
94 compatible = "ti,am4-scrm";
95 reg = <0x44e10000 0x2000>;
96
97 scrm_clocks: clocks {
98 #address-cells = <1>;
99 #size-cells = <0>;
100 };
101
102 scrm_clockdomains: clockdomains {
103 };
104 };
105
9e3269b8
LV		 106 edma: edma@49000000 {
107 compatible = "ti,edma3";
108 ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2";
109 reg = <0x49000000 0x10000>,
110 <0x44e10f90 0x10>;
111 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
112 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
113 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
114 #dma-cells = <1>;
9e3269b8 115 };
6cfd8117
AM		 116
117 uart0: serial@44e09000 {
118 compatible = "ti,am4372-uart","ti,omap2-uart";
119 reg = <0x44e09000 0x2000>;
120 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
73456012
AM		 121 ti,hwmods = "uart1";
122 };
123
124 uart1: serial@48022000 {
125 compatible = "ti,am4372-uart","ti,omap2-uart";
126 reg = <0x48022000 0x2000>;
127 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
128 ti,hwmods = "uart2";
129 status = "disabled";
130 };
131
132 uart2: serial@48024000 {
133 compatible = "ti,am4372-uart","ti,omap2-uart";
134 reg = <0x48024000 0x2000>;
135 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
136 ti,hwmods = "uart3";
137 status = "disabled";
138 };
139
140 uart3: serial@481a6000 {
141 compatible = "ti,am4372-uart","ti,omap2-uart";
142 reg = <0x481a6000 0x2000>;
143 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
144 ti,hwmods = "uart4";
145 status = "disabled";
146 };
147
148 uart4: serial@481a8000 {
149 compatible = "ti,am4372-uart","ti,omap2-uart";
150 reg = <0x481a8000 0x2000>;
151 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
152 ti,hwmods = "uart5";
153 status = "disabled";
154 };
155
156 uart5: serial@481aa000 {
157 compatible = "ti,am4372-uart","ti,omap2-uart";
158 reg = <0x481aa000 0x2000>;
159 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
160 ti,hwmods = "uart6";
161 status = "disabled";
6cfd8117
AM		 162 };
163
9e3269b8
LV		 164 mailbox: mailbox@480C8000 {
165 compatible = "ti,omap4-mailbox";
166 reg = <0x480C8000 0x200>;
167 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
168 ti,hwmods = "mailbox";
169 ti,mbox-num-users = <4>;
170 ti,mbox-num-fifos = <8>;
9e3269b8
LV		 171 };
172
6cfd8117
AM		 173 timer1: timer@44e31000 {
174 compatible = "ti,am4372-timer-1ms","ti,am335x-timer-1ms";
175 reg = <0x44e31000 0x400>;
176 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
177 ti,timer-alwon;
73456012 178 ti,hwmods = "timer1";
6cfd8117
AM		 179 };
180
181 timer2: timer@48040000 {
182 compatible = "ti,am4372-timer","ti,am335x-timer";
183 reg = <0x48040000 0x400>;
184 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
73456012
AM		 185 ti,hwmods = "timer2";
186 };
187
188 timer3: timer@48042000 {
189 compatible = "ti,am4372-timer","ti,am335x-timer";
190 reg = <0x48042000 0x400>;
191 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
192 ti,hwmods = "timer3";
193 status = "disabled";
194 };
195
196 timer4: timer@48044000 {
197 compatible = "ti,am4372-timer","ti,am335x-timer";
198 reg = <0x48044000 0x400>;
199 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
200 ti,timer-pwm;
201 ti,hwmods = "timer4";
202 status = "disabled";
203 };
204
205 timer5: timer@48046000 {
206 compatible = "ti,am4372-timer","ti,am335x-timer";
207 reg = <0x48046000 0x400>;
208 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
209 ti,timer-pwm;
210 ti,hwmods = "timer5";
211 status = "disabled";
212 };
213
214 timer6: timer@48048000 {
215 compatible = "ti,am4372-timer","ti,am335x-timer";
216 reg = <0x48048000 0x400>;
217 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
218 ti,timer-pwm;
219 ti,hwmods = "timer6";
220 status = "disabled";
221 };
222
223 timer7: timer@4804a000 {
224 compatible = "ti,am4372-timer","ti,am335x-timer";
225 reg = <0x4804a000 0x400>;
226 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
227 ti,timer-pwm;
228 ti,hwmods = "timer7";
229 status = "disabled";
230 };
231
232 timer8: timer@481c1000 {
233 compatible = "ti,am4372-timer","ti,am335x-timer";
234 reg = <0x481c1000 0x400>;
235 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
236 ti,hwmods = "timer8";
237 status = "disabled";
238 };
239
240 timer9: timer@4833d000 {
241 compatible = "ti,am4372-timer","ti,am335x-timer";
242 reg = <0x4833d000 0x400>;
243 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
244 ti,hwmods = "timer9";
245 status = "disabled";
246 };
247
248 timer10: timer@4833f000 {
249 compatible = "ti,am4372-timer","ti,am335x-timer";
250 reg = <0x4833f000 0x400>;
251 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
252 ti,hwmods = "timer10";
253 status = "disabled";
254 };
255
256 timer11: timer@48341000 {
257 compatible = "ti,am4372-timer","ti,am335x-timer";
258 reg = <0x48341000 0x400>;
259 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
260 ti,hwmods = "timer11";
261 status = "disabled";
6cfd8117
AM		 262 };
263
264 counter32k: counter@44e86000 {
265 compatible = "ti,am4372-counter32k","ti,omap-counter32k";
266 reg = <0x44e86000 0x40>;
73456012
AM		 267 ti,hwmods = "counter_32k";
268 };
269
08ecb28a 270 rtc: rtc@44e3e000 {
73456012
AM		 271 compatible = "ti,am4372-rtc","ti,da830-rtc";
272 reg = <0x44e3e000 0x1000>;
273 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH
274 GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
275 ti,hwmods = "rtc";
276 status = "disabled";
277 };
278
08ecb28a 279 wdt: wdt@44e35000 {
73456012
AM		 280 compatible = "ti,am4372-wdt","ti,omap3-wdt";
281 reg = <0x44e35000 0x1000>;
282 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
283 ti,hwmods = "wd_timer2";
73456012
AM		 284 };
285
286 gpio0: gpio@44e07000 {
287 compatible = "ti,am4372-gpio","ti,omap4-gpio";
288 reg = <0x44e07000 0x1000>;
289 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
290 gpio-controller;
291 #gpio-cells = <2>;
292 interrupt-controller;
293 #interrupt-cells = <2>;
294 ti,hwmods = "gpio1";
295 status = "disabled";
296 };
297
298 gpio1: gpio@4804c000 {
299 compatible = "ti,am4372-gpio","ti,omap4-gpio";
300 reg = <0x4804c000 0x1000>;
301 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
302 gpio-controller;
303 #gpio-cells = <2>;
304 interrupt-controller;
305 #interrupt-cells = <2>;
306 ti,hwmods = "gpio2";
307 status = "disabled";
308 };
309
310 gpio2: gpio@481ac000 {
311 compatible = "ti,am4372-gpio","ti,omap4-gpio";
312 reg = <0x481ac000 0x1000>;
313 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
314 gpio-controller;
315 #gpio-cells = <2>;
316 interrupt-controller;
317 #interrupt-cells = <2>;
318 ti,hwmods = "gpio3";
319 status = "disabled";
320 };
321
322 gpio3: gpio@481ae000 {
323 compatible = "ti,am4372-gpio","ti,omap4-gpio";
324 reg = <0x481ae000 0x1000>;
325 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
326 gpio-controller;
327 #gpio-cells = <2>;
328 interrupt-controller;
329 #interrupt-cells = <2>;
330 ti,hwmods = "gpio4";
331 status = "disabled";
332 };
333
334 gpio4: gpio@48320000 {
335 compatible = "ti,am4372-gpio","ti,omap4-gpio";
336 reg = <0x48320000 0x1000>;
337 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
338 gpio-controller;
339 #gpio-cells = <2>;
340 interrupt-controller;
341 #interrupt-cells = <2>;
342 ti,hwmods = "gpio5";
343 status = "disabled";
344 };
345
346 gpio5: gpio@48322000 {
347 compatible = "ti,am4372-gpio","ti,omap4-gpio";
348 reg = <0x48322000 0x1000>;
349 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
350 gpio-controller;
351 #gpio-cells = <2>;
352 interrupt-controller;
353 #interrupt-cells = <2>;
354 ti,hwmods = "gpio6";
355 status = "disabled";
356 };
357
fd4a8a68
SA		 358 hwspinlock: spinlock@480ca000 {
359 compatible = "ti,omap4-hwspinlock";
360 reg = <0x480ca000 0x1000>;
361 ti,hwmods = "spinlock";
362 #hwlock-cells = <1>;
363 };
364
73456012
AM		 365 i2c0: i2c@44e0b000 {
366 compatible = "ti,am4372-i2c","ti,omap4-i2c";
367 reg = <0x44e0b000 0x1000>;
368 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
369 ti,hwmods = "i2c1";
370 #address-cells = <1>;
371 #size-cells = <0>;
372 status = "disabled";
373 };
374
375 i2c1: i2c@4802a000 {
376 compatible = "ti,am4372-i2c","ti,omap4-i2c";
377 reg = <0x4802a000 0x1000>;
378 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
379 ti,hwmods = "i2c2";
380 #address-cells = <1>;
381 #size-cells = <0>;
382 status = "disabled";
383 };
384
385 i2c2: i2c@4819c000 {
386 compatible = "ti,am4372-i2c","ti,omap4-i2c";
387 reg = <0x4819c000 0x1000>;
388 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
389 ti,hwmods = "i2c3";
390 #address-cells = <1>;
391 #size-cells = <0>;
392 status = "disabled";
393 };
394
395 spi0: spi@48030000 {
396 compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
397 reg = <0x48030000 0x400>;
398 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
399 ti,hwmods = "spi0";
400 #address-cells = <1>;
401 #size-cells = <0>;
402 status = "disabled";
403 };
404
9e3269b8
LV		 405 mmc1: mmc@48060000 {
406 compatible = "ti,omap4-hsmmc";
407 reg = <0x48060000 0x1000>;
408 ti,hwmods = "mmc1";
409 ti,dual-volt;
410 ti,needs-special-reset;
411 dmas = <&edma 24
412 &edma 25>;
413 dma-names = "tx", "rx";
414 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
415 status = "disabled";
416 };
417
418 mmc2: mmc@481d8000 {
419 compatible = "ti,omap4-hsmmc";
420 reg = <0x481d8000 0x1000>;
421 ti,hwmods = "mmc2";
422 ti,needs-special-reset;
423 dmas = <&edma 2
424 &edma 3>;
425 dma-names = "tx", "rx";
426 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
427 status = "disabled";
428 };
429
430 mmc3: mmc@47810000 {
431 compatible = "ti,omap4-hsmmc";
432 reg = <0x47810000 0x1000>;
433 ti,hwmods = "mmc3";
434 ti,needs-special-reset;
435 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
436 status = "disabled";
437 };
438
73456012
AM		 439 spi1: spi@481a0000 {
440 compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
441 reg = <0x481a0000 0x400>;
442 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
443 ti,hwmods = "spi1";
444 #address-cells = <1>;
445 #size-cells = <0>;
446 status = "disabled";
447 };
448
449 spi2: spi@481a2000 {
450 compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
451 reg = <0x481a2000 0x400>;
452 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
453 ti,hwmods = "spi2";
454 #address-cells = <1>;
455 #size-cells = <0>;
456 status = "disabled";
457 };
458
459 spi3: spi@481a4000 {
460 compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
461 reg = <0x481a4000 0x400>;
462 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
463 ti,hwmods = "spi3";
464 #address-cells = <1>;
465 #size-cells = <0>;
466 status = "disabled";
467 };
468
469 spi4: spi@48345000 {
470 compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
471 reg = <0x48345000 0x400>;
472 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
473 ti,hwmods = "spi4";
474 #address-cells = <1>;
475 #size-cells = <0>;
476 status = "disabled";
477 };
478
479 mac: ethernet@4a100000 {
480 compatible = "ti,am4372-cpsw","ti,cpsw";
481 reg = <0x4a100000 0x800
482 0x4a101200 0x100>;
483 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH
484 GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH
485 GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH
486 GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
9e3269b8
LV		 487 #address-cells = <1>;
488 #size-cells = <1>;
73456012 489 ti,hwmods = "cpgmac0";
de21b26e
GC		 490 clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>;
491 clock-names = "fck", "cpts";
73456012 492 status = "disabled";
9e3269b8
LV		 493 cpdma_channels = <8>;
494 ale_entries = <1024>;
495 bd_ram_size = <0x2000>;
496 no_bd_ram = <0>;
497 rx_descs = <64>;
498 mac_control = <0x20>;
499 slaves = <2>;
500 active_slave = <0>;
501 cpts_clock_mult = <0x80000000>;
502 cpts_clock_shift = <29>;
503 ranges;
504
505 davinci_mdio: mdio@4a101000 {
506 compatible = "ti,am4372-mdio","ti,davinci_mdio";
507 reg = <0x4a101000 0x100>;
508 #address-cells = <1>;
509 #size-cells = <0>;
510 ti,hwmods = "davinci_mdio";
511 bus_freq = <1000000>;
512 status = "disabled";
513 };
514
515 cpsw_emac0: slave@4a100200 {
516 /* Filled in by U-Boot */
517 mac-address = [ 00 00 00 00 00 00 ];
518 };
519
520 cpsw_emac1: slave@4a100300 {
521 /* Filled in by U-Boot */
522 mac-address = [ 00 00 00 00 00 00 ];
523 };
a9682cfb
M		 524
525 phy_sel: cpsw-phy-sel@44e10650 {
526 compatible = "ti,am43xx-cpsw-phy-sel";
527 reg= <0x44e10650 0x4>;
528 reg-names = "gmii-sel";
529 };
73456012
AM		 530 };
531
532 epwmss0: epwmss@48300000 {
533 compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
534 reg = <0x48300000 0x10>;
9e3269b8
LV		 535 #address-cells = <1>;
536 #size-cells = <1>;
537 ranges;
73456012
AM		 538 ti,hwmods = "epwmss0";
539 status = "disabled";
9e3269b8
LV		 540
541 ecap0: ecap@48300100 {
542 compatible = "ti,am4372-ecap","ti,am33xx-ecap";
aa842305 543 #pwm-cells = <3>;
9e3269b8
LV		 544 reg = <0x48300100 0x80>;
545 ti,hwmods = "ecap0";
546 status = "disabled";
547 };
548
549 ehrpwm0: ehrpwm@48300200 {
550 compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
aa842305 551 #pwm-cells = <3>;
9e3269b8
LV		 552 reg = <0x48300200 0x80>;
553 ti,hwmods = "ehrpwm0";
554 status = "disabled";
555 };
73456012
AM		 556 };
557
558 epwmss1: epwmss@48302000 {
559 compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
560 reg = <0x48302000 0x10>;
9e3269b8
LV		 561 #address-cells = <1>;
562 #size-cells = <1>;
563 ranges;
73456012
AM		 564 ti,hwmods = "epwmss1";
565 status = "disabled";
9e3269b8
LV		 566
567 ecap1: ecap@48302100 {
568 compatible = "ti,am4372-ecap","ti,am33xx-ecap";
aa842305 569 #pwm-cells = <3>;
9e3269b8
LV		 570 reg = <0x48302100 0x80>;
571 ti,hwmods = "ecap1";
572 status = "disabled";
573 };
574
575 ehrpwm1: ehrpwm@48302200 {
576 compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
aa842305 577 #pwm-cells = <3>;
9e3269b8
LV		 578 reg = <0x48302200 0x80>;
579 ti,hwmods = "ehrpwm1";
580 status = "disabled";
581 };
73456012
AM		 582 };
583
584 epwmss2: epwmss@48304000 {
585 compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
586 reg = <0x48304000 0x10>;
9e3269b8
LV		 587 #address-cells = <1>;
588 #size-cells = <1>;
589 ranges;
73456012
AM		 590 ti,hwmods = "epwmss2";
591 status = "disabled";
9e3269b8
LV		 592
593 ecap2: ecap@48304100 {
594 compatible = "ti,am4372-ecap","ti,am33xx-ecap";
aa842305 595 #pwm-cells = <3>;
9e3269b8
LV		 596 reg = <0x48304100 0x80>;
597 ti,hwmods = "ecap2";
598 status = "disabled";
599 };
600
601 ehrpwm2: ehrpwm@48304200 {
602 compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
aa842305 603 #pwm-cells = <3>;
9e3269b8
LV		 604 reg = <0x48304200 0x80>;
605 ti,hwmods = "ehrpwm2";
606 status = "disabled";
607 };
73456012
AM		 608 };
609
610 epwmss3: epwmss@48306000 {
611 compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
612 reg = <0x48306000 0x10>;
9e3269b8
LV		 613 #address-cells = <1>;
614 #size-cells = <1>;
615 ranges;
73456012
AM		 616 ti,hwmods = "epwmss3";
617 status = "disabled";
9e3269b8
LV		 618
619 ehrpwm3: ehrpwm@48306200 {
620 compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
aa842305 621 #pwm-cells = <3>;
9e3269b8
LV		 622 reg = <0x48306200 0x80>;
623 ti,hwmods = "ehrpwm3";
624 status = "disabled";
625 };
73456012
AM		 626 };
627
628 epwmss4: epwmss@48308000 {
629 compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
630 reg = <0x48308000 0x10>;
9e3269b8
LV		 631 #address-cells = <1>;
632 #size-cells = <1>;
633 ranges;
73456012
AM		 634 ti,hwmods = "epwmss4";
635 status = "disabled";
9e3269b8
LV		 636
637 ehrpwm4: ehrpwm@48308200 {
638 compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
aa842305 639 #pwm-cells = <3>;
9e3269b8
LV		 640 reg = <0x48308200 0x80>;
641 ti,hwmods = "ehrpwm4";
642 status = "disabled";
643 };
73456012
AM		 644 };
645
646 epwmss5: epwmss@4830a000 {
647 compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
648 reg = <0x4830a000 0x10>;
9e3269b8
LV		 649 #address-cells = <1>;
650 #size-cells = <1>;
651 ranges;
73456012
AM		 652 ti,hwmods = "epwmss5";
653 status = "disabled";
9e3269b8
LV		 654
655 ehrpwm5: ehrpwm@4830a200 {
656 compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
aa842305 657 #pwm-cells = <3>;
9e3269b8
LV		 658 reg = <0x4830a200 0x80>;
659 ti,hwmods = "ehrpwm5";
660 status = "disabled";
661 };
662 };
663
664 sham: sham@53100000 {
665 compatible = "ti,omap5-sham";
666 ti,hwmods = "sham";
667 reg = <0x53100000 0x300>;
668 dmas = <&edma 36>;
669 dma-names = "rx";
670 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
6cfd8117 671 };
6e70a510
JF		 672
673 aes: aes@53501000 {
674 compatible = "ti,omap4-aes";
675 ti,hwmods = "aes";
676 reg = <0x53501000 0xa0>;
677 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
9e3269b8
LV		 678 dmas = <&edma 6
679 &edma 5>;
680 dma-names = "tx", "rx";
6e70a510 681 };
099f3a85
JF		 682
683 des: des@53701000 {
684 compatible = "ti,omap4-des";
685 ti,hwmods = "des";
686 reg = <0x53701000 0xa0>;
687 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
9e3269b8
LV		 688 dmas = <&edma 34
689 &edma 33>;
690 dma-names = "tx", "rx";
099f3a85 691 };
9e3269b8 692
b9c95bf4
PU		 693 mcasp0: mcasp@48038000 {
694 compatible = "ti,am33xx-mcasp-audio";
695 ti,hwmods = "mcasp0";
696 reg = <0x48038000 0x2000>,
697 <0x46000000 0x400000>;
698 reg-names = "mpu", "dat";
699 interrupts = <80>, <81>;
ae107d06 700 interrupt-names = "tx", "rx";
b9c95bf4
PU		 701 status = "disabled";
702 dmas = <&edma 8>,
703 <&edma 9>;
704 dma-names = "tx", "rx";
705 };
706
707 mcasp1: mcasp@4803C000 {
708 compatible = "ti,am33xx-mcasp-audio";
709 ti,hwmods = "mcasp1";
710 reg = <0x4803C000 0x2000>,
711 <0x46400000 0x400000>;
712 reg-names = "mpu", "dat";
713 interrupts = <82>, <83>;
ae107d06 714 interrupt-names = "tx", "rx";
b9c95bf4
PU		 715 status = "disabled";
716 dmas = <&edma 10>,
717 <&edma 11>;
718 dma-names = "tx", "rx";
719 };
f68e355c
PG		 720
721 elm: elm@48080000 {
722 compatible = "ti,am3352-elm";
723 reg = <0x48080000 0x2000>;
724 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
725 ti,hwmods = "elm";
726 clocks = <&l4ls_gclk>;
727 clock-names = "fck";
728 status = "disabled";
729 };
730
731 gpmc: gpmc@50000000 {
732 compatible = "ti,am3352-gpmc";
733 ti,hwmods = "gpmc";
734 clocks = <&l3s_gclk>;
735 clock-names = "fck";
736 reg = <0x50000000 0x2000>;
737 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
738 gpmc,num-cs = <7>;
739 gpmc,num-waitpins = <2>;
740 #address-cells = <2>;
741 #size-cells = <1>;
742 status = "disabled";
743 };
a0ae47ea
GC		 744
745 am43xx_control_usb2phy1: control-phy@44e10620 {
746 compatible = "ti,control-phy-usb2-am437";
747 reg = <0x44e10620 0x4>;
748 reg-names = "power";
749 };
750
751 am43xx_control_usb2phy2: control-phy@0x44e10628 {
752 compatible = "ti,control-phy-usb2-am437";
753 reg = <0x44e10628 0x4>;
754 reg-names = "power";
755 };
756
757 ocp2scp0: ocp2scp@483a8000 {
758 compatible = "ti,omap-ocp2scp";
759 #address-cells = <1>;
760 #size-cells = <1>;
761 ranges;
762 ti,hwmods = "ocp2scp0";
763
764 usb2_phy1: phy@483a8000 {
765 compatible = "ti,am437x-usb2";
766 reg = <0x483a8000 0x8000>;
767 ctrl-module = <&am43xx_control_usb2phy1>;
768 clocks = <&usb_phy0_always_on_clk32k>,
769 <&usb_otg_ss0_refclk960m>;
770 clock-names = "wkupclk", "refclk";
771 #phy-cells = <0>;
772 status = "disabled";
773 };
774 };
775
776 ocp2scp1: ocp2scp@483e8000 {
777 compatible = "ti,omap-ocp2scp";
778 #address-cells = <1>;
779 #size-cells = <1>;
780 ranges;
781 ti,hwmods = "ocp2scp1";
782
783 usb2_phy2: phy@483e8000 {
784 compatible = "ti,am437x-usb2";
785 reg = <0x483e8000 0x8000>;
786 ctrl-module = <&am43xx_control_usb2phy2>;
787 clocks = <&usb_phy1_always_on_clk32k>,
788 <&usb_otg_ss1_refclk960m>;
789 clock-names = "wkupclk", "refclk";
790 #phy-cells = <0>;
791 status = "disabled";
792 };
793 };
794
795 dwc3_1: omap_dwc3@48380000 {
796 compatible = "ti,am437x-dwc3";
797 ti,hwmods = "usb_otg_ss0";
798 reg = <0x48380000 0x10000>;
799 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
800 #address-cells = <1>;
801 #size-cells = <1>;
802 utmi-mode = <1>;
803 ranges;
804
805 usb1: usb@48390000 {
806 compatible = "synopsys,dwc3";
807 reg = <0x48390000 0x17000>;
808 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
809 phys = <&usb2_phy1>;
810 phy-names = "usb2-phy";
811 maximum-speed = "high-speed";
812 dr_mode = "otg";
813 status = "disabled";
814 };
815 };
816
817 dwc3_2: omap_dwc3@483c0000 {
818 compatible = "ti,am437x-dwc3";
819 ti,hwmods = "usb_otg_ss1";
820 reg = <0x483c0000 0x10000>;
821 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
822 #address-cells = <1>;
823 #size-cells = <1>;
824 utmi-mode = <1>;
825 ranges;
826
827 usb2: usb@483d0000 {
828 compatible = "synopsys,dwc3";
829 reg = <0x483d0000 0x17000>;
830 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
831 phys = <&usb2_phy2>;
832 phy-names = "usb2-phy";
833 maximum-speed = "high-speed";
834 dr_mode = "otg";
835 status = "disabled";
836 };
837 };
2a1a5043
SP		 838
839 qspi: qspi@47900000 {
840 compatible = "ti,am4372-qspi";
841 reg = <0x47900000 0x100>;
842 #address-cells = <1>;
843 #size-cells = <0>;
844 ti,hwmods = "qspi";
845 interrupts = <0 138 0x4>;
846 num-cs = <4>;
847 status = "disabled";
848 };
741cac5f
SP		 849
850 hdq: hdq@48347000 {
851 compatible = "ti,am43xx-hdq";
852 reg = <0x48347000 0x1000>;
853 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
854 clocks = <&func_12m_clk>;
855 clock-names = "fck";
856 ti,hwmods = "hdq1w";
857 status = "disabled";
858 };
8c793367
SP		 859
860 dss: dss@4832a000 {
861 compatible = "ti,omap3-dss";
862 reg = <0x4832a000 0x200>;
863 status = "disabled";
864 ti,hwmods = "dss_core";
865 clocks = <&disp_clk>;
866 clock-names = "fck";
867 #address-cells = <1>;
868 #size-cells = <1>;
869 ranges;
870
08ecb28a 871 dispc: dispc@4832a400 {
8c793367
SP		 872 compatible = "ti,omap3-dispc";
873 reg = <0x4832a400 0x400>;
874 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
875 ti,hwmods = "dss_dispc";
876 clocks = <&disp_clk>;
877 clock-names = "fck";
878 };
879
880 rfbi: rfbi@4832a800 {
881 compatible = "ti,omap3-rfbi";
882 reg = <0x4832a800 0x100>;
883 ti,hwmods = "dss_rfbi";
884 clocks = <&disp_clk>;
885 clock-names = "fck";
886 };
887 };
6cfd8117
AM		 888 };
889};
6a679208
TK		 890
891/include/ "am43xx-clocks.dtsi"
Linux kernel - Deliverables
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