[deliverable/linux.git] / arch / arm / boot / dts / am4372.dtsi

/*
 * Device Tree Source for AM4372 SoC
 *
 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
 *
 * This file is licensed under the terms of the GNU General Public License
 * version 2.  This program is licensed "as is" without any warranty of any
 * kind, whether express or implied.
 */

#include <dt-bindings/interrupt-controller/arm-gic.h>

#include "skeleton.dtsi"

/ {
	compatible = "ti,am4372", "ti,am43";
	interrupt-parent = <&gic>;


	aliases {
		serial0 = &uart0;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		cpu@0 {
			compatible = "arm,cortex-a9";
			device_type = "cpu";
			reg = <0>;
		};
	};

	gic: interrupt-controller@48241000 {
		compatible = "arm,cortex-a9-gic";
		interrupt-controller;
		#interrupt-cells = <3>;
		reg = <0x48241000 0x1000>,
		      <0x48240100 0x0100>;
	};

	ocp {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		uart0: serial@44e09000 {
			compatible = "ti,am4372-uart","ti,omap2-uart";
			reg = <0x44e09000 0x2000>;
			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "uart1";
		};

		uart1: serial@48022000 {
			compatible = "ti,am4372-uart","ti,omap2-uart";
			reg = <0x48022000 0x2000>;
			interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "uart2";
			status = "disabled";
		};

		uart2: serial@48024000 {
			compatible = "ti,am4372-uart","ti,omap2-uart";
			reg = <0x48024000 0x2000>;
			interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "uart3";
			status = "disabled";
		};

		uart3: serial@481a6000 {
			compatible = "ti,am4372-uart","ti,omap2-uart";
			reg = <0x481a6000 0x2000>;
			interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "uart4";
			status = "disabled";
		};

		uart4: serial@481a8000 {
			compatible = "ti,am4372-uart","ti,omap2-uart";
			reg = <0x481a8000 0x2000>;
			interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "uart5";
			status = "disabled";
		};

		uart5: serial@481aa000 {
			compatible = "ti,am4372-uart","ti,omap2-uart";
			reg = <0x481aa000 0x2000>;
			interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "uart6";
			status = "disabled";
		};

		timer1: timer@44e31000 {
			compatible = "ti,am4372-timer-1ms","ti,am335x-timer-1ms";
			reg = <0x44e31000 0x400>;
			interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
			ti,timer-alwon;
			ti,hwmods = "timer1";
		};

		timer2: timer@48040000  {
			compatible = "ti,am4372-timer","ti,am335x-timer";
			reg = <0x48040000  0x400>;
			interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "timer2";
		};

		timer3: timer@48042000 {
			compatible = "ti,am4372-timer","ti,am335x-timer";
			reg = <0x48042000 0x400>;
			interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "timer3";
			status = "disabled";
		};

		timer4: timer@48044000 {
			compatible = "ti,am4372-timer","ti,am335x-timer";
			reg = <0x48044000 0x400>;
			interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
			ti,timer-pwm;
			ti,hwmods = "timer4";
			status = "disabled";
		};

		timer5: timer@48046000 {
			compatible = "ti,am4372-timer","ti,am335x-timer";
			reg = <0x48046000 0x400>;
			interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
			ti,timer-pwm;
			ti,hwmods = "timer5";
			status = "disabled";
		};

		timer6: timer@48048000 {
			compatible = "ti,am4372-timer","ti,am335x-timer";
			reg = <0x48048000 0x400>;
			interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
			ti,timer-pwm;
			ti,hwmods = "timer6";
			status = "disabled";
		};

		timer7: timer@4804a000 {
			compatible = "ti,am4372-timer","ti,am335x-timer";
			reg = <0x4804a000 0x400>;
			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
			ti,timer-pwm;
			ti,hwmods = "timer7";
			status = "disabled";
		};

		timer8: timer@481c1000 {
			compatible = "ti,am4372-timer","ti,am335x-timer";
			reg = <0x481c1000 0x400>;
			interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "timer8";
			status = "disabled";
		};

		timer9: timer@4833d000 {
			compatible = "ti,am4372-timer","ti,am335x-timer";
			reg = <0x4833d000 0x400>;
			interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "timer9";
			status = "disabled";
		};

		timer10: timer@4833f000 {
			compatible = "ti,am4372-timer","ti,am335x-timer";
			reg = <0x4833f000 0x400>;
			interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "timer10";
			status = "disabled";
		};

		timer11: timer@48341000 {
			compatible = "ti,am4372-timer","ti,am335x-timer";
			reg = <0x48341000 0x400>;
			interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "timer11";
			status = "disabled";
		};

		counter32k: counter@44e86000 {
			compatible = "ti,am4372-counter32k","ti,omap-counter32k";
			reg = <0x44e86000 0x40>;
			ti,hwmods = "counter_32k";
		};

		rtc@44e3e000 {
			compatible = "ti,am4372-rtc","ti,da830-rtc";
			reg = <0x44e3e000 0x1000>;
			interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH
				      GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "rtc";
			status = "disabled";
		};

		wdt@44e35000 {
			compatible = "ti,am4372-wdt","ti,omap3-wdt";
			reg = <0x44e35000 0x1000>;
			interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "wd_timer2";
			status = "disabled";
		};

		gpio0: gpio@44e07000 {
			compatible = "ti,am4372-gpio","ti,omap4-gpio";
			reg = <0x44e07000 0x1000>;
			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
			ti,hwmods = "gpio1";
			status = "disabled";
		};

		gpio1: gpio@4804c000 {
			compatible = "ti,am4372-gpio","ti,omap4-gpio";
			reg = <0x4804c000 0x1000>;
			interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
			ti,hwmods = "gpio2";
			status = "disabled";
		};

		gpio2: gpio@481ac000 {
			compatible = "ti,am4372-gpio","ti,omap4-gpio";
			reg = <0x481ac000 0x1000>;
			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
			ti,hwmods = "gpio3";
			status = "disabled";
		};

		gpio3: gpio@481ae000 {
			compatible = "ti,am4372-gpio","ti,omap4-gpio";
			reg = <0x481ae000 0x1000>;
			interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
			ti,hwmods = "gpio4";
			status = "disabled";
		};

		gpio4: gpio@48320000 {
			compatible = "ti,am4372-gpio","ti,omap4-gpio";
			reg = <0x48320000 0x1000>;
			interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
			ti,hwmods = "gpio5";
			status = "disabled";
		};

		gpio5: gpio@48322000 {
			compatible = "ti,am4372-gpio","ti,omap4-gpio";
			reg = <0x48322000 0x1000>;
			interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
			ti,hwmods = "gpio6";
			status = "disabled";
		};

		i2c0: i2c@44e0b000 {
			compatible = "ti,am4372-i2c","ti,omap4-i2c";
			reg = <0x44e0b000 0x1000>;
			interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "i2c1";
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		i2c1: i2c@4802a000 {
			compatible = "ti,am4372-i2c","ti,omap4-i2c";
			reg = <0x4802a000 0x1000>;
			interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "i2c2";
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		i2c2: i2c@4819c000 {
			compatible = "ti,am4372-i2c","ti,omap4-i2c";
			reg = <0x4819c000 0x1000>;
			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "i2c3";
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		spi0: spi@48030000 {
			compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
			reg = <0x48030000 0x400>;
			interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "spi0";
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		spi1: spi@481a0000 {
			compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
			reg = <0x481a0000 0x400>;
			interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "spi1";
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		spi2: spi@481a2000 {
			compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
			reg = <0x481a2000 0x400>;
			interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "spi2";
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		spi3: spi@481a4000 {
			compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
			reg = <0x481a4000 0x400>;
			interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "spi3";
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		spi4: spi@48345000 {
			compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
			reg = <0x48345000 0x400>;
			interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "spi4";
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		mac: ethernet@4a100000 {
			compatible = "ti,am4372-cpsw","ti,cpsw";
			reg = <0x4a100000 0x800
			       0x4a101200 0x100>;
			interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH
				      GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH
				      GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH
				      GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "cpgmac0";
			status = "disabled";
		};

		epwmss0: epwmss@48300000 {
			compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
			reg = <0x48300000 0x10>;
			ti,hwmods = "epwmss0";
			status = "disabled";
		};

		epwmss1: epwmss@48302000 {
			compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
			reg = <0x48302000 0x10>;
			ti,hwmods = "epwmss1";
			status = "disabled";
		};

		epwmss2: epwmss@48304000 {
			compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
			reg = <0x48304000 0x10>;
			ti,hwmods = "epwmss2";
			status = "disabled";
		};

		epwmss3: epwmss@48306000 {
			compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
			reg = <0x48306000 0x10>;
			ti,hwmods = "epwmss3";
			status = "disabled";
		};

		epwmss4: epwmss@48308000 {
			compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
			reg = <0x48308000 0x10>;
			ti,hwmods = "epwmss4";
			status = "disabled";
		};

		epwmss5: epwmss@4830a000 {
			compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
			reg = <0x4830a000 0x10>;
			ti,hwmods = "epwmss5";
			status = "disabled";
		};

		aes: aes@53501000 {
			compatible = "ti,omap4-aes";
			ti,hwmods = "aes";
			reg = <0x53501000 0xa0>;
			interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
		};

		des: des@53701000 {
			compatible = "ti,omap4-des";
			ti,hwmods = "des";
			reg = <0x53701000 0xa0>;
			interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
		};
	};
};
Commit	Line	Data
6cfd8117 AM	1	/*
	2	* Device Tree Source for AM4372 SoC
	3	*
	4	* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
	5	*
	6	* This file is licensed under the terms of the GNU General Public License
	7	* version 2. This program is licensed "as is" without any warranty of any
	8	* kind, whether express or implied.
	9	*/
	10
	11	#include <dt-bindings/interrupt-controller/arm-gic.h>
	12
	13	#include "skeleton.dtsi"
	14
	15	/ {
	16	compatible = "ti,am4372", "ti,am43";
	17	interrupt-parent = <&gic>;
	18
	19
	20	aliases {
	21	serial0 = &uart0;
	22	};
	23
	24	cpus {
738c7409 AM	25	#address-cells = <1>;
738c7409 AM	26	#size-cells = <0>;
6cfd8117 AM	27	cpu@0 {
6cfd8117 AM	28	compatible = "arm,cortex-a9";
738c7409 AM	29	device_type = "cpu";
738c7409 AM	30	reg = <0>;
6cfd8117 AM	31	};
	32	};
	33
	34	gic: interrupt-controller@48241000 {
	35	compatible = "arm,cortex-a9-gic";
	36	interrupt-controller;
	37	#interrupt-cells = <3>;
	38	reg = <0x48241000 0x1000>,
	39	<0x48240100 0x0100>;
	40	};
	41
	42	ocp {
	43	compatible = "simple-bus";
	44	#address-cells = <1>;
	45	#size-cells = <1>;
	46	ranges;
	47
	48	uart0: serial@44e09000 {
	49	compatible = "ti,am4372-uart","ti,omap2-uart";
	50	reg = <0x44e09000 0x2000>;
	51	interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
73456012 AM	52	ti,hwmods = "uart1";
	53	};
	54
	55	uart1: serial@48022000 {
	56	compatible = "ti,am4372-uart","ti,omap2-uart";
	57	reg = <0x48022000 0x2000>;
	58	interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
	59	ti,hwmods = "uart2";
	60	status = "disabled";
	61	};
	62
	63	uart2: serial@48024000 {
	64	compatible = "ti,am4372-uart","ti,omap2-uart";
	65	reg = <0x48024000 0x2000>;
	66	interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
	67	ti,hwmods = "uart3";
	68	status = "disabled";
	69	};
	70
	71	uart3: serial@481a6000 {
	72	compatible = "ti,am4372-uart","ti,omap2-uart";
	73	reg = <0x481a6000 0x2000>;
	74	interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
	75	ti,hwmods = "uart4";
	76	status = "disabled";
	77	};
	78
	79	uart4: serial@481a8000 {
	80	compatible = "ti,am4372-uart","ti,omap2-uart";
	81	reg = <0x481a8000 0x2000>;
	82	interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
	83	ti,hwmods = "uart5";
	84	status = "disabled";
	85	};
	86
	87	uart5: serial@481aa000 {
	88	compatible = "ti,am4372-uart","ti,omap2-uart";
	89	reg = <0x481aa000 0x2000>;
	90	interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
	91	ti,hwmods = "uart6";
	92	status = "disabled";
6cfd8117 AM	93	};
	94
	95	timer1: timer@44e31000 {
	96	compatible = "ti,am4372-timer-1ms","ti,am335x-timer-1ms";
	97	reg = <0x44e31000 0x400>;
	98	interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
	99	ti,timer-alwon;
73456012	100	ti,hwmods = "timer1";
6cfd8117 AM	101	};
	102
	103	timer2: timer@48040000 {
	104	compatible = "ti,am4372-timer","ti,am335x-timer";
	105	reg = <0x48040000 0x400>;
	106	interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
73456012 AM	107	ti,hwmods = "timer2";
	108	};
	109
	110	timer3: timer@48042000 {
	111	compatible = "ti,am4372-timer","ti,am335x-timer";
	112	reg = <0x48042000 0x400>;
	113	interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
	114	ti,hwmods = "timer3";
	115	status = "disabled";
	116	};
	117
	118	timer4: timer@48044000 {
	119	compatible = "ti,am4372-timer","ti,am335x-timer";
	120	reg = <0x48044000 0x400>;
	121	interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
	122	ti,timer-pwm;
	123	ti,hwmods = "timer4";
	124	status = "disabled";
	125	};
	126
	127	timer5: timer@48046000 {
	128	compatible = "ti,am4372-timer","ti,am335x-timer";
	129	reg = <0x48046000 0x400>;
	130	interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
	131	ti,timer-pwm;
	132	ti,hwmods = "timer5";
	133	status = "disabled";
	134	};
	135
	136	timer6: timer@48048000 {
	137	compatible = "ti,am4372-timer","ti,am335x-timer";
	138	reg = <0x48048000 0x400>;
	139	interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
	140	ti,timer-pwm;
	141	ti,hwmods = "timer6";
	142	status = "disabled";
	143	};
	144
	145	timer7: timer@4804a000 {
	146	compatible = "ti,am4372-timer","ti,am335x-timer";
	147	reg = <0x4804a000 0x400>;
	148	interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
	149	ti,timer-pwm;
	150	ti,hwmods = "timer7";
	151	status = "disabled";
	152	};
	153
	154	timer8: timer@481c1000 {
	155	compatible = "ti,am4372-timer","ti,am335x-timer";
	156	reg = <0x481c1000 0x400>;
	157	interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
	158	ti,hwmods = "timer8";
	159	status = "disabled";
	160	};
	161
	162	timer9: timer@4833d000 {
	163	compatible = "ti,am4372-timer","ti,am335x-timer";
	164	reg = <0x4833d000 0x400>;
	165	interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
	166	ti,hwmods = "timer9";
	167	status = "disabled";
	168	};
	169
	170	timer10: timer@4833f000 {
171	compatible = "ti,am4372-timer","ti,am335x-timer";
172	reg = <0x4833f000 0x400>;
173	interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
174	ti,hwmods = "timer10";
175	status = "disabled";
176	};
177
178	timer11: timer@48341000 {
179	compatible = "ti,am4372-timer","ti,am335x-timer";
180	reg = <0x48341000 0x400>;
181	interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
182	ti,hwmods = "timer11";
183	status = "disabled";
6cfd8117 AM	184	};
	185
	186	counter32k: counter@44e86000 {
	187	compatible = "ti,am4372-counter32k","ti,omap-counter32k";
	188	reg = <0x44e86000 0x40>;
73456012 AM	189	ti,hwmods = "counter_32k";
	190	};
	191
	192	rtc@44e3e000 {
	193	compatible = "ti,am4372-rtc","ti,da830-rtc";
	194	reg = <0x44e3e000 0x1000>;
	195	interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH
	196	GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
	197	ti,hwmods = "rtc";
	198	status = "disabled";
	199	};
	200
	201	wdt@44e35000 {
	202	compatible = "ti,am4372-wdt","ti,omap3-wdt";
	203	reg = <0x44e35000 0x1000>;
	204	interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
	205	ti,hwmods = "wd_timer2";
	206	status = "disabled";
	207	};
	208
	209	gpio0: gpio@44e07000 {
	210	compatible = "ti,am4372-gpio","ti,omap4-gpio";
	211	reg = <0x44e07000 0x1000>;
	212	interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
	213	gpio-controller;
	214	#gpio-cells = <2>;
	215	interrupt-controller;
	216	#interrupt-cells = <2>;
	217	ti,hwmods = "gpio1";
	218	status = "disabled";
	219	};
	220
	221	gpio1: gpio@4804c000 {
	222	compatible = "ti,am4372-gpio","ti,omap4-gpio";
	223	reg = <0x4804c000 0x1000>;
	224	interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
	225	gpio-controller;
	226	#gpio-cells = <2>;
	227	interrupt-controller;
	228	#interrupt-cells = <2>;
	229	ti,hwmods = "gpio2";
	230	status = "disabled";
	231	};
	232
	233	gpio2: gpio@481ac000 {
	234	compatible = "ti,am4372-gpio","ti,omap4-gpio";
	235	reg = <0x481ac000 0x1000>;
	236	interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
	237	gpio-controller;
	238	#gpio-cells = <2>;
	239	interrupt-controller;
	240	#interrupt-cells = <2>;
	241	ti,hwmods = "gpio3";
	242	status = "disabled";
	243	};
	244
	245	gpio3: gpio@481ae000 {
	246	compatible = "ti,am4372-gpio","ti,omap4-gpio";
	247	reg = <0x481ae000 0x1000>;
	248	interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
	249	gpio-controller;
	250	#gpio-cells = <2>;
	251	interrupt-controller;
	252	#interrupt-cells = <2>;
253	ti,hwmods = "gpio4";
254	status = "disabled";
255	};
256
257	gpio4: gpio@48320000 {
258	compatible = "ti,am4372-gpio","ti,omap4-gpio";
259	reg = <0x48320000 0x1000>;
260	interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
261	gpio-controller;
262	#gpio-cells = <2>;
263	interrupt-controller;
264	#interrupt-cells = <2>;
265	ti,hwmods = "gpio5";
266	status = "disabled";
267	};
268
269	gpio5: gpio@48322000 {
270	compatible = "ti,am4372-gpio","ti,omap4-gpio";
271	reg = <0x48322000 0x1000>;
272	interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
273	gpio-controller;
274	#gpio-cells = <2>;
275	interrupt-controller;
276	#interrupt-cells = <2>;
277	ti,hwmods = "gpio6";
278	status = "disabled";
279	};
280
281	i2c0: i2c@44e0b000 {
282	compatible = "ti,am4372-i2c","ti,omap4-i2c";
283	reg = <0x44e0b000 0x1000>;
284	interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
285	ti,hwmods = "i2c1";
286	#address-cells = <1>;
287	#size-cells = <0>;
288	status = "disabled";
289	};
290
291	i2c1: i2c@4802a000 {
292	compatible = "ti,am4372-i2c","ti,omap4-i2c";
293	reg = <0x4802a000 0x1000>;
294	interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
295	ti,hwmods = "i2c2";
296	#address-cells = <1>;
297	#size-cells = <0>;
298	status = "disabled";
299	};
300
301	i2c2: i2c@4819c000 {
302	compatible = "ti,am4372-i2c","ti,omap4-i2c";
303	reg = <0x4819c000 0x1000>;
304	interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
305	ti,hwmods = "i2c3";
306	#address-cells = <1>;
307	#size-cells = <0>;
308	status = "disabled";
309	};
310
311	spi0: spi@48030000 {
312	compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
313	reg = <0x48030000 0x400>;
314	interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
315	ti,hwmods = "spi0";
316	#address-cells = <1>;
317	#size-cells = <0>;
318	status = "disabled";
319	};
320
321	spi1: spi@481a0000 {
322	compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
323	reg = <0x481a0000 0x400>;
324	interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
325	ti,hwmods = "spi1";
326	#address-cells = <1>;
327	#size-cells = <0>;
328	status = "disabled";
329	};
330
331	spi2: spi@481a2000 {
332	compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
333	reg = <0x481a2000 0x400>;
334	interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
335	ti,hwmods = "spi2";
336	#address-cells = <1>;
337	#size-cells = <0>;
338	status = "disabled";
339	};
340
341	spi3: spi@481a4000 {
342	compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
343	reg = <0x481a4000 0x400>;
344	interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
345	ti,hwmods = "spi3";
346	#address-cells = <1>;
347	#size-cells = <0>;
348	status = "disabled";
349	};
350
351	spi4: spi@48345000 {
352	compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
353	reg = <0x48345000 0x400>;
354	interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
355	ti,hwmods = "spi4";
356	#address-cells = <1>;
357	#size-cells = <0>;
358	status = "disabled";
359	};
360
361	mac: ethernet@4a100000 {
362	compatible = "ti,am4372-cpsw","ti,cpsw";
363	reg = <0x4a100000 0x800
364	0x4a101200 0x100>;
365	interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH
366	GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH
367	GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH
368	GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
369	ti,hwmods = "cpgmac0";
370	status = "disabled";
371	};
372
373	epwmss0: epwmss@48300000 {
374	compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
375	reg = <0x48300000 0x10>;
376	ti,hwmods = "epwmss0";
377	status = "disabled";
378	};
379
380	epwmss1: epwmss@48302000 {
381	compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
382	reg = <0x48302000 0x10>;
383	ti,hwmods = "epwmss1";
384	status = "disabled";
385	};
386
387	epwmss2: epwmss@48304000 {
388	compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
389	reg = <0x48304000 0x10>;
390	ti,hwmods = "epwmss2";
391	status = "disabled";
392	};
393
394	epwmss3: epwmss@48306000 {
395	compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
396	reg = <0x48306000 0x10>;
397	ti,hwmods = "epwmss3";
398	status = "disabled";
399	};
400
401	epwmss4: epwmss@48308000 {
402	compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
403	reg = <0x48308000 0x10>;
404	ti,hwmods = "epwmss4";
405	status = "disabled";
406	};
407
408	epwmss5: epwmss@4830a000 {
409	compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
410	reg = <0x4830a000 0x10>;
411	ti,hwmods = "epwmss5";
412	status = "disabled";
6cfd8117	413	};
6e70a510 JF	414
	415	aes: aes@53501000 {
	416	compatible = "ti,omap4-aes";
	417	ti,hwmods = "aes";
	418	reg = <0x53501000 0xa0>;
	419	interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
	420	};
099f3a85 JF	421
	422	des: des@53701000 {
	423	compatible = "ti,omap4-des";
	424	ti,hwmods = "des";
	425	reg = <0x53701000 0xa0>;
	426	interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
	427	};
6cfd8117 AM	428	};
6cfd8117 AM	429	};