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ARM: dts: dra72-evm: Add CAN support
[deliverable/linux.git] / arch / arm / boot / dts / am4372.dtsi
CommitLineData
6cfd8117
AM		 1/*
2 * Device Tree Source for AM4372 SoC
3 *
4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
d2885dbb 11#include <dt-bindings/gpio/gpio.h>
6cfd8117
AM		 12#include <dt-bindings/interrupt-controller/arm-gic.h>
13
14#include "skeleton.dtsi"
15
16/ {
17 compatible = "ti,am4372", "ti,am43";
18 interrupt-parent = <&gic>;
19
20
21 aliases {
6a968678
NM		 22 i2c0 = &i2c0;
23 i2c1 = &i2c1;
24 i2c2 = &i2c2;
6cfd8117 25 serial0 = &uart0;
9e3269b8
LV		 26 ethernet0 = &cpsw_emac0;
27 ethernet1 = &cpsw_emac1;
6cfd8117
AM		 28 };
29
30 cpus {
738c7409
AM		 31 #address-cells = <1>;
32 #size-cells = <0>;
08ecb28a 33 cpu: cpu@0 {
6cfd8117 34 compatible = "arm,cortex-a9";
738c7409
AM		 35 device_type = "cpu";
36 reg = <0>;
8d766fa2
NM		 37
38 clocks = <&dpll_mpu_ck>;
39 clock-names = "cpu";
40
41 clock-latency = <300000>; /* From omap-cpufreq driver */
6cfd8117
AM		 42 };
43 };
44
45 gic: interrupt-controller@48241000 {
46 compatible = "arm,cortex-a9-gic";
47 interrupt-controller;
48 #interrupt-cells = <3>;
49 reg = <0x48241000 0x1000>,
50 <0x48240100 0x0100>;
51 };
52
9e3269b8
LV		 53 l2-cache-controller@48242000 {
54 compatible = "arm,pl310-cache";
55 reg = <0x48242000 0x1000>;
56 cache-unified;
57 cache-level = <2>;
58 };
59
60 am43xx_pinmux: pinmux@44e10800 {
d8c5bab6 61 compatible = "ti,am437-padconf", "pinctrl-single";
9e3269b8
LV		 62 reg = <0x44e10800 0x31c>;
63 #address-cells = <1>;
64 #size-cells = <0>;
d8c5bab6
NM		 65 #interrupt-cells = <1>;
66 interrupt-controller;
9e3269b8
LV		 67 pinctrl-single,register-width = <32>;
68 pinctrl-single,function-mask = <0xffffffff>;
69 };
70
6cfd8117 71 ocp {
2eeddb8a 72 compatible = "ti,am4372-l3-noc", "simple-bus";
6cfd8117
AM		 73 #address-cells = <1>;
74 #size-cells = <1>;
75 ranges;
9e3269b8 76 ti,hwmods = "l3_main";
2eeddb8a
AM		 77 reg = <0x44000000 0x400000
78 0x44800000 0x400000>;
79 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
80 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
9e3269b8 81
6a679208
TK		 82 prcm: prcm@44df0000 {
83 compatible = "ti,am4-prcm";
84 reg = <0x44df0000 0x11000>;
85
86 prcm_clocks: clocks {
87 #address-cells = <1>;
88 #size-cells = <0>;
89 };
90
91 prcm_clockdomains: clockdomains {
92 };
93 };
94
95 scrm: scrm@44e10000 {
96 compatible = "ti,am4-scrm";
97 reg = <0x44e10000 0x2000>;
98
99 scrm_clocks: clocks {
100 #address-cells = <1>;
101 #size-cells = <0>;
102 };
103
104 scrm_clockdomains: clockdomains {
105 };
106 };
107
9e3269b8
LV		 108 edma: edma@49000000 {
109 compatible = "ti,edma3";
110 ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2";
111 reg = <0x49000000 0x10000>,
112 <0x44e10f90 0x10>;
113 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
114 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
115 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
116 #dma-cells = <1>;
9e3269b8 117 };
6cfd8117
AM		 118
119 uart0: serial@44e09000 {
120 compatible = "ti,am4372-uart","ti,omap2-uart";
121 reg = <0x44e09000 0x2000>;
122 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
73456012
AM		 123 ti,hwmods = "uart1";
124 };
125
126 uart1: serial@48022000 {
127 compatible = "ti,am4372-uart","ti,omap2-uart";
128 reg = <0x48022000 0x2000>;
129 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
130 ti,hwmods = "uart2";
131 status = "disabled";
132 };
133
134 uart2: serial@48024000 {
135 compatible = "ti,am4372-uart","ti,omap2-uart";
136 reg = <0x48024000 0x2000>;
137 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
138 ti,hwmods = "uart3";
139 status = "disabled";
140 };
141
142 uart3: serial@481a6000 {
143 compatible = "ti,am4372-uart","ti,omap2-uart";
144 reg = <0x481a6000 0x2000>;
145 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
146 ti,hwmods = "uart4";
147 status = "disabled";
148 };
149
150 uart4: serial@481a8000 {
151 compatible = "ti,am4372-uart","ti,omap2-uart";
152 reg = <0x481a8000 0x2000>;
153 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
154 ti,hwmods = "uart5";
155 status = "disabled";
156 };
157
158 uart5: serial@481aa000 {
159 compatible = "ti,am4372-uart","ti,omap2-uart";
160 reg = <0x481aa000 0x2000>;
161 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
162 ti,hwmods = "uart6";
163 status = "disabled";
6cfd8117
AM		 164 };
165
9e3269b8
LV		 166 mailbox: mailbox@480C8000 {
167 compatible = "ti,omap4-mailbox";
168 reg = <0x480C8000 0x200>;
169 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
170 ti,hwmods = "mailbox";
24df0453 171 #mbox-cells = <1>;
9e3269b8
LV		 172 ti,mbox-num-users = <4>;
173 ti,mbox-num-fifos = <8>;
d27704d1
SA		 174 mbox_wkupm3: wkup_m3 {
175 ti,mbox-tx = <0 0 0>;
176 ti,mbox-rx = <0 0 3>;
177 };
9e3269b8
LV		 178 };
179
6cfd8117
AM		 180 timer1: timer@44e31000 {
181 compatible = "ti,am4372-timer-1ms","ti,am335x-timer-1ms";
182 reg = <0x44e31000 0x400>;
183 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
184 ti,timer-alwon;
73456012 185 ti,hwmods = "timer1";
6cfd8117
AM		 186 };
187
188 timer2: timer@48040000 {
189 compatible = "ti,am4372-timer","ti,am335x-timer";
190 reg = <0x48040000 0x400>;
191 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
73456012
AM		 192 ti,hwmods = "timer2";
193 };
194
195 timer3: timer@48042000 {
196 compatible = "ti,am4372-timer","ti,am335x-timer";
197 reg = <0x48042000 0x400>;
198 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
199 ti,hwmods = "timer3";
200 status = "disabled";
201 };
202
203 timer4: timer@48044000 {
204 compatible = "ti,am4372-timer","ti,am335x-timer";
205 reg = <0x48044000 0x400>;
206 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
207 ti,timer-pwm;
208 ti,hwmods = "timer4";
209 status = "disabled";
210 };
211
212 timer5: timer@48046000 {
213 compatible = "ti,am4372-timer","ti,am335x-timer";
214 reg = <0x48046000 0x400>;
215 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
216 ti,timer-pwm;
217 ti,hwmods = "timer5";
218 status = "disabled";
219 };
220
221 timer6: timer@48048000 {
222 compatible = "ti,am4372-timer","ti,am335x-timer";
223 reg = <0x48048000 0x400>;
224 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
225 ti,timer-pwm;
226 ti,hwmods = "timer6";
227 status = "disabled";
228 };
229
230 timer7: timer@4804a000 {
231 compatible = "ti,am4372-timer","ti,am335x-timer";
232 reg = <0x4804a000 0x400>;
233 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
234 ti,timer-pwm;
235 ti,hwmods = "timer7";
236 status = "disabled";
237 };
238
239 timer8: timer@481c1000 {
240 compatible = "ti,am4372-timer","ti,am335x-timer";
241 reg = <0x481c1000 0x400>;
242 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
243 ti,hwmods = "timer8";
244 status = "disabled";
245 };
246
247 timer9: timer@4833d000 {
248 compatible = "ti,am4372-timer","ti,am335x-timer";
249 reg = <0x4833d000 0x400>;
250 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
251 ti,hwmods = "timer9";
252 status = "disabled";
253 };
254
255 timer10: timer@4833f000 {
256 compatible = "ti,am4372-timer","ti,am335x-timer";
257 reg = <0x4833f000 0x400>;
258 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
259 ti,hwmods = "timer10";
260 status = "disabled";
261 };
262
263 timer11: timer@48341000 {
264 compatible = "ti,am4372-timer","ti,am335x-timer";
265 reg = <0x48341000 0x400>;
266 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
267 ti,hwmods = "timer11";
268 status = "disabled";
6cfd8117
AM		 269 };
270
271 counter32k: counter@44e86000 {
272 compatible = "ti,am4372-counter32k","ti,omap-counter32k";
273 reg = <0x44e86000 0x40>;
73456012
AM		 274 ti,hwmods = "counter_32k";
275 };
276
08ecb28a 277 rtc: rtc@44e3e000 {
73456012
AM		 278 compatible = "ti,am4372-rtc","ti,da830-rtc";
279 reg = <0x44e3e000 0x1000>;
280 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH
281 GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
282 ti,hwmods = "rtc";
283 status = "disabled";
284 };
285
08ecb28a 286 wdt: wdt@44e35000 {
73456012
AM		 287 compatible = "ti,am4372-wdt","ti,omap3-wdt";
288 reg = <0x44e35000 0x1000>;
289 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
290 ti,hwmods = "wd_timer2";
73456012
AM		 291 };
292
293 gpio0: gpio@44e07000 {
294 compatible = "ti,am4372-gpio","ti,omap4-gpio";
295 reg = <0x44e07000 0x1000>;
296 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
297 gpio-controller;
298 #gpio-cells = <2>;
299 interrupt-controller;
300 #interrupt-cells = <2>;
301 ti,hwmods = "gpio1";
302 status = "disabled";
303 };
304
305 gpio1: gpio@4804c000 {
306 compatible = "ti,am4372-gpio","ti,omap4-gpio";
307 reg = <0x4804c000 0x1000>;
308 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
309 gpio-controller;
310 #gpio-cells = <2>;
311 interrupt-controller;
312 #interrupt-cells = <2>;
313 ti,hwmods = "gpio2";
314 status = "disabled";
315 };
316
317 gpio2: gpio@481ac000 {
318 compatible = "ti,am4372-gpio","ti,omap4-gpio";
319 reg = <0x481ac000 0x1000>;
320 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
321 gpio-controller;
322 #gpio-cells = <2>;
323 interrupt-controller;
324 #interrupt-cells = <2>;
325 ti,hwmods = "gpio3";
326 status = "disabled";
327 };
328
329 gpio3: gpio@481ae000 {
330 compatible = "ti,am4372-gpio","ti,omap4-gpio";
331 reg = <0x481ae000 0x1000>;
332 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
333 gpio-controller;
334 #gpio-cells = <2>;
335 interrupt-controller;
336 #interrupt-cells = <2>;
337 ti,hwmods = "gpio4";
338 status = "disabled";
339 };
340
341 gpio4: gpio@48320000 {
342 compatible = "ti,am4372-gpio","ti,omap4-gpio";
343 reg = <0x48320000 0x1000>;
344 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
345 gpio-controller;
346 #gpio-cells = <2>;
347 interrupt-controller;
348 #interrupt-cells = <2>;
349 ti,hwmods = "gpio5";
350 status = "disabled";
351 };
352
353 gpio5: gpio@48322000 {
354 compatible = "ti,am4372-gpio","ti,omap4-gpio";
355 reg = <0x48322000 0x1000>;
356 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
357 gpio-controller;
358 #gpio-cells = <2>;
359 interrupt-controller;
360 #interrupt-cells = <2>;
361 ti,hwmods = "gpio6";
362 status = "disabled";
363 };
364
fd4a8a68
SA		 365 hwspinlock: spinlock@480ca000 {
366 compatible = "ti,omap4-hwspinlock";
367 reg = <0x480ca000 0x1000>;
368 ti,hwmods = "spinlock";
369 #hwlock-cells = <1>;
370 };
371
73456012
AM		 372 i2c0: i2c@44e0b000 {
373 compatible = "ti,am4372-i2c","ti,omap4-i2c";
374 reg = <0x44e0b000 0x1000>;
375 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
376 ti,hwmods = "i2c1";
377 #address-cells = <1>;
378 #size-cells = <0>;
379 status = "disabled";
380 };
381
382 i2c1: i2c@4802a000 {
383 compatible = "ti,am4372-i2c","ti,omap4-i2c";
384 reg = <0x4802a000 0x1000>;
385 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
386 ti,hwmods = "i2c2";
387 #address-cells = <1>;
388 #size-cells = <0>;
389 status = "disabled";
390 };
391
392 i2c2: i2c@4819c000 {
393 compatible = "ti,am4372-i2c","ti,omap4-i2c";
394 reg = <0x4819c000 0x1000>;
395 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
396 ti,hwmods = "i2c3";
397 #address-cells = <1>;
398 #size-cells = <0>;
399 status = "disabled";
400 };
401
402 spi0: spi@48030000 {
403 compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
404 reg = <0x48030000 0x400>;
405 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
406 ti,hwmods = "spi0";
407 #address-cells = <1>;
408 #size-cells = <0>;
409 status = "disabled";
410 };
411
9e3269b8
LV		 412 mmc1: mmc@48060000 {
413 compatible = "ti,omap4-hsmmc";
414 reg = <0x48060000 0x1000>;
415 ti,hwmods = "mmc1";
416 ti,dual-volt;
417 ti,needs-special-reset;
418 dmas = <&edma 24
419 &edma 25>;
420 dma-names = "tx", "rx";
421 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
422 status = "disabled";
423 };
424
425 mmc2: mmc@481d8000 {
426 compatible = "ti,omap4-hsmmc";
427 reg = <0x481d8000 0x1000>;
428 ti,hwmods = "mmc2";
429 ti,needs-special-reset;
430 dmas = <&edma 2
431 &edma 3>;
432 dma-names = "tx", "rx";
433 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
434 status = "disabled";
435 };
436
437 mmc3: mmc@47810000 {
438 compatible = "ti,omap4-hsmmc";
439 reg = <0x47810000 0x1000>;
440 ti,hwmods = "mmc3";
441 ti,needs-special-reset;
442 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
443 status = "disabled";
444 };
445
73456012
AM		 446 spi1: spi@481a0000 {
447 compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
448 reg = <0x481a0000 0x400>;
449 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
450 ti,hwmods = "spi1";
451 #address-cells = <1>;
452 #size-cells = <0>;
453 status = "disabled";
454 };
455
456 spi2: spi@481a2000 {
457 compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
458 reg = <0x481a2000 0x400>;
459 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
460 ti,hwmods = "spi2";
461 #address-cells = <1>;
462 #size-cells = <0>;
463 status = "disabled";
464 };
465
466 spi3: spi@481a4000 {
467 compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
468 reg = <0x481a4000 0x400>;
469 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
470 ti,hwmods = "spi3";
471 #address-cells = <1>;
472 #size-cells = <0>;
473 status = "disabled";
474 };
475
476 spi4: spi@48345000 {
477 compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
478 reg = <0x48345000 0x400>;
479 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
480 ti,hwmods = "spi4";
481 #address-cells = <1>;
482 #size-cells = <0>;
483 status = "disabled";
484 };
485
486 mac: ethernet@4a100000 {
487 compatible = "ti,am4372-cpsw","ti,cpsw";
488 reg = <0x4a100000 0x800
489 0x4a101200 0x100>;
490 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH
491 GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH
492 GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH
493 GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
9e3269b8
LV		 494 #address-cells = <1>;
495 #size-cells = <1>;
73456012 496 ti,hwmods = "cpgmac0";
de21b26e
GC		 497 clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>;
498 clock-names = "fck", "cpts";
73456012 499 status = "disabled";
9e3269b8
LV		 500 cpdma_channels = <8>;
501 ale_entries = <1024>;
502 bd_ram_size = <0x2000>;
503 no_bd_ram = <0>;
504 rx_descs = <64>;
505 mac_control = <0x20>;
506 slaves = <2>;
507 active_slave = <0>;
508 cpts_clock_mult = <0x80000000>;
509 cpts_clock_shift = <29>;
510 ranges;
511
512 davinci_mdio: mdio@4a101000 {
513 compatible = "ti,am4372-mdio","ti,davinci_mdio";
514 reg = <0x4a101000 0x100>;
515 #address-cells = <1>;
516 #size-cells = <0>;
517 ti,hwmods = "davinci_mdio";
518 bus_freq = <1000000>;
519 status = "disabled";
520 };
521
522 cpsw_emac0: slave@4a100200 {
523 /* Filled in by U-Boot */
524 mac-address = [ 00 00 00 00 00 00 ];
525 };
526
527 cpsw_emac1: slave@4a100300 {
528 /* Filled in by U-Boot */
529 mac-address = [ 00 00 00 00 00 00 ];
530 };
a9682cfb
M		 531
532 phy_sel: cpsw-phy-sel@44e10650 {
533 compatible = "ti,am43xx-cpsw-phy-sel";
534 reg= <0x44e10650 0x4>;
535 reg-names = "gmii-sel";
536 };
73456012
AM		 537 };
538
539 epwmss0: epwmss@48300000 {
540 compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
541 reg = <0x48300000 0x10>;
9e3269b8
LV		 542 #address-cells = <1>;
543 #size-cells = <1>;
544 ranges;
73456012
AM		 545 ti,hwmods = "epwmss0";
546 status = "disabled";
9e3269b8
LV		 547
548 ecap0: ecap@48300100 {
549 compatible = "ti,am4372-ecap","ti,am33xx-ecap";
aa842305 550 #pwm-cells = <3>;
9e3269b8
LV		 551 reg = <0x48300100 0x80>;
552 ti,hwmods = "ecap0";
553 status = "disabled";
554 };
555
556 ehrpwm0: ehrpwm@48300200 {
557 compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
aa842305 558 #pwm-cells = <3>;
9e3269b8
LV		 559 reg = <0x48300200 0x80>;
560 ti,hwmods = "ehrpwm0";
561 status = "disabled";
562 };
73456012
AM		 563 };
564
565 epwmss1: epwmss@48302000 {
566 compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
567 reg = <0x48302000 0x10>;
9e3269b8
LV		 568 #address-cells = <1>;
569 #size-cells = <1>;
570 ranges;
73456012
AM		 571 ti,hwmods = "epwmss1";
572 status = "disabled";
9e3269b8
LV		 573
574 ecap1: ecap@48302100 {
575 compatible = "ti,am4372-ecap","ti,am33xx-ecap";
aa842305 576 #pwm-cells = <3>;
9e3269b8
LV		 577 reg = <0x48302100 0x80>;
578 ti,hwmods = "ecap1";
579 status = "disabled";
580 };
581
582 ehrpwm1: ehrpwm@48302200 {
583 compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
aa842305 584 #pwm-cells = <3>;
9e3269b8
LV		 585 reg = <0x48302200 0x80>;
586 ti,hwmods = "ehrpwm1";
587 status = "disabled";
588 };
73456012
AM		 589 };
590
591 epwmss2: epwmss@48304000 {
592 compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
593 reg = <0x48304000 0x10>;
9e3269b8
LV		 594 #address-cells = <1>;
595 #size-cells = <1>;
596 ranges;
73456012
AM		 597 ti,hwmods = "epwmss2";
598 status = "disabled";
9e3269b8
LV		 599
600 ecap2: ecap@48304100 {
601 compatible = "ti,am4372-ecap","ti,am33xx-ecap";
aa842305 602 #pwm-cells = <3>;
9e3269b8
LV		 603 reg = <0x48304100 0x80>;
604 ti,hwmods = "ecap2";
605 status = "disabled";
606 };
607
608 ehrpwm2: ehrpwm@48304200 {
609 compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
aa842305 610 #pwm-cells = <3>;
9e3269b8
LV		 611 reg = <0x48304200 0x80>;
612 ti,hwmods = "ehrpwm2";
613 status = "disabled";
614 };
73456012
AM		 615 };
616
617 epwmss3: epwmss@48306000 {
618 compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
619 reg = <0x48306000 0x10>;
9e3269b8
LV		 620 #address-cells = <1>;
621 #size-cells = <1>;
622 ranges;
73456012
AM		 623 ti,hwmods = "epwmss3";
624 status = "disabled";
9e3269b8
LV		 625
626 ehrpwm3: ehrpwm@48306200 {
627 compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
aa842305 628 #pwm-cells = <3>;
9e3269b8
LV		 629 reg = <0x48306200 0x80>;
630 ti,hwmods = "ehrpwm3";
631 status = "disabled";
632 };
73456012
AM		 633 };
634
635 epwmss4: epwmss@48308000 {
636 compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
637 reg = <0x48308000 0x10>;
9e3269b8
LV		 638 #address-cells = <1>;
639 #size-cells = <1>;
640 ranges;
73456012
AM		 641 ti,hwmods = "epwmss4";
642 status = "disabled";
9e3269b8
LV		 643
644 ehrpwm4: ehrpwm@48308200 {
645 compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
aa842305 646 #pwm-cells = <3>;
9e3269b8
LV		 647 reg = <0x48308200 0x80>;
648 ti,hwmods = "ehrpwm4";
649 status = "disabled";
650 };
73456012
AM		 651 };
652
653 epwmss5: epwmss@4830a000 {
654 compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
655 reg = <0x4830a000 0x10>;
9e3269b8
LV		 656 #address-cells = <1>;
657 #size-cells = <1>;
658 ranges;
73456012
AM		 659 ti,hwmods = "epwmss5";
660 status = "disabled";
9e3269b8
LV		 661
662 ehrpwm5: ehrpwm@4830a200 {
663 compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
aa842305 664 #pwm-cells = <3>;
9e3269b8
LV		 665 reg = <0x4830a200 0x80>;
666 ti,hwmods = "ehrpwm5";
667 status = "disabled";
668 };
669 };
670
0f39f7b9
V		 671 tscadc: tscadc@44e0d000 {
672 compatible = "ti,am3359-tscadc";
673 reg = <0x44e0d000 0x1000>;
674 ti,hwmods = "adc_tsc";
675 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
676 clocks = <&adc_tsc_fck>;
677 clock-names = "fck";
678 status = "disabled";
679
680 tsc {
681 compatible = "ti,am3359-tsc";
682 };
683
684 adc {
685 #io-channel-cells = <1>;
686 compatible = "ti,am3359-adc";
687 };
688
689 };
690
9e3269b8
LV		 691 sham: sham@53100000 {
692 compatible = "ti,omap5-sham";
693 ti,hwmods = "sham";
694 reg = <0x53100000 0x300>;
695 dmas = <&edma 36>;
696 dma-names = "rx";
697 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
6cfd8117 698 };
6e70a510
JF		 699
700 aes: aes@53501000 {
701 compatible = "ti,omap4-aes";
702 ti,hwmods = "aes";
703 reg = <0x53501000 0xa0>;
704 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
9e3269b8
LV		 705 dmas = <&edma 6
706 &edma 5>;
707 dma-names = "tx", "rx";
6e70a510 708 };
099f3a85
JF		 709
710 des: des@53701000 {
711 compatible = "ti,omap4-des";
712 ti,hwmods = "des";
713 reg = <0x53701000 0xa0>;
714 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
9e3269b8
LV		 715 dmas = <&edma 34
716 &edma 33>;
717 dma-names = "tx", "rx";
099f3a85 718 };
9e3269b8 719
b9c95bf4
PU		 720 mcasp0: mcasp@48038000 {
721 compatible = "ti,am33xx-mcasp-audio";
722 ti,hwmods = "mcasp0";
723 reg = <0x48038000 0x2000>,
724 <0x46000000 0x400000>;
725 reg-names = "mpu", "dat";
726 interrupts = <80>, <81>;
ae107d06 727 interrupt-names = "tx", "rx";
b9c95bf4
PU		 728 status = "disabled";
729 dmas = <&edma 8>,
730 <&edma 9>;
731 dma-names = "tx", "rx";
732 };
733
734 mcasp1: mcasp@4803C000 {
735 compatible = "ti,am33xx-mcasp-audio";
736 ti,hwmods = "mcasp1";
737 reg = <0x4803C000 0x2000>,
738 <0x46400000 0x400000>;
739 reg-names = "mpu", "dat";
740 interrupts = <82>, <83>;
ae107d06 741 interrupt-names = "tx", "rx";
b9c95bf4
PU		 742 status = "disabled";
743 dmas = <&edma 10>,
744 <&edma 11>;
745 dma-names = "tx", "rx";
746 };
f68e355c
PG		 747
748 elm: elm@48080000 {
749 compatible = "ti,am3352-elm";
750 reg = <0x48080000 0x2000>;
751 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
752 ti,hwmods = "elm";
753 clocks = <&l4ls_gclk>;
754 clock-names = "fck";
755 status = "disabled";
756 };
757
758 gpmc: gpmc@50000000 {
759 compatible = "ti,am3352-gpmc";
760 ti,hwmods = "gpmc";
761 clocks = <&l3s_gclk>;
762 clock-names = "fck";
763 reg = <0x50000000 0x2000>;
764 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
765 gpmc,num-cs = <7>;
766 gpmc,num-waitpins = <2>;
767 #address-cells = <2>;
768 #size-cells = <1>;
769 status = "disabled";
770 };
a0ae47ea
GC		 771
772 am43xx_control_usb2phy1: control-phy@44e10620 {
773 compatible = "ti,control-phy-usb2-am437";
774 reg = <0x44e10620 0x4>;
775 reg-names = "power";
776 };
777
778 am43xx_control_usb2phy2: control-phy@0x44e10628 {
779 compatible = "ti,control-phy-usb2-am437";
780 reg = <0x44e10628 0x4>;
781 reg-names = "power";
782 };
783
784 ocp2scp0: ocp2scp@483a8000 {
785 compatible = "ti,omap-ocp2scp";
786 #address-cells = <1>;
787 #size-cells = <1>;
788 ranges;
789 ti,hwmods = "ocp2scp0";
790
791 usb2_phy1: phy@483a8000 {
792 compatible = "ti,am437x-usb2";
793 reg = <0x483a8000 0x8000>;
794 ctrl-module = <&am43xx_control_usb2phy1>;
795 clocks = <&usb_phy0_always_on_clk32k>,
796 <&usb_otg_ss0_refclk960m>;
797 clock-names = "wkupclk", "refclk";
798 #phy-cells = <0>;
799 status = "disabled";
800 };
801 };
802
803 ocp2scp1: ocp2scp@483e8000 {
804 compatible = "ti,omap-ocp2scp";
805 #address-cells = <1>;
806 #size-cells = <1>;
807 ranges;
808 ti,hwmods = "ocp2scp1";
809
810 usb2_phy2: phy@483e8000 {
811 compatible = "ti,am437x-usb2";
812 reg = <0x483e8000 0x8000>;
813 ctrl-module = <&am43xx_control_usb2phy2>;
814 clocks = <&usb_phy1_always_on_clk32k>,
815 <&usb_otg_ss1_refclk960m>;
816 clock-names = "wkupclk", "refclk";
817 #phy-cells = <0>;
818 status = "disabled";
819 };
820 };
821
822 dwc3_1: omap_dwc3@48380000 {
823 compatible = "ti,am437x-dwc3";
824 ti,hwmods = "usb_otg_ss0";
825 reg = <0x48380000 0x10000>;
826 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
827 #address-cells = <1>;
828 #size-cells = <1>;
829 utmi-mode = <1>;
830 ranges;
831
832 usb1: usb@48390000 {
833 compatible = "synopsys,dwc3";
4b143f0f 834 reg = <0x48390000 0x10000>;
a0ae47ea
GC		 835 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
836 phys = <&usb2_phy1>;
837 phy-names = "usb2-phy";
838 maximum-speed = "high-speed";
839 dr_mode = "otg";
840 status = "disabled";
841 };
842 };
843
844 dwc3_2: omap_dwc3@483c0000 {
845 compatible = "ti,am437x-dwc3";
846 ti,hwmods = "usb_otg_ss1";
847 reg = <0x483c0000 0x10000>;
848 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
849 #address-cells = <1>;
850 #size-cells = <1>;
851 utmi-mode = <1>;
852 ranges;
853
854 usb2: usb@483d0000 {
855 compatible = "synopsys,dwc3";
4b143f0f 856 reg = <0x483d0000 0x10000>;
a0ae47ea
GC		 857 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
858 phys = <&usb2_phy2>;
859 phy-names = "usb2-phy";
860 maximum-speed = "high-speed";
861 dr_mode = "otg";
862 status = "disabled";
863 };
864 };
2a1a5043
SP		 865
866 qspi: qspi@47900000 {
867 compatible = "ti,am4372-qspi";
868 reg = <0x47900000 0x100>;
869 #address-cells = <1>;
870 #size-cells = <0>;
871 ti,hwmods = "qspi";
872 interrupts = <0 138 0x4>;
873 num-cs = <4>;
874 status = "disabled";
875 };
741cac5f
SP		 876
877 hdq: hdq@48347000 {
878 compatible = "ti,am43xx-hdq";
879 reg = <0x48347000 0x1000>;
880 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
881 clocks = <&func_12m_clk>;
882 clock-names = "fck";
883 ti,hwmods = "hdq1w";
884 status = "disabled";
885 };
8c793367
SP		 886
887 dss: dss@4832a000 {
888 compatible = "ti,omap3-dss";
889 reg = <0x4832a000 0x200>;
890 status = "disabled";
891 ti,hwmods = "dss_core";
892 clocks = <&disp_clk>;
893 clock-names = "fck";
894 #address-cells = <1>;
895 #size-cells = <1>;
896 ranges;
897
08ecb28a 898 dispc: dispc@4832a400 {
8c793367
SP		 899 compatible = "ti,omap3-dispc";
900 reg = <0x4832a400 0x400>;
901 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
902 ti,hwmods = "dss_dispc";
903 clocks = <&disp_clk>;
904 clock-names = "fck";
905 };
906
907 rfbi: rfbi@4832a800 {
908 compatible = "ti,omap3-rfbi";
909 reg = <0x4832a800 0x100>;
910 ti,hwmods = "dss_rfbi";
911 clocks = <&disp_clk>;
912 clock-names = "fck";
913 };
914 };
8b9a2810
RN		 915
916 ocmcram: ocmcram@40300000 {
917 compatible = "mmio-sram";
918 reg = <0x40300000 0x40000>; /* 256k */
919 };
6cfd8117
AM		 920 };
921};
6a679208
TK		 922
923/include/ "am43xx-clocks.dtsi"
Linux kernel - Deliverables
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