Commit | Line | Data |
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11e2191c LV |
1 | /* |
2 | * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | */ | |
8 | ||
9 | /* AM437x GP EVM */ | |
10 | ||
11 | /dts-v1/; | |
12 | ||
13 | #include "am4372.dtsi" | |
14 | #include <dt-bindings/pinctrl/am43xx.h> | |
c540b476 | 15 | #include <dt-bindings/pwm/pwm.h> |
51724dbb | 16 | #include <dt-bindings/gpio/gpio.h> |
11e2191c LV |
17 | |
18 | / { | |
19 | model = "TI AM437x GP EVM"; | |
20 | compatible = "ti,am437x-gp-evm","ti,am4372","ti,am43"; | |
c540b476 | 21 | |
0bacb529 SP |
22 | aliases { |
23 | display0 = &lcd0; | |
24 | }; | |
25 | ||
390810a9 | 26 | evm_v3_3d: fixedregulator-v3_3d { |
506be3fb | 27 | compatible = "regulator-fixed"; |
390810a9 | 28 | regulator-name = "evm_v3_3d"; |
506be3fb B |
29 | regulator-min-microvolt = <3300000>; |
30 | regulator-max-microvolt = <3300000>; | |
31 | enable-active-high; | |
32 | }; | |
33 | ||
b2873bfa DG |
34 | vtt_fixed: fixedregulator-vtt { |
35 | compatible = "regulator-fixed"; | |
36 | regulator-name = "vtt_fixed"; | |
37 | regulator-min-microvolt = <1500000>; | |
38 | regulator-max-microvolt = <1500000>; | |
39 | regulator-always-on; | |
40 | regulator-boot-on; | |
41 | enable-active-high; | |
42 | gpio = <&gpio5 7 GPIO_ACTIVE_HIGH>; | |
43 | }; | |
44 | ||
b6bbf598 ER |
45 | vmmcwl_fixed: fixedregulator-mmcwl { |
46 | compatible = "regulator-fixed"; | |
47 | regulator-name = "vmmcwl_fixed"; | |
48 | regulator-min-microvolt = <1800000>; | |
49 | regulator-max-microvolt = <1800000>; | |
50 | gpio = <&gpio1 20 GPIO_ACTIVE_HIGH>; | |
51 | enable-active-high; | |
52 | }; | |
53 | ||
c540b476 SP |
54 | backlight { |
55 | compatible = "pwm-backlight"; | |
56 | pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>; | |
57 | brightness-levels = <0 51 53 56 62 75 101 152 255>; | |
58 | default-brightness-level = <8>; | |
59 | }; | |
51724dbb SP |
60 | |
61 | matrix_keypad: matrix_keypad@0 { | |
62 | compatible = "gpio-matrix-keypad"; | |
63 | debounce-delay-ms = <5>; | |
64 | col-scan-delay-us = <2>; | |
65 | ||
66 | row-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH /* Bank3, pin21 */ | |
67 | &gpio4 3 GPIO_ACTIVE_HIGH /* Bank4, pin3 */ | |
68 | &gpio4 2 GPIO_ACTIVE_HIGH>; /* Bank4, pin2 */ | |
69 | ||
70 | col-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH /* Bank3, pin19 */ | |
71 | &gpio3 20 GPIO_ACTIVE_HIGH>; /* Bank3, pin20 */ | |
72 | ||
73 | linux,keymap = <0x00000201 /* P1 */ | |
74 | 0x00010202 /* P2 */ | |
75 | 0x01000067 /* UP */ | |
76 | 0x0101006a /* RIGHT */ | |
77 | 0x02000069 /* LEFT */ | |
78 | 0x0201006c>; /* DOWN */ | |
79 | }; | |
0bacb529 SP |
80 | |
81 | lcd0: display { | |
82 | compatible = "osddisplays,osd057T0559-34ts", "panel-dpi"; | |
83 | label = "lcd"; | |
84 | ||
0bacb529 SP |
85 | panel-timing { |
86 | clock-frequency = <33000000>; | |
87 | hactive = <800>; | |
88 | vactive = <480>; | |
89 | hfront-porch = <210>; | |
90 | hback-porch = <16>; | |
91 | hsync-len = <30>; | |
92 | vback-porch = <10>; | |
93 | vfront-porch = <22>; | |
94 | vsync-len = <13>; | |
95 | hsync-active = <0>; | |
96 | vsync-active = <0>; | |
97 | de-active = <1>; | |
98 | pixelclk-active = <1>; | |
99 | }; | |
100 | ||
101 | port { | |
102 | lcd_in: endpoint { | |
103 | remote-endpoint = <&dpi_out>; | |
104 | }; | |
105 | }; | |
106 | }; | |
3aa59200 LP |
107 | |
108 | /* fixed 12MHz oscillator */ | |
109 | refclk: oscillator { | |
110 | #clock-cells = <0>; | |
111 | compatible = "fixed-clock"; | |
112 | clock-frequency = <12000000>; | |
113 | }; | |
114 | ||
fff51e77 K |
115 | /* fixed 32k external oscillator clock */ |
116 | clk_32k_rtc: clk_32k_rtc { | |
117 | #clock-cells = <0>; | |
118 | compatible = "fixed-clock"; | |
119 | clock-frequency = <32768>; | |
120 | }; | |
121 | ||
4e8603ef | 122 | sound0: sound0 { |
cf9a4850 PU |
123 | compatible = "simple-audio-card"; |
124 | simple-audio-card,name = "AM437x-GP-EVM"; | |
125 | simple-audio-card,widgets = | |
126 | "Headphone", "Headphone Jack", | |
127 | "Line", "Line In"; | |
128 | simple-audio-card,routing = | |
129 | "Headphone Jack", "HPLOUT", | |
130 | "Headphone Jack", "HPROUT", | |
131 | "LINE1L", "Line In", | |
132 | "LINE1R", "Line In"; | |
133 | simple-audio-card,format = "dsp_b"; | |
134 | simple-audio-card,bitclock-master = <&sound0_master>; | |
135 | simple-audio-card,frame-master = <&sound0_master>; | |
136 | simple-audio-card,bitclock-inversion; | |
137 | ||
138 | simple-audio-card,cpu { | |
139 | sound-dai = <&mcasp1>; | |
140 | system-clock-frequency = <12000000>; | |
141 | }; | |
142 | ||
143 | sound0_master: simple-audio-card,codec { | |
144 | sound-dai = <&tlv320aic3106>; | |
145 | system-clock-frequency = <12000000>; | |
146 | }; | |
147 | }; | |
11e2191c LV |
148 | }; |
149 | ||
150 | &am43xx_pinmux { | |
b6bbf598 ER |
151 | pinctrl-names = "default", "sleep"; |
152 | pinctrl-0 = <&wlan_pins_default>; | |
153 | pinctrl-1 = <&wlan_pins_sleep>; | |
154 | ||
11e2191c LV |
155 | i2c0_pins: i2c0_pins { |
156 | pinctrl-single,pins = < | |
596bad7d JMC |
157 | AM4372_IOPAD(0x988, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_sda.i2c0_sda */ |
158 | AM4372_IOPAD(0x98c, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */ | |
11e2191c LV |
159 | >; |
160 | }; | |
161 | ||
162 | i2c1_pins: i2c1_pins { | |
163 | pinctrl-single,pins = < | |
596bad7d JMC |
164 | AM4372_IOPAD(0x95c, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE2) /* spi0_cs0.i2c1_scl */ |
165 | AM4372_IOPAD(0x958, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE2) /* spi0_d1.i2c1_sda */ | |
11e2191c LV |
166 | >; |
167 | }; | |
c540b476 | 168 | |
506be3fb B |
169 | mmc1_pins: pinmux_mmc1_pins { |
170 | pinctrl-single,pins = < | |
596bad7d | 171 | AM4372_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */ |
506be3fb B |
172 | >; |
173 | }; | |
174 | ||
c540b476 SP |
175 | ecap0_pins: backlight_pins { |
176 | pinctrl-single,pins = < | |
596bad7d | 177 | AM4372_IOPAD(0x964, MUX_MODE0) /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */ |
c540b476 SP |
178 | >; |
179 | }; | |
0ebc1e25 SN |
180 | |
181 | pixcir_ts_pins: pixcir_ts_pins { | |
182 | pinctrl-single,pins = < | |
596bad7d | 183 | AM4372_IOPAD(0xa64, PIN_INPUT_PULLUP | MUX_MODE7) /* spi2_d0.gpio3_22 */ |
0ebc1e25 SN |
184 | >; |
185 | }; | |
7b25babf M |
186 | |
187 | cpsw_default: cpsw_default { | |
188 | pinctrl-single,pins = < | |
189 | /* Slave 1 */ | |
596bad7d JMC |
190 | AM4372_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_txen */ |
191 | AM4372_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxdv.rgmii1_rxctl */ | |
192 | AM4372_IOPAD(0x91c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_txd3 */ | |
193 | AM4372_IOPAD(0x920, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_txd2 */ | |
194 | AM4372_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_txd1 */ | |
195 | AM4372_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_txd0 */ | |
196 | AM4372_IOPAD(0x92c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rmii1_tclk */ | |
197 | AM4372_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxclk.rmii1_rclk */ | |
198 | AM4372_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rxd3 */ | |
199 | AM4372_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rxd2 */ | |
200 | AM4372_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rxd1 */ | |
201 | AM4372_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rxd0 */ | |
7b25babf M |
202 | >; |
203 | }; | |
204 | ||
205 | cpsw_sleep: cpsw_sleep { | |
206 | pinctrl-single,pins = < | |
207 | /* Slave 1 reset value */ | |
596bad7d JMC |
208 | AM4372_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7) |
209 | AM4372_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7) | |
210 | AM4372_IOPAD(0x91c, PIN_INPUT_PULLDOWN | MUX_MODE7) | |
211 | AM4372_IOPAD(0x920, PIN_INPUT_PULLDOWN | MUX_MODE7) | |
212 | AM4372_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7) | |
213 | AM4372_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7) | |
214 | AM4372_IOPAD(0x92c, PIN_INPUT_PULLDOWN | MUX_MODE7) | |
215 | AM4372_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE7) | |
216 | AM4372_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE7) | |
217 | AM4372_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE7) | |
218 | AM4372_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7) | |
219 | AM4372_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7) | |
7b25babf M |
220 | >; |
221 | }; | |
222 | ||
223 | davinci_mdio_default: davinci_mdio_default { | |
224 | pinctrl-single,pins = < | |
225 | /* MDIO */ | |
596bad7d JMC |
226 | AM4372_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ |
227 | AM4372_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ | |
7b25babf M |
228 | >; |
229 | }; | |
230 | ||
231 | davinci_mdio_sleep: davinci_mdio_sleep { | |
232 | pinctrl-single,pins = < | |
233 | /* MDIO reset value */ | |
596bad7d JMC |
234 | AM4372_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7) |
235 | AM4372_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7) | |
7b25babf M |
236 | >; |
237 | }; | |
99ffa642 PG |
238 | |
239 | nand_flash_x8: nand_flash_x8 { | |
240 | pinctrl-single,pins = < | |
596bad7d JMC |
241 | AM4372_IOPAD(0x800, PIN_INPUT | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */ |
242 | AM4372_IOPAD(0x804, PIN_INPUT | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */ | |
243 | AM4372_IOPAD(0x808, PIN_INPUT | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */ | |
244 | AM4372_IOPAD(0x80c, PIN_INPUT | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */ | |
245 | AM4372_IOPAD(0x810, PIN_INPUT | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */ | |
246 | AM4372_IOPAD(0x814, PIN_INPUT | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */ | |
247 | AM4372_IOPAD(0x818, PIN_INPUT | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */ | |
248 | AM4372_IOPAD(0x81c, PIN_INPUT | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */ | |
249 | AM4372_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */ | |
250 | AM4372_IOPAD(0x874, PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpmc_wpn */ | |
251 | AM4372_IOPAD(0x87c, PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */ | |
252 | AM4372_IOPAD(0x890, PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */ | |
253 | AM4372_IOPAD(0x894, PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */ | |
254 | AM4372_IOPAD(0x898, PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */ | |
255 | AM4372_IOPAD(0x89c, PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */ | |
99ffa642 PG |
256 | >; |
257 | }; | |
0bacb529 SP |
258 | |
259 | dss_pins: dss_pins { | |
260 | pinctrl-single,pins = < | |
596bad7d JMC |
261 | AM4372_IOPAD(0x820, PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 8 -> DSS DATA 23 */ |
262 | AM4372_IOPAD(0x824, PIN_OUTPUT_PULLUP | MUX_MODE1) | |
263 | AM4372_IOPAD(0x828, PIN_OUTPUT_PULLUP | MUX_MODE1) | |
264 | AM4372_IOPAD(0x82c, PIN_OUTPUT_PULLUP | MUX_MODE1) | |
265 | AM4372_IOPAD(0x830, PIN_OUTPUT_PULLUP | MUX_MODE1) | |
266 | AM4372_IOPAD(0x834, PIN_OUTPUT_PULLUP | MUX_MODE1) | |
267 | AM4372_IOPAD(0x838, PIN_OUTPUT_PULLUP | MUX_MODE1) | |
268 | AM4372_IOPAD(0x83c, PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 15 -> DSS DATA 16 */ | |
269 | AM4372_IOPAD(0x8a0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 0 */ | |
270 | AM4372_IOPAD(0x8a4, PIN_OUTPUT_PULLUP | MUX_MODE0) | |
271 | AM4372_IOPAD(0x8a8, PIN_OUTPUT_PULLUP | MUX_MODE0) | |
272 | AM4372_IOPAD(0x8ac, PIN_OUTPUT_PULLUP | MUX_MODE0) | |
273 | AM4372_IOPAD(0x8b0, PIN_OUTPUT_PULLUP | MUX_MODE0) | |
274 | AM4372_IOPAD(0x8b4, PIN_OUTPUT_PULLUP | MUX_MODE0) | |
275 | AM4372_IOPAD(0x8b8, PIN_OUTPUT_PULLUP | MUX_MODE0) | |
276 | AM4372_IOPAD(0x8bc, PIN_OUTPUT_PULLUP | MUX_MODE0) | |
277 | AM4372_IOPAD(0x8c0, PIN_OUTPUT_PULLUP | MUX_MODE0) | |
278 | AM4372_IOPAD(0x8c4, PIN_OUTPUT_PULLUP | MUX_MODE0) | |
279 | AM4372_IOPAD(0x8c8, PIN_OUTPUT_PULLUP | MUX_MODE0) | |
280 | AM4372_IOPAD(0x8cc, PIN_OUTPUT_PULLUP | MUX_MODE0) | |
281 | AM4372_IOPAD(0x8d0, PIN_OUTPUT_PULLUP | MUX_MODE0) | |
282 | AM4372_IOPAD(0x8d4, PIN_OUTPUT_PULLUP | MUX_MODE0) | |
283 | AM4372_IOPAD(0x8d8, PIN_OUTPUT_PULLUP | MUX_MODE0) | |
284 | AM4372_IOPAD(0x8dc, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 15 */ | |
285 | AM4372_IOPAD(0x8e0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS VSYNC */ | |
286 | AM4372_IOPAD(0x8e4, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS HSYNC */ | |
287 | AM4372_IOPAD(0x8e8, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS PCLK */ | |
288 | AM4372_IOPAD(0x8ec, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS AC BIAS EN */ | |
0bacb529 SP |
289 | |
290 | >; | |
291 | }; | |
292 | ||
593113e7 | 293 | display_mux_pins: display_mux_pins { |
0bacb529 SP |
294 | pinctrl-single,pins = < |
295 | /* GPIO 5_8 to select LCD / HDMI */ | |
596bad7d | 296 | AM4372_IOPAD(0xa38, PIN_OUTPUT_PULLUP | MUX_MODE7) |
0bacb529 SP |
297 | >; |
298 | }; | |
4b1ce235 M |
299 | |
300 | dcan0_default: dcan0_default_pins { | |
301 | pinctrl-single,pins = < | |
596bad7d JMC |
302 | AM4372_IOPAD(0x978, PIN_OUTPUT | MUX_MODE2) /* uart1_ctsn.d_can0_tx */ |
303 | AM4372_IOPAD(0x97c, PIN_INPUT_PULLUP | MUX_MODE2) /* uart1_rtsn.d_can0_rx */ | |
4b1ce235 M |
304 | >; |
305 | }; | |
306 | ||
f95b1064 RQ |
307 | dcan0_sleep: dcan0_sleep_pins { |
308 | pinctrl-single,pins = < | |
596bad7d JMC |
309 | AM4372_IOPAD(0x978, PIN_INPUT_PULLUP | MUX_MODE7) /* uart1_ctsn.gpio0_12 */ |
310 | AM4372_IOPAD(0x97c, PIN_INPUT_PULLUP | MUX_MODE7) /* uart1_rtsn.gpio0_13 */ | |
f95b1064 RQ |
311 | >; |
312 | }; | |
313 | ||
4b1ce235 M |
314 | dcan1_default: dcan1_default_pins { |
315 | pinctrl-single,pins = < | |
596bad7d JMC |
316 | AM4372_IOPAD(0x980, PIN_OUTPUT | MUX_MODE2) /* uart1_rxd.d_can1_tx */ |
317 | AM4372_IOPAD(0x984, PIN_INPUT_PULLUP | MUX_MODE2) /* uart1_txd.d_can1_rx */ | |
4b1ce235 M |
318 | >; |
319 | }; | |
c788a7f4 | 320 | |
f95b1064 RQ |
321 | dcan1_sleep: dcan1_sleep_pins { |
322 | pinctrl-single,pins = < | |
596bad7d JMC |
323 | AM4372_IOPAD(0x980, PIN_INPUT_PULLUP | MUX_MODE7) /* uart1_rxd.gpio0_14 */ |
324 | AM4372_IOPAD(0x984, PIN_INPUT_PULLUP | MUX_MODE7) /* uart1_txd.gpio0_15 */ | |
f95b1064 RQ |
325 | >; |
326 | }; | |
327 | ||
c788a7f4 BP |
328 | vpfe0_pins_default: vpfe0_pins_default { |
329 | pinctrl-single,pins = < | |
596bad7d JMC |
330 | AM4372_IOPAD(0x9b0, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_hd mode 0*/ |
331 | AM4372_IOPAD(0x9b4, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_vd mode 0*/ | |
332 | AM4372_IOPAD(0x9c0, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_pclk mode 0*/ | |
333 | AM4372_IOPAD(0x9c4, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data8 mode 0*/ | |
334 | AM4372_IOPAD(0x9c8, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data9 mode 0*/ | |
335 | AM4372_IOPAD(0xa08, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data0 mode 0*/ | |
336 | AM4372_IOPAD(0xa0c, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data1 mode 0*/ | |
337 | AM4372_IOPAD(0xa10, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data2 mode 0*/ | |
338 | AM4372_IOPAD(0xa14, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data3 mode 0*/ | |
339 | AM4372_IOPAD(0xa18, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data4 mode 0*/ | |
340 | AM4372_IOPAD(0xa1c, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data5 mode 0*/ | |
341 | AM4372_IOPAD(0xa20, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data6 mode 0*/ | |
342 | AM4372_IOPAD(0xa24, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data7 mode 0*/ | |
c788a7f4 BP |
343 | >; |
344 | }; | |
345 | ||
346 | vpfe0_pins_sleep: vpfe0_pins_sleep { | |
347 | pinctrl-single,pins = < | |
596bad7d JMC |
348 | AM4372_IOPAD(0x9b0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_hd mode 0*/ |
349 | AM4372_IOPAD(0x9b4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_vd mode 0*/ | |
350 | AM4372_IOPAD(0x9c0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_pclk mode 0*/ | |
351 | AM4372_IOPAD(0x9c4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data8 mode 0*/ | |
352 | AM4372_IOPAD(0x9c8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data9 mode 0*/ | |
353 | AM4372_IOPAD(0xa08, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data0 mode 0*/ | |
354 | AM4372_IOPAD(0xa0c, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data1 mode 0*/ | |
355 | AM4372_IOPAD(0xa10, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data2 mode 0*/ | |
356 | AM4372_IOPAD(0xa14, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data3 mode 0*/ | |
357 | AM4372_IOPAD(0xa18, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data4 mode 0*/ | |
358 | AM4372_IOPAD(0xa1c, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data5 mode 0*/ | |
359 | AM4372_IOPAD(0xa20, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data6 mode 0*/ | |
360 | AM4372_IOPAD(0xa24, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data7 mode 0*/ | |
c788a7f4 BP |
361 | >; |
362 | }; | |
363 | ||
364 | vpfe1_pins_default: vpfe1_pins_default { | |
365 | pinctrl-single,pins = < | |
596bad7d JMC |
366 | AM4372_IOPAD(0x9cc, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data9 mode 0*/ |
367 | AM4372_IOPAD(0x9d0, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data8 mode 0*/ | |
368 | AM4372_IOPAD(0x9d4, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_hd mode 0*/ | |
369 | AM4372_IOPAD(0x9d8, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_vd mode 0*/ | |
370 | AM4372_IOPAD(0x9dC, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_pclk mode 0*/ | |
371 | AM4372_IOPAD(0x9e8, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data0 mode 0*/ | |
372 | AM4372_IOPAD(0x9ec, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data1 mode 0*/ | |
373 | AM4372_IOPAD(0x9f0, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data2 mode 0*/ | |
374 | AM4372_IOPAD(0x9f4, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data3 mode 0*/ | |
375 | AM4372_IOPAD(0x9f8, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data4 mode 0*/ | |
376 | AM4372_IOPAD(0x9fc, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data5 mode 0*/ | |
377 | AM4372_IOPAD(0xa00, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data6 mode 0*/ | |
378 | AM4372_IOPAD(0xa04, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data7 mode 0*/ | |
c788a7f4 BP |
379 | >; |
380 | }; | |
381 | ||
382 | vpfe1_pins_sleep: vpfe1_pins_sleep { | |
383 | pinctrl-single,pins = < | |
596bad7d JMC |
384 | AM4372_IOPAD(0x9cc, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data9 mode 0*/ |
385 | AM4372_IOPAD(0x9d0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data8 mode 0*/ | |
386 | AM4372_IOPAD(0x9d4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_hd mode 0*/ | |
387 | AM4372_IOPAD(0x9d8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_vd mode 0*/ | |
388 | AM4372_IOPAD(0x9dc, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_pclk mode 0*/ | |
389 | AM4372_IOPAD(0x9e8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data0 mode 0*/ | |
390 | AM4372_IOPAD(0x9ec, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data1 mode 0*/ | |
391 | AM4372_IOPAD(0x9f0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data2 mode 0*/ | |
392 | AM4372_IOPAD(0x9f4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data3 mode 0*/ | |
393 | AM4372_IOPAD(0x9f8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data4 mode 0*/ | |
394 | AM4372_IOPAD(0x9fc, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data5 mode 0*/ | |
395 | AM4372_IOPAD(0xa00, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data6 mode 0*/ | |
396 | AM4372_IOPAD(0xa04, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data7 mode 0*/ | |
c788a7f4 BP |
397 | >; |
398 | }; | |
b6bbf598 ER |
399 | |
400 | mmc3_pins_default: pinmux_mmc3_pins_default { | |
401 | pinctrl-single,pins = < | |
596bad7d JMC |
402 | AM4372_IOPAD(0x88c, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_clk.mmc2_clk */ |
403 | AM4372_IOPAD(0x888, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_csn3.mmc2_cmd */ | |
404 | AM4372_IOPAD(0x844, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a1.mmc2_dat0 */ | |
405 | AM4372_IOPAD(0x848, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a2.mmc2_dat1 */ | |
406 | AM4372_IOPAD(0x84c, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a3.mmc2_dat2 */ | |
407 | AM4372_IOPAD(0x878, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_be1n.mmc2_dat3 */ | |
b6bbf598 ER |
408 | >; |
409 | }; | |
410 | ||
411 | mmc3_pins_sleep: pinmux_mmc3_pins_sleep { | |
412 | pinctrl-single,pins = < | |
596bad7d JMC |
413 | AM4372_IOPAD(0x88c, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_clk.mmc2_clk */ |
414 | AM4372_IOPAD(0x888, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_csn3.mmc2_cmd */ | |
415 | AM4372_IOPAD(0x844, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a1.mmc2_dat0 */ | |
416 | AM4372_IOPAD(0x848, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a2.mmc2_dat1 */ | |
417 | AM4372_IOPAD(0x84c, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a3.mmc2_dat2 */ | |
418 | AM4372_IOPAD(0x878, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_be1n.mmc2_dat3 */ | |
b6bbf598 ER |
419 | >; |
420 | }; | |
421 | ||
422 | wlan_pins_default: pinmux_wlan_pins_default { | |
423 | pinctrl-single,pins = < | |
596bad7d JMC |
424 | AM4372_IOPAD(0x850, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a4.gpio1_20 WL_EN */ |
425 | AM4372_IOPAD(0x85c, PIN_INPUT | WAKEUP_ENABLE | MUX_MODE7) /* gpmc_a7.gpio1_23 WL_IRQ*/ | |
426 | AM4372_IOPAD(0x840, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a0.gpio1_16 BT_EN*/ | |
b6bbf598 ER |
427 | >; |
428 | }; | |
429 | ||
430 | wlan_pins_sleep: pinmux_wlan_pins_sleep { | |
431 | pinctrl-single,pins = < | |
596bad7d JMC |
432 | AM4372_IOPAD(0x850, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a4.gpio1_20 WL_EN */ |
433 | AM4372_IOPAD(0x85c, PIN_INPUT | WAKEUP_ENABLE | MUX_MODE7) /* gpmc_a7.gpio1_23 WL_IRQ*/ | |
434 | AM4372_IOPAD(0x840, PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a0.gpio1_16 BT_EN*/ | |
b6bbf598 ER |
435 | >; |
436 | }; | |
437 | ||
438 | uart3_pins: uart3_pins { | |
439 | pinctrl-single,pins = < | |
596bad7d JMC |
440 | AM4372_IOPAD(0xa28, PIN_INPUT | MUX_MODE0) /* uart3_rxd.uart3_rxd */ |
441 | AM4372_IOPAD(0xa2c, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart3_txd.uart3_txd */ | |
442 | AM4372_IOPAD(0xa30, PIN_INPUT_PULLUP | MUX_MODE0) /* uart3_ctsn.uart3_ctsn */ | |
443 | AM4372_IOPAD(0xa34, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart3_rtsn.uart3_rtsn */ | |
b6bbf598 ER |
444 | >; |
445 | }; | |
d3d92af1 PU |
446 | |
447 | mcasp1_pins: mcasp1_pins { | |
448 | pinctrl-single,pins = < | |
596bad7d JMC |
449 | AM4372_IOPAD(0x908, PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* mii1_col.mcasp1_axr2 */ |
450 | AM4372_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_crs.mcasp1_aclkx */ | |
451 | AM4372_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_rxerr.mcasp1_fsx */ | |
452 | AM4372_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */ | |
d3d92af1 PU |
453 | >; |
454 | }; | |
455 | ||
456 | mcasp1_sleep_pins: mcasp1_sleep_pins { | |
457 | pinctrl-single,pins = < | |
596bad7d JMC |
458 | AM4372_IOPAD(0x908, PIN_INPUT_PULLDOWN | MUX_MODE7) |
459 | AM4372_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE7) | |
460 | AM4372_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE7) | |
461 | AM4372_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE7) | |
d3d92af1 PU |
462 | >; |
463 | }; | |
50336f51 RQ |
464 | |
465 | gpio0_pins: gpio0_pins { | |
466 | pinctrl-single,pins = < | |
596bad7d | 467 | AM4372_IOPAD(0xa6c, PIN_OUTPUT | MUX_MODE9) /* spi2_cs0.gpio0_23 SEL_eMMCorNANDn */ |
50336f51 RQ |
468 | >; |
469 | }; | |
eb157c81 RQ |
470 | |
471 | emmc_pins_default: emmc_pins_default { | |
472 | pinctrl-single,pins = < | |
596bad7d JMC |
473 | AM4372_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */ |
474 | AM4372_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */ | |
475 | AM4372_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */ | |
476 | AM4372_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */ | |
477 | AM4372_IOPAD(0x810, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */ | |
478 | AM4372_IOPAD(0x814, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */ | |
479 | AM4372_IOPAD(0x818, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */ | |
480 | AM4372_IOPAD(0x81c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */ | |
481 | AM4372_IOPAD(0x880, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk */ | |
482 | AM4372_IOPAD(0x884, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd */ | |
eb157c81 RQ |
483 | >; |
484 | }; | |
485 | ||
486 | emmc_pins_sleep: emmc_pins_sleep { | |
487 | pinctrl-single,pins = < | |
596bad7d JMC |
488 | AM4372_IOPAD(0x800, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad0.gpio1_0 */ |
489 | AM4372_IOPAD(0x804, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad1.gpio1_1 */ | |
490 | AM4372_IOPAD(0x808, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad2.gpio1_2 */ | |
491 | AM4372_IOPAD(0x80c, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad3.gpio1_3 */ | |
492 | AM4372_IOPAD(0x810, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad4.gpio1_4 */ | |
493 | AM4372_IOPAD(0x814, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad5.gpio1_5 */ | |
494 | AM4372_IOPAD(0x818, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad6.gpio1_6 */ | |
495 | AM4372_IOPAD(0x81c, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad7.gpio1_7 */ | |
496 | AM4372_IOPAD(0x880, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_csn1.gpio1_30 */ | |
497 | AM4372_IOPAD(0x884, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_csn2.gpio1_31 */ | |
eb157c81 RQ |
498 | >; |
499 | }; | |
11e2191c LV |
500 | }; |
501 | ||
502 | &i2c0 { | |
1fc98144 K |
503 | status = "okay"; |
504 | pinctrl-names = "default"; | |
505 | pinctrl-0 = <&i2c0_pins>; | |
93166413 | 506 | clock-frequency = <100000>; |
0e2da5e6 K |
507 | |
508 | tps65218: tps65218@24 { | |
509 | reg = <0x24>; | |
510 | compatible = "ti,tps65218"; | |
511 | interrupts = <GIC_SPI 7 IRQ_TYPE_NONE>; /* NMIn */ | |
0e2da5e6 K |
512 | interrupt-controller; |
513 | #interrupt-cells = <2>; | |
514 | ||
515 | dcdc1: regulator-dcdc1 { | |
516 | compatible = "ti,tps65218-dcdc1"; | |
517 | regulator-name = "vdd_core"; | |
518 | regulator-min-microvolt = <912000>; | |
519 | regulator-max-microvolt = <1144000>; | |
520 | regulator-boot-on; | |
521 | regulator-always-on; | |
522 | }; | |
523 | ||
524 | dcdc2: regulator-dcdc2 { | |
525 | compatible = "ti,tps65218-dcdc2"; | |
526 | regulator-name = "vdd_mpu"; | |
527 | regulator-min-microvolt = <912000>; | |
528 | regulator-max-microvolt = <1378000>; | |
529 | regulator-boot-on; | |
530 | regulator-always-on; | |
531 | }; | |
532 | ||
533 | dcdc3: regulator-dcdc3 { | |
534 | compatible = "ti,tps65218-dcdc3"; | |
535 | regulator-name = "vdcdc3"; | |
3015ddbd K |
536 | regulator-min-microvolt = <1500000>; |
537 | regulator-max-microvolt = <1500000>; | |
0e2da5e6 K |
538 | regulator-boot-on; |
539 | regulator-always-on; | |
540 | }; | |
541 | dcdc5: regulator-dcdc5 { | |
542 | compatible = "ti,tps65218-dcdc5"; | |
543 | regulator-name = "v1_0bat"; | |
544 | regulator-min-microvolt = <1000000>; | |
545 | regulator-max-microvolt = <1000000>; | |
1e9f7474 DG |
546 | regulator-boot-on; |
547 | regulator-always-on; | |
0e2da5e6 K |
548 | }; |
549 | ||
550 | dcdc6: regulator-dcdc6 { | |
551 | compatible = "ti,tps65218-dcdc6"; | |
552 | regulator-name = "v1_8bat"; | |
553 | regulator-min-microvolt = <1800000>; | |
554 | regulator-max-microvolt = <1800000>; | |
1e9f7474 DG |
555 | regulator-boot-on; |
556 | regulator-always-on; | |
0e2da5e6 K |
557 | }; |
558 | ||
559 | ldo1: regulator-ldo1 { | |
560 | compatible = "ti,tps65218-ldo1"; | |
561 | regulator-min-microvolt = <1800000>; | |
562 | regulator-max-microvolt = <1800000>; | |
563 | regulator-boot-on; | |
564 | regulator-always-on; | |
565 | }; | |
566 | }; | |
3aa59200 LP |
567 | |
568 | ov2659@30 { | |
569 | compatible = "ovti,ov2659"; | |
570 | reg = <0x30>; | |
571 | ||
572 | clocks = <&refclk 0>; | |
573 | clock-names = "xvclk"; | |
574 | ||
575 | port { | |
576 | ov2659_0: endpoint { | |
577 | remote-endpoint = <&vpfe1_ep>; | |
578 | link-frequencies = /bits/ 64 <70000000>; | |
579 | }; | |
580 | }; | |
581 | }; | |
11e2191c LV |
582 | }; |
583 | ||
584 | &i2c1 { | |
1fc98144 K |
585 | status = "okay"; |
586 | pinctrl-names = "default"; | |
587 | pinctrl-0 = <&i2c1_pins>; | |
0ebc1e25 SN |
588 | pixcir_ts@5c { |
589 | compatible = "pixcir,pixcir_tangoc"; | |
590 | pinctrl-names = "default"; | |
591 | pinctrl-0 = <&pixcir_ts_pins>; | |
592 | reg = <0x5c>; | |
0ebc1e25 SN |
593 | |
594 | attb-gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; | |
595 | ||
f513d22c V |
596 | /* |
597 | * 0x264 represents the offset of padconf register of | |
598 | * gpio3_22 from am43xx_pinmux base. | |
599 | */ | |
95e7d03e | 600 | interrupts-extended = <&gpio3 22 IRQ_TYPE_EDGE_FALLING>, |
f513d22c V |
601 | <&am43xx_pinmux 0x264>; |
602 | interrupt-names = "tsc", "wakeup"; | |
603 | ||
f048615e RQ |
604 | touchscreen-size-x = <1024>; |
605 | touchscreen-size-y = <600>; | |
f513d22c | 606 | wakeup-source; |
0ebc1e25 | 607 | }; |
3aa59200 LP |
608 | |
609 | ov2659@30 { | |
610 | compatible = "ovti,ov2659"; | |
611 | reg = <0x30>; | |
612 | ||
613 | clocks = <&refclk 0>; | |
614 | clock-names = "xvclk"; | |
615 | ||
616 | port { | |
617 | ov2659_1: endpoint { | |
618 | remote-endpoint = <&vpfe0_ep>; | |
619 | link-frequencies = /bits/ 64 <70000000>; | |
620 | }; | |
621 | }; | |
622 | }; | |
6076b159 PU |
623 | |
624 | tlv320aic3106: tlv320aic3106@1b { | |
cf9a4850 | 625 | #sound-dai-cells = <0>; |
6076b159 PU |
626 | compatible = "ti,tlv320aic3106"; |
627 | reg = <0x1b>; | |
628 | status = "okay"; | |
629 | ||
630 | /* Regulators */ | |
631 | IOVDD-supply = <&evm_v3_3d>; /* V3_3D -> <tps63031> EN: V1_8D -> VBAT */ | |
632 | AVDD-supply = <&evm_v3_3d>; /* v3_3AUD -> V3_3D -> ... */ | |
633 | DRVDD-supply = <&evm_v3_3d>; /* v3_3AUD -> V3_3D -> ... */ | |
634 | DVDD-supply = <&ldo1>; /* V1_8D -> LDO1 */ | |
635 | }; | |
11e2191c | 636 | }; |
c540b476 SP |
637 | |
638 | &epwmss0 { | |
639 | status = "okay"; | |
640 | }; | |
641 | ||
0f39f7b9 V |
642 | &tscadc { |
643 | status = "okay"; | |
644 | ||
645 | adc { | |
646 | ti,adc-channels = <0 1 2 3 4 5 6 7>; | |
647 | }; | |
648 | }; | |
649 | ||
c540b476 SP |
650 | &ecap0 { |
651 | status = "okay"; | |
652 | pinctrl-names = "default"; | |
653 | pinctrl-0 = <&ecap0_pins>; | |
654 | }; | |
d3d46cca | 655 | |
506be3fb | 656 | &gpio0 { |
50336f51 RQ |
657 | pinctrl-names = "default"; |
658 | pinctrl-0 = <&gpio0_pins>; | |
506be3fb | 659 | status = "okay"; |
50336f51 RQ |
660 | |
661 | p23 { | |
662 | gpio-hog; | |
663 | gpios = <23 GPIO_ACTIVE_HIGH>; | |
664 | /* SelEMMCorNAND selects between eMMC and NAND: | |
665 | * Low: NAND | |
666 | * High: eMMC | |
667 | * When changing this line make sure the newly | |
668 | * selected device node is enabled and the previously | |
669 | * selected device node is disabled. | |
670 | */ | |
671 | output-low; | |
672 | line-name = "SelEMMCorNAND"; | |
673 | }; | |
506be3fb B |
674 | }; |
675 | ||
b6bbf598 ER |
676 | &gpio1 { |
677 | status = "okay"; | |
678 | }; | |
679 | ||
d3d46cca SP |
680 | &gpio3 { |
681 | status = "okay"; | |
682 | }; | |
683 | ||
684 | &gpio4 { | |
685 | status = "okay"; | |
686 | }; | |
506be3fb | 687 | |
1ff3859e | 688 | &gpio5 { |
593113e7 PU |
689 | pinctrl-names = "default"; |
690 | pinctrl-0 = <&display_mux_pins>; | |
1ff3859e DG |
691 | status = "okay"; |
692 | ti,no-reset-on-init; | |
593113e7 PU |
693 | |
694 | p8 { | |
695 | /* | |
696 | * SelLCDorHDMI selects between display and audio paths: | |
697 | * Low: HDMI display with audio via HDMI | |
698 | * High: LCD display with analog audio via aic3111 codec | |
699 | */ | |
700 | gpio-hog; | |
701 | gpios = <8 GPIO_ACTIVE_HIGH>; | |
702 | output-high; | |
703 | line-name = "SelLCDorHDMI"; | |
704 | }; | |
1ff3859e DG |
705 | }; |
706 | ||
506be3fb B |
707 | &mmc1 { |
708 | status = "okay"; | |
390810a9 | 709 | vmmc-supply = <&evm_v3_3d>; |
506be3fb B |
710 | bus-width = <4>; |
711 | pinctrl-names = "default"; | |
712 | pinctrl-0 = <&mmc1_pins>; | |
0731cbdd | 713 | cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; |
506be3fb | 714 | }; |
b5820d3a | 715 | |
eb157c81 RQ |
716 | /* eMMC sits on mmc2 */ |
717 | &mmc2 { | |
718 | /* | |
719 | * When enabling eMMC, disable GPMC/NAND and set | |
720 | * SelEMMCorNAND to output-high | |
721 | */ | |
722 | status = "disabled"; | |
723 | vmmc-supply = <&evm_v3_3d>; | |
724 | bus-width = <8>; | |
725 | pinctrl-names = "default", "sleep"; | |
726 | pinctrl-0 = <&emmc_pins_default>; | |
727 | pinctrl-1 = <&emmc_pins_sleep>; | |
728 | ti,non-removable; | |
729 | }; | |
730 | ||
b6bbf598 ER |
731 | &mmc3 { |
732 | status = "okay"; | |
733 | /* these are on the crossbar and are outlined in the | |
734 | xbar-event-map element */ | |
cce1ee00 PU |
735 | dmas = <&edma_xbar 30 0 1>, |
736 | <&edma_xbar 31 0 2>; | |
b6bbf598 ER |
737 | dma-names = "tx", "rx"; |
738 | vmmc-supply = <&vmmcwl_fixed>; | |
739 | bus-width = <4>; | |
740 | pinctrl-names = "default", "sleep"; | |
741 | pinctrl-0 = <&mmc3_pins_default>; | |
742 | pinctrl-1 = <&mmc3_pins_sleep>; | |
743 | cap-power-off-card; | |
744 | keep-power-in-suspend; | |
745 | ti,non-removable; | |
746 | ||
747 | #address-cells = <1>; | |
748 | #size-cells = <0>; | |
749 | wlcore: wlcore@0 { | |
750 | compatible = "ti,wl1835"; | |
751 | reg = <2>; | |
752 | interrupt-parent = <&gpio1>; | |
753 | interrupts = <23 IRQ_TYPE_LEVEL_HIGH>; | |
754 | }; | |
755 | }; | |
756 | ||
b6bbf598 ER |
757 | &uart3 { |
758 | status = "okay"; | |
759 | pinctrl-names = "default"; | |
760 | pinctrl-0 = <&uart3_pins>; | |
761 | }; | |
762 | ||
b5820d3a GC |
763 | &usb2_phy1 { |
764 | status = "okay"; | |
765 | }; | |
766 | ||
767 | &usb1 { | |
768 | dr_mode = "peripheral"; | |
769 | status = "okay"; | |
770 | }; | |
771 | ||
772 | &usb2_phy2 { | |
773 | status = "okay"; | |
774 | }; | |
775 | ||
776 | &usb2 { | |
777 | dr_mode = "host"; | |
778 | status = "okay"; | |
779 | }; | |
7b25babf M |
780 | |
781 | &mac { | |
782 | slaves = <1>; | |
783 | pinctrl-names = "default", "sleep"; | |
784 | pinctrl-0 = <&cpsw_default>; | |
785 | pinctrl-1 = <&cpsw_sleep>; | |
786 | status = "okay"; | |
787 | }; | |
788 | ||
789 | &davinci_mdio { | |
790 | pinctrl-names = "default", "sleep"; | |
791 | pinctrl-0 = <&davinci_mdio_default>; | |
792 | pinctrl-1 = <&davinci_mdio_sleep>; | |
793 | status = "okay"; | |
794 | }; | |
795 | ||
796 | &cpsw_emac0 { | |
797 | phy_id = <&davinci_mdio>, <0>; | |
798 | phy-mode = "rgmii"; | |
799 | }; | |
99ffa642 PG |
800 | |
801 | &elm { | |
802 | status = "okay"; | |
803 | }; | |
804 | ||
805 | &gpmc { | |
eb157c81 RQ |
806 | /* |
807 | * When enabling GPMC, disable eMMC and set | |
808 | * SelEMMCorNAND to output-low | |
809 | */ | |
99ffa642 PG |
810 | status = "okay"; |
811 | pinctrl-names = "default"; | |
812 | pinctrl-0 = <&nand_flash_x8>; | |
be3f39c8 | 813 | ranges = <0 0 0x08000000 0x01000000>; /* CS0 space. Min partition = 16MB */ |
99ffa642 | 814 | nand@0,0 { |
be3f39c8 | 815 | compatible = "ti,omap2-nand"; |
99ffa642 | 816 | reg = <0 0 4>; /* device IO registers */ |
be3f39c8 RQ |
817 | interrupt-parent = <&gpmc>; |
818 | interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ | |
819 | <1 IRQ_TYPE_NONE>; /* termcount */ | |
99a41011 | 820 | rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */ |
6b869110 | 821 | ti,nand-ecc-opt = "bch16"; |
99ffa642 PG |
822 | ti,elm-id = <&elm>; |
823 | nand-bus-width = <8>; | |
824 | gpmc,device-width = <1>; | |
825 | gpmc,sync-clk-ps = <0>; | |
826 | gpmc,cs-on-ns = <0>; | |
827 | gpmc,cs-rd-off-ns = <40>; | |
828 | gpmc,cs-wr-off-ns = <40>; | |
829 | gpmc,adv-on-ns = <0>; | |
830 | gpmc,adv-rd-off-ns = <25>; | |
831 | gpmc,adv-wr-off-ns = <25>; | |
832 | gpmc,we-on-ns = <0>; | |
833 | gpmc,we-off-ns = <20>; | |
834 | gpmc,oe-on-ns = <3>; | |
835 | gpmc,oe-off-ns = <30>; | |
836 | gpmc,access-ns = <30>; | |
837 | gpmc,rd-cycle-ns = <40>; | |
838 | gpmc,wr-cycle-ns = <40>; | |
99ffa642 PG |
839 | gpmc,bus-turnaround-ns = <0>; |
840 | gpmc,cycle2cycle-delay-ns = <0>; | |
841 | gpmc,clk-activation-ns = <0>; | |
99ffa642 PG |
842 | gpmc,wr-access-ns = <40>; |
843 | gpmc,wr-data-mux-bus-ns = <0>; | |
844 | /* MTD partition table */ | |
845 | /* All SPL-* partitions are sized to minimal length | |
846 | * which can be independently programmable. For | |
847 | * NAND flash this is equal to size of erase-block */ | |
848 | #address-cells = <1>; | |
849 | #size-cells = <1>; | |
850 | partition@0 { | |
851 | label = "NAND.SPL"; | |
852 | reg = <0x00000000 0x00040000>; | |
853 | }; | |
854 | partition@1 { | |
855 | label = "NAND.SPL.backup1"; | |
856 | reg = <0x00040000 0x00040000>; | |
857 | }; | |
858 | partition@2 { | |
859 | label = "NAND.SPL.backup2"; | |
860 | reg = <0x00080000 0x00040000>; | |
861 | }; | |
862 | partition@3 { | |
863 | label = "NAND.SPL.backup3"; | |
864 | reg = <0x000c0000 0x00040000>; | |
865 | }; | |
866 | partition@4 { | |
867 | label = "NAND.u-boot-spl-os"; | |
868 | reg = <0x00100000 0x00080000>; | |
869 | }; | |
870 | partition@5 { | |
871 | label = "NAND.u-boot"; | |
872 | reg = <0x00180000 0x00100000>; | |
873 | }; | |
874 | partition@6 { | |
875 | label = "NAND.u-boot-env"; | |
876 | reg = <0x00280000 0x00040000>; | |
877 | }; | |
878 | partition@7 { | |
879 | label = "NAND.u-boot-env.backup1"; | |
880 | reg = <0x002c0000 0x00040000>; | |
881 | }; | |
882 | partition@8 { | |
883 | label = "NAND.kernel"; | |
884 | reg = <0x00300000 0x00700000>; | |
885 | }; | |
886 | partition@9 { | |
887 | label = "NAND.file-system"; | |
888 | reg = <0x00a00000 0x1f600000>; | |
889 | }; | |
890 | }; | |
891 | }; | |
0bacb529 SP |
892 | |
893 | &dss { | |
894 | status = "ok"; | |
895 | ||
896 | pinctrl-names = "default"; | |
897 | pinctrl-0 = <&dss_pins>; | |
898 | ||
899 | port { | |
900 | dpi_out: endpoint@0 { | |
901 | remote-endpoint = <&lcd_in>; | |
902 | data-lines = <24>; | |
903 | }; | |
904 | }; | |
905 | }; | |
4b1ce235 M |
906 | |
907 | &dcan0 { | |
f95b1064 | 908 | pinctrl-names = "default", "sleep"; |
4b1ce235 | 909 | pinctrl-0 = <&dcan0_default>; |
f95b1064 | 910 | pinctrl-1 = <&dcan0_sleep>; |
4b1ce235 M |
911 | status = "okay"; |
912 | }; | |
913 | ||
914 | &dcan1 { | |
f95b1064 | 915 | pinctrl-names = "default", "sleep"; |
4b1ce235 | 916 | pinctrl-0 = <&dcan1_default>; |
f95b1064 | 917 | pinctrl-1 = <&dcan1_sleep>; |
4b1ce235 M |
918 | status = "okay"; |
919 | }; | |
c788a7f4 BP |
920 | |
921 | &vpfe0 { | |
922 | status = "okay"; | |
923 | pinctrl-names = "default", "sleep"; | |
924 | pinctrl-0 = <&vpfe0_pins_default>; | |
925 | pinctrl-1 = <&vpfe0_pins_sleep>; | |
926 | ||
927 | port { | |
928 | vpfe0_ep: endpoint { | |
3aa59200 | 929 | remote-endpoint = <&ov2659_1>; |
c788a7f4 BP |
930 | ti,am437x-vpfe-interface = <0>; |
931 | bus-width = <8>; | |
932 | hsync-active = <0>; | |
933 | vsync-active = <0>; | |
934 | }; | |
935 | }; | |
936 | }; | |
937 | ||
938 | &vpfe1 { | |
939 | status = "okay"; | |
940 | pinctrl-names = "default", "sleep"; | |
941 | pinctrl-0 = <&vpfe1_pins_default>; | |
942 | pinctrl-1 = <&vpfe1_pins_sleep>; | |
943 | ||
944 | port { | |
945 | vpfe1_ep: endpoint { | |
3aa59200 | 946 | remote-endpoint = <&ov2659_0>; |
c788a7f4 BP |
947 | ti,am437x-vpfe-interface = <0>; |
948 | bus-width = <8>; | |
949 | hsync-active = <0>; | |
950 | vsync-active = <0>; | |
951 | }; | |
952 | }; | |
953 | }; | |
d3d92af1 PU |
954 | |
955 | &mcasp1 { | |
cf9a4850 | 956 | #sound-dai-cells = <0>; |
d3d92af1 PU |
957 | pinctrl-names = "default", "sleep"; |
958 | pinctrl-0 = <&mcasp1_pins>; | |
959 | pinctrl-1 = <&mcasp1_sleep_pins>; | |
960 | ||
961 | status = "okay"; | |
962 | ||
963 | op-mode = <0>; /* MCASP_IIS_MODE */ | |
964 | tdm-slots = <2>; | |
965 | /* 4 serializers */ | |
966 | serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ | |
967 | 0 0 1 2 | |
968 | >; | |
969 | tx-num-evt = <32>; | |
970 | rx-num-evt = <32>; | |
971 | }; | |
fff51e77 K |
972 | |
973 | &rtc { | |
974 | clocks = <&clk_32k_rtc>, <&clk_32768_ck>; | |
975 | clock-names = "ext-clk", "int-clk"; | |
976 | status = "okay"; | |
977 | }; |