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ARM: dts: enable PCIe support for Cygnus
[deliverable/linux.git] / arch / arm / boot / dts / am437x-gp-evm.dts
CommitLineData
11e2191c
LV		 1/*
2 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9/* AM437x GP EVM */
10
11/dts-v1/;
12
13#include "am4372.dtsi"
14#include <dt-bindings/pinctrl/am43xx.h>
c540b476 15#include <dt-bindings/pwm/pwm.h>
51724dbb 16#include <dt-bindings/gpio/gpio.h>
11e2191c
LV		 17
18/ {
19 model = "TI AM437x GP EVM";
20 compatible = "ti,am437x-gp-evm","ti,am4372","ti,am43";
c540b476 21
0bacb529
SP		 22 aliases {
23 display0 = &lcd0;
24 };
25
506be3fb
B		 26 vmmcsd_fixed: fixedregulator-sd {
27 compatible = "regulator-fixed";
28 regulator-name = "vmmcsd_fixed";
29 regulator-min-microvolt = <3300000>;
30 regulator-max-microvolt = <3300000>;
31 enable-active-high;
32 };
33
b2873bfa
DG		 34 vtt_fixed: fixedregulator-vtt {
35 compatible = "regulator-fixed";
36 regulator-name = "vtt_fixed";
37 regulator-min-microvolt = <1500000>;
38 regulator-max-microvolt = <1500000>;
39 regulator-always-on;
40 regulator-boot-on;
41 enable-active-high;
42 gpio = <&gpio5 7 GPIO_ACTIVE_HIGH>;
43 };
44
c540b476
SP		 45 backlight {
46 compatible = "pwm-backlight";
47 pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>;
48 brightness-levels = <0 51 53 56 62 75 101 152 255>;
49 default-brightness-level = <8>;
50 };
51724dbb
SP		 51
52 matrix_keypad: matrix_keypad@0 {
53 compatible = "gpio-matrix-keypad";
54 debounce-delay-ms = <5>;
55 col-scan-delay-us = <2>;
56
57 row-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH /* Bank3, pin21 */
58 &gpio4 3 GPIO_ACTIVE_HIGH /* Bank4, pin3 */
59 &gpio4 2 GPIO_ACTIVE_HIGH>; /* Bank4, pin2 */
60
61 col-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH /* Bank3, pin19 */
62 &gpio3 20 GPIO_ACTIVE_HIGH>; /* Bank3, pin20 */
63
64 linux,keymap = <0x00000201 /* P1 */
65 0x00010202 /* P2 */
66 0x01000067 /* UP */
67 0x0101006a /* RIGHT */
68 0x02000069 /* LEFT */
69 0x0201006c>; /* DOWN */
70 };
0bacb529
SP		 71
72 lcd0: display {
73 compatible = "osddisplays,osd057T0559-34ts", "panel-dpi";
74 label = "lcd";
75
76 pinctrl-names = "default";
77 pinctrl-0 = <&lcd_pins>;
78
79 /*
80 * SelLCDorHDMI, LOW to select HDMI. This is not really the
81 * panel's enable GPIO, but we don't have HDMI driver support nor
82 * support to switch between two displays, so using this gpio as
83 * panel's enable should be safe.
84 */
85 enable-gpios = <&gpio5 8 GPIO_ACTIVE_HIGH>;
86
87 panel-timing {
88 clock-frequency = <33000000>;
89 hactive = <800>;
90 vactive = <480>;
91 hfront-porch = <210>;
92 hback-porch = <16>;
93 hsync-len = <30>;
94 vback-porch = <10>;
95 vfront-porch = <22>;
96 vsync-len = <13>;
97 hsync-active = <0>;
98 vsync-active = <0>;
99 de-active = <1>;
100 pixelclk-active = <1>;
101 };
102
103 port {
104 lcd_in: endpoint {
105 remote-endpoint = <&dpi_out>;
106 };
107 };
108 };
11e2191c
LV		 109};
110
111&am43xx_pinmux {
112 i2c0_pins: i2c0_pins {
113 pinctrl-single,pins = <
114 0x188 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_sda.i2c0_sda */
115 0x18c (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */
116 >;
117 };
118
119 i2c1_pins: i2c1_pins {
120 pinctrl-single,pins = <
121 0x15c (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE2) /* spi0_cs0.i2c1_scl */
122 0x158 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE2) /* spi0_d1.i2c1_sda */
123 >;
124 };
c540b476 125
506be3fb
B		 126 mmc1_pins: pinmux_mmc1_pins {
127 pinctrl-single,pins = <
128 0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
129 >;
130 };
131
c540b476
SP		 132 ecap0_pins: backlight_pins {
133 pinctrl-single,pins = <
134 0x164 MUX_MODE0 /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */
135 >;
136 };
0ebc1e25
SN		 137
138 pixcir_ts_pins: pixcir_ts_pins {
139 pinctrl-single,pins = <
140 0x264 (PIN_INPUT_PULLUP | MUX_MODE7) /* spi2_d0.gpio3_22 */
141 >;
142 };
7b25babf
M		 143
144 cpsw_default: cpsw_default {
145 pinctrl-single,pins = <
146 /* Slave 1 */
147 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_txen */
148 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxdv.rgmii1_rxctl */
149 0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_txd3 */
150 0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_txd2 */
151 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_txd1 */
152 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_txd0 */
153 0x12c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rmii1_tclk */
154 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxclk.rmii1_rclk */
155 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rxd3 */
156 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rxd2 */
157 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rxd1 */
158 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rxd0 */
159 >;
160 };
161
162 cpsw_sleep: cpsw_sleep {
163 pinctrl-single,pins = <
164 /* Slave 1 reset value */
165 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
166 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
167 0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7)
168 0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7)
169 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
170 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
171 0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7)
172 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7)
173 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7)
174 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7)
175 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
176 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
177 >;
178 };
179
180 davinci_mdio_default: davinci_mdio_default {
181 pinctrl-single,pins = <
182 /* MDIO */
183 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
184 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
185 >;
186 };
187
188 davinci_mdio_sleep: davinci_mdio_sleep {
189 pinctrl-single,pins = <
190 /* MDIO reset value */
191 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
192 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
193 >;
194 };
99ffa642
PG		 195
196 nand_flash_x8: nand_flash_x8 {
197 pinctrl-single,pins = <
198 0x26c(PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* spi2_cs0.gpio/eMMCorNANDsel */
199 0x0 (PIN_INPUT | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */
200 0x4 (PIN_INPUT | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */
201 0x8 (PIN_INPUT | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */
202 0xc (PIN_INPUT | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */
203 0x10 (PIN_INPUT | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */
204 0x14 (PIN_INPUT | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */
205 0x18 (PIN_INPUT | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */
206 0x1c (PIN_INPUT | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */
207 0x70 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */
208 0x74 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpmc_wpn */
209 0x7c (PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */
210 0x90 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */
211 0x94 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */
212 0x98 (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */
213 0x9c (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */
214 >;
215 };
0bacb529
SP		 216
217 dss_pins: dss_pins {
218 pinctrl-single,pins = <
219 0x020 (PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 8 -> DSS DATA 23 */
220 0x024 (PIN_OUTPUT_PULLUP | MUX_MODE1)
221 0x028 (PIN_OUTPUT_PULLUP | MUX_MODE1)
222 0x02c (PIN_OUTPUT_PULLUP | MUX_MODE1)
223 0x030 (PIN_OUTPUT_PULLUP | MUX_MODE1)
224 0x034 (PIN_OUTPUT_PULLUP | MUX_MODE1)
225 0x038 (PIN_OUTPUT_PULLUP | MUX_MODE1)
226 0x03c (PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 15 -> DSS DATA 16 */
227 0x0a0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 0 */
228 0x0a4 (PIN_OUTPUT_PULLUP | MUX_MODE0)
229 0x0a8 (PIN_OUTPUT_PULLUP | MUX_MODE0)
230 0x0ac (PIN_OUTPUT_PULLUP | MUX_MODE0)
231 0x0b0 (PIN_OUTPUT_PULLUP | MUX_MODE0)
232 0x0b4 (PIN_OUTPUT_PULLUP | MUX_MODE0)
233 0x0b8 (PIN_OUTPUT_PULLUP | MUX_MODE0)
234 0x0bc (PIN_OUTPUT_PULLUP | MUX_MODE0)
235 0x0c0 (PIN_OUTPUT_PULLUP | MUX_MODE0)
236 0x0c4 (PIN_OUTPUT_PULLUP | MUX_MODE0)
237 0x0c8 (PIN_OUTPUT_PULLUP | MUX_MODE0)
238 0x0cc (PIN_OUTPUT_PULLUP | MUX_MODE0)
239 0x0d0 (PIN_OUTPUT_PULLUP | MUX_MODE0)
240 0x0d4 (PIN_OUTPUT_PULLUP | MUX_MODE0)
241 0x0d8 (PIN_OUTPUT_PULLUP | MUX_MODE0)
242 0x0dc (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 15 */
243 0x0e0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS VSYNC */
244 0x0e4 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS HSYNC */
245 0x0e8 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS PCLK */
246 0x0ec (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS AC BIAS EN */
247
248 >;
249 };
250
251 lcd_pins: lcd_pins {
252 pinctrl-single,pins = <
253 /* GPIO 5_8 to select LCD / HDMI */
254 0x238 (PIN_OUTPUT_PULLUP | MUX_MODE7)
255 >;
256 };
4b1ce235
M		 257
258 dcan0_default: dcan0_default_pins {
259 pinctrl-single,pins = <
260 0x178 (PIN_OUTPUT | MUX_MODE2) /* uart1_ctsn.d_can0_tx */
261 0x17c (PIN_INPUT_PULLUP | MUX_MODE2) /* uart1_rtsn.d_can0_rx */
262 >;
263 };
264
265 dcan1_default: dcan1_default_pins {
266 pinctrl-single,pins = <
267 0x180 (PIN_OUTPUT | MUX_MODE2) /* uart1_rxd.d_can1_tx */
268 0x184 (PIN_INPUT_PULLUP | MUX_MODE2) /* uart1_txd.d_can1_rx */
269 >;
270 };
c788a7f4
BP		 271
272 vpfe0_pins_default: vpfe0_pins_default {
273 pinctrl-single,pins = <
274 0x1B0 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_hd mode 0*/
275 0x1B4 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_vd mode 0*/
276 0x1C0 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_pclk mode 0*/
277 0x1C4 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data8 mode 0*/
278 0x1C8 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data9 mode 0*/
279 0x208 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data0 mode 0*/
280 0x20C (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data1 mode 0*/
281 0x210 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data2 mode 0*/
282 0x214 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data3 mode 0*/
283 0x218 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data4 mode 0*/
284 0x21C (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data5 mode 0*/
285 0x220 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data6 mode 0*/
286 0x224 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data7 mode 0*/
287 >;
288 };
289
290 vpfe0_pins_sleep: vpfe0_pins_sleep {
291 pinctrl-single,pins = <
292 0x1B0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_hd mode 0*/
293 0x1B4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_vd mode 0*/
294 0x1C0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_pclk mode 0*/
295 0x1C4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data8 mode 0*/
296 0x1C8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data9 mode 0*/
297 0x208 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data0 mode 0*/
298 0x20C (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data1 mode 0*/
299 0x210 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data2 mode 0*/
300 0x214 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data3 mode 0*/
301 0x218 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data4 mode 0*/
302 0x21C (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data5 mode 0*/
303 0x220 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data6 mode 0*/
304 0x224 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data7 mode 0*/
305 >;
306 };
307
308 vpfe1_pins_default: vpfe1_pins_default {
309 pinctrl-single,pins = <
310 0x1CC (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data9 mode 0*/
311 0x1D0 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data8 mode 0*/
312 0x1D4 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_hd mode 0*/
313 0x1D8 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_vd mode 0*/
314 0x1DC (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_pclk mode 0*/
315 0x1E8 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data0 mode 0*/
316 0x1EC (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data1 mode 0*/
317 0x1F0 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data2 mode 0*/
318 0x1F4 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data3 mode 0*/
319 0x1F8 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data4 mode 0*/
320 0x1FC (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data5 mode 0*/
321 0x200 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data6 mode 0*/
322 0x204 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data7 mode 0*/
323 >;
324 };
325
326 vpfe1_pins_sleep: vpfe1_pins_sleep {
327 pinctrl-single,pins = <
328 0x1CC (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data9 mode 0*/
329 0x1D0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data8 mode 0*/
330 0x1D4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_hd mode 0*/
331 0x1D8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_vd mode 0*/
332 0x1DC (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_pclk mode 0*/
333 0x1E8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data0 mode 0*/
334 0x1EC (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data1 mode 0*/
335 0x1F0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data2 mode 0*/
336 0x1F4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data3 mode 0*/
337 0x1F8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data4 mode 0*/
338 0x1FC (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data5 mode 0*/
339 0x200 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data6 mode 0*/
340 0x204 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data7 mode 0*/
341 >;
342 };
11e2191c
LV		 343};
344
345&i2c0 {
1fc98144
K		 346 status = "okay";
347 pinctrl-names = "default";
348 pinctrl-0 = <&i2c0_pins>;
93166413 349 clock-frequency = <100000>;
0e2da5e6
K		 350
351 tps65218: tps65218@24 {
352 reg = <0x24>;
353 compatible = "ti,tps65218";
354 interrupts = <GIC_SPI 7 IRQ_TYPE_NONE>; /* NMIn */
355 interrupt-parent = <&gic>;
356 interrupt-controller;
357 #interrupt-cells = <2>;
358
359 dcdc1: regulator-dcdc1 {
360 compatible = "ti,tps65218-dcdc1";
361 regulator-name = "vdd_core";
362 regulator-min-microvolt = <912000>;
363 regulator-max-microvolt = <1144000>;
364 regulator-boot-on;
365 regulator-always-on;
366 };
367
368 dcdc2: regulator-dcdc2 {
369 compatible = "ti,tps65218-dcdc2";
370 regulator-name = "vdd_mpu";
371 regulator-min-microvolt = <912000>;
372 regulator-max-microvolt = <1378000>;
373 regulator-boot-on;
374 regulator-always-on;
375 };
376
377 dcdc3: regulator-dcdc3 {
378 compatible = "ti,tps65218-dcdc3";
379 regulator-name = "vdcdc3";
3015ddbd
K		 380 regulator-min-microvolt = <1500000>;
381 regulator-max-microvolt = <1500000>;
0e2da5e6
K		 382 regulator-boot-on;
383 regulator-always-on;
384 };
385 dcdc5: regulator-dcdc5 {
386 compatible = "ti,tps65218-dcdc5";
387 regulator-name = "v1_0bat";
388 regulator-min-microvolt = <1000000>;
389 regulator-max-microvolt = <1000000>;
390 };
391
392 dcdc6: regulator-dcdc6 {
393 compatible = "ti,tps65218-dcdc6";
394 regulator-name = "v1_8bat";
395 regulator-min-microvolt = <1800000>;
396 regulator-max-microvolt = <1800000>;
397 };
398
399 ldo1: regulator-ldo1 {
400 compatible = "ti,tps65218-ldo1";
401 regulator-min-microvolt = <1800000>;
402 regulator-max-microvolt = <1800000>;
403 regulator-boot-on;
404 regulator-always-on;
405 };
406 };
11e2191c
LV		 407};
408
409&i2c1 {
1fc98144
K		 410 status = "okay";
411 pinctrl-names = "default";
412 pinctrl-0 = <&i2c1_pins>;
0ebc1e25
SN		 413 pixcir_ts@5c {
414 compatible = "pixcir,pixcir_tangoc";
415 pinctrl-names = "default";
416 pinctrl-0 = <&pixcir_ts_pins>;
417 reg = <0x5c>;
418 interrupt-parent = <&gpio3>;
419 interrupts = <22 0>;
420
421 attb-gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
422
f048615e
RQ		 423 touchscreen-size-x = <1024>;
424 touchscreen-size-y = <600>;
0ebc1e25 425 };
11e2191c 426};
c540b476
SP		 427
428&epwmss0 {
429 status = "okay";
430};
431
0f39f7b9
V		 432&tscadc {
433 status = "okay";
434
435 adc {
436 ti,adc-channels = <0 1 2 3 4 5 6 7>;
437 };
438};
439
c540b476
SP		 440&ecap0 {
441 status = "okay";
442 pinctrl-names = "default";
443 pinctrl-0 = <&ecap0_pins>;
444};
d3d46cca 445
506be3fb
B		 446&gpio0 {
447 status = "okay";
448};
449
d3d46cca
SP		 450&gpio3 {
451 status = "okay";
452};
453
454&gpio4 {
455 status = "okay";
456};
506be3fb 457
1ff3859e
DG		 458&gpio5 {
459 status = "okay";
460 ti,no-reset-on-init;
461};
462
506be3fb
B		 463&mmc1 {
464 status = "okay";
465 vmmc-supply = <&vmmcsd_fixed>;
466 bus-width = <4>;
467 pinctrl-names = "default";
468 pinctrl-0 = <&mmc1_pins>;
469 cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
470};
b5820d3a
GC		 471
472&usb2_phy1 {
473 status = "okay";
474};
475
476&usb1 {
477 dr_mode = "peripheral";
478 status = "okay";
479};
480
481&usb2_phy2 {
482 status = "okay";
483};
484
485&usb2 {
486 dr_mode = "host";
487 status = "okay";
488};
7b25babf
M		 489
490&mac {
491 slaves = <1>;
492 pinctrl-names = "default", "sleep";
493 pinctrl-0 = <&cpsw_default>;
494 pinctrl-1 = <&cpsw_sleep>;
495 status = "okay";
496};
497
498&davinci_mdio {
499 pinctrl-names = "default", "sleep";
500 pinctrl-0 = <&davinci_mdio_default>;
501 pinctrl-1 = <&davinci_mdio_sleep>;
502 status = "okay";
503};
504
505&cpsw_emac0 {
506 phy_id = <&davinci_mdio>, <0>;
507 phy-mode = "rgmii";
508};
99ffa642
PG		 509
510&elm {
511 status = "okay";
512};
513
514&gpmc {
515 status = "okay";
516 pinctrl-names = "default";
517 pinctrl-0 = <&nand_flash_x8>;
518 ranges = <0 0 0 0x01000000>; /* minimum GPMC partition = 16MB */
519 nand@0,0 {
520 reg = <0 0 4>; /* device IO registers */
6b869110 521 ti,nand-ecc-opt = "bch16";
99ffa642
PG		 522 ti,elm-id = <&elm>;
523 nand-bus-width = <8>;
524 gpmc,device-width = <1>;
525 gpmc,sync-clk-ps = <0>;
526 gpmc,cs-on-ns = <0>;
527 gpmc,cs-rd-off-ns = <40>;
528 gpmc,cs-wr-off-ns = <40>;
529 gpmc,adv-on-ns = <0>;
530 gpmc,adv-rd-off-ns = <25>;
531 gpmc,adv-wr-off-ns = <25>;
532 gpmc,we-on-ns = <0>;
533 gpmc,we-off-ns = <20>;
534 gpmc,oe-on-ns = <3>;
535 gpmc,oe-off-ns = <30>;
536 gpmc,access-ns = <30>;
537 gpmc,rd-cycle-ns = <40>;
538 gpmc,wr-cycle-ns = <40>;
539 gpmc,wait-pin = <0>;
99ffa642
PG		 540 gpmc,bus-turnaround-ns = <0>;
541 gpmc,cycle2cycle-delay-ns = <0>;
542 gpmc,clk-activation-ns = <0>;
543 gpmc,wait-monitoring-ns = <0>;
544 gpmc,wr-access-ns = <40>;
545 gpmc,wr-data-mux-bus-ns = <0>;
546 /* MTD partition table */
547 /* All SPL-* partitions are sized to minimal length
548 * which can be independently programmable. For
549 * NAND flash this is equal to size of erase-block */
550 #address-cells = <1>;
551 #size-cells = <1>;
552 partition@0 {
553 label = "NAND.SPL";
554 reg = <0x00000000 0x00040000>;
555 };
556 partition@1 {
557 label = "NAND.SPL.backup1";
558 reg = <0x00040000 0x00040000>;
559 };
560 partition@2 {
561 label = "NAND.SPL.backup2";
562 reg = <0x00080000 0x00040000>;
563 };
564 partition@3 {
565 label = "NAND.SPL.backup3";
566 reg = <0x000c0000 0x00040000>;
567 };
568 partition@4 {
569 label = "NAND.u-boot-spl-os";
570 reg = <0x00100000 0x00080000>;
571 };
572 partition@5 {
573 label = "NAND.u-boot";
574 reg = <0x00180000 0x00100000>;
575 };
576 partition@6 {
577 label = "NAND.u-boot-env";
578 reg = <0x00280000 0x00040000>;
579 };
580 partition@7 {
581 label = "NAND.u-boot-env.backup1";
582 reg = <0x002c0000 0x00040000>;
583 };
584 partition@8 {
585 label = "NAND.kernel";
586 reg = <0x00300000 0x00700000>;
587 };
588 partition@9 {
589 label = "NAND.file-system";
590 reg = <0x00a00000 0x1f600000>;
591 };
592 };
593};
0bacb529
SP		 594
595&dss {
596 status = "ok";
597
598 pinctrl-names = "default";
599 pinctrl-0 = <&dss_pins>;
600
601 port {
602 dpi_out: endpoint@0 {
603 remote-endpoint = <&lcd_in>;
604 data-lines = <24>;
605 };
606 };
607};
4b1ce235
M		 608
609&dcan0 {
610 pinctrl-names = "default";
611 pinctrl-0 = <&dcan0_default>;
612 status = "okay";
613};
614
615&dcan1 {
616 pinctrl-names = "default";
617 pinctrl-0 = <&dcan1_default>;
618 status = "okay";
619};
c788a7f4
BP		 620
621&vpfe0 {
622 status = "okay";
623 pinctrl-names = "default", "sleep";
624 pinctrl-0 = <&vpfe0_pins_default>;
625 pinctrl-1 = <&vpfe0_pins_sleep>;
626
627 port {
628 vpfe0_ep: endpoint {
629 /* remote-endpoint = <&sensor>; add once we have it */
630 ti,am437x-vpfe-interface = <0>;
631 bus-width = <8>;
632 hsync-active = <0>;
633 vsync-active = <0>;
634 };
635 };
636};
637
638&vpfe1 {
639 status = "okay";
640 pinctrl-names = "default", "sleep";
641 pinctrl-0 = <&vpfe1_pins_default>;
642 pinctrl-1 = <&vpfe1_pins_sleep>;
643
644 port {
645 vpfe1_ep: endpoint {
646 /* remote-endpoint = <&sensor>; add once we have it */
647 ti,am437x-vpfe-interface = <0>;
648 bus-width = <8>;
649 hsync-active = <0>;
650 vsync-active = <0>;
651 };
652 };
653};
Linux kernel - Deliverables
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