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ARM: dts: am437x-gp-evm: Add node for tlv320aic3106 audio codec
[deliverable/linux.git] / arch / arm / boot / dts / am437x-gp-evm.dts
CommitLineData
11e2191c
LV		 1/*
2 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9/* AM437x GP EVM */
10
11/dts-v1/;
12
13#include "am4372.dtsi"
14#include <dt-bindings/pinctrl/am43xx.h>
c540b476 15#include <dt-bindings/pwm/pwm.h>
51724dbb 16#include <dt-bindings/gpio/gpio.h>
11e2191c
LV		 17
18/ {
19 model = "TI AM437x GP EVM";
20 compatible = "ti,am437x-gp-evm","ti,am4372","ti,am43";
c540b476 21
0bacb529
SP		 22 aliases {
23 display0 = &lcd0;
b6bbf598 24 serial3 = &uart3;
0bacb529
SP		 25 };
26
390810a9 27 evm_v3_3d: fixedregulator-v3_3d {
506be3fb 28 compatible = "regulator-fixed";
390810a9 29 regulator-name = "evm_v3_3d";
506be3fb
B		 30 regulator-min-microvolt = <3300000>;
31 regulator-max-microvolt = <3300000>;
32 enable-active-high;
33 };
34
b2873bfa
DG		 35 vtt_fixed: fixedregulator-vtt {
36 compatible = "regulator-fixed";
37 regulator-name = "vtt_fixed";
38 regulator-min-microvolt = <1500000>;
39 regulator-max-microvolt = <1500000>;
40 regulator-always-on;
41 regulator-boot-on;
42 enable-active-high;
43 gpio = <&gpio5 7 GPIO_ACTIVE_HIGH>;
44 };
45
b6bbf598
ER		 46 vmmcwl_fixed: fixedregulator-mmcwl {
47 compatible = "regulator-fixed";
48 regulator-name = "vmmcwl_fixed";
49 regulator-min-microvolt = <1800000>;
50 regulator-max-microvolt = <1800000>;
51 gpio = <&gpio1 20 GPIO_ACTIVE_HIGH>;
52 enable-active-high;
53 };
54
c540b476
SP		 55 backlight {
56 compatible = "pwm-backlight";
57 pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>;
58 brightness-levels = <0 51 53 56 62 75 101 152 255>;
59 default-brightness-level = <8>;
60 };
51724dbb
SP		 61
62 matrix_keypad: matrix_keypad@0 {
63 compatible = "gpio-matrix-keypad";
64 debounce-delay-ms = <5>;
65 col-scan-delay-us = <2>;
66
67 row-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH /* Bank3, pin21 */
68 &gpio4 3 GPIO_ACTIVE_HIGH /* Bank4, pin3 */
69 &gpio4 2 GPIO_ACTIVE_HIGH>; /* Bank4, pin2 */
70
71 col-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH /* Bank3, pin19 */
72 &gpio3 20 GPIO_ACTIVE_HIGH>; /* Bank3, pin20 */
73
74 linux,keymap = <0x00000201 /* P1 */
75 0x00010202 /* P2 */
76 0x01000067 /* UP */
77 0x0101006a /* RIGHT */
78 0x02000069 /* LEFT */
79 0x0201006c>; /* DOWN */
80 };
0bacb529
SP		 81
82 lcd0: display {
83 compatible = "osddisplays,osd057T0559-34ts", "panel-dpi";
84 label = "lcd";
85
0bacb529
SP		 86 panel-timing {
87 clock-frequency = <33000000>;
88 hactive = <800>;
89 vactive = <480>;
90 hfront-porch = <210>;
91 hback-porch = <16>;
92 hsync-len = <30>;
93 vback-porch = <10>;
94 vfront-porch = <22>;
95 vsync-len = <13>;
96 hsync-active = <0>;
97 vsync-active = <0>;
98 de-active = <1>;
99 pixelclk-active = <1>;
100 };
101
102 port {
103 lcd_in: endpoint {
104 remote-endpoint = <&dpi_out>;
105 };
106 };
107 };
3aa59200
LP		 108
109 /* fixed 12MHz oscillator */
110 refclk: oscillator {
111 #clock-cells = <0>;
112 compatible = "fixed-clock";
113 clock-frequency = <12000000>;
114 };
115
11e2191c
LV		 116};
117
118&am43xx_pinmux {
b6bbf598
ER		 119 pinctrl-names = "default", "sleep";
120 pinctrl-0 = <&wlan_pins_default>;
121 pinctrl-1 = <&wlan_pins_sleep>;
122
11e2191c
LV		 123 i2c0_pins: i2c0_pins {
124 pinctrl-single,pins = <
125 0x188 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_sda.i2c0_sda */
126 0x18c (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */
127 >;
128 };
129
130 i2c1_pins: i2c1_pins {
131 pinctrl-single,pins = <
132 0x15c (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE2) /* spi0_cs0.i2c1_scl */
133 0x158 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE2) /* spi0_d1.i2c1_sda */
134 >;
135 };
c540b476 136
506be3fb
B		 137 mmc1_pins: pinmux_mmc1_pins {
138 pinctrl-single,pins = <
139 0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
140 >;
141 };
142
c540b476
SP		 143 ecap0_pins: backlight_pins {
144 pinctrl-single,pins = <
145 0x164 MUX_MODE0 /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */
146 >;
147 };
0ebc1e25
SN		 148
149 pixcir_ts_pins: pixcir_ts_pins {
150 pinctrl-single,pins = <
151 0x264 (PIN_INPUT_PULLUP | MUX_MODE7) /* spi2_d0.gpio3_22 */
152 >;
153 };
7b25babf
M		 154
155 cpsw_default: cpsw_default {
156 pinctrl-single,pins = <
157 /* Slave 1 */
158 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_txen */
159 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxdv.rgmii1_rxctl */
160 0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_txd3 */
161 0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_txd2 */
162 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_txd1 */
163 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_txd0 */
164 0x12c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rmii1_tclk */
165 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxclk.rmii1_rclk */
166 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rxd3 */
167 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rxd2 */
168 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rxd1 */
169 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rxd0 */
170 >;
171 };
172
173 cpsw_sleep: cpsw_sleep {
174 pinctrl-single,pins = <
175 /* Slave 1 reset value */
176 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
177 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
178 0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7)
179 0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7)
180 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
181 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
182 0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7)
183 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7)
184 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7)
185 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7)
186 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
187 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
188 >;
189 };
190
191 davinci_mdio_default: davinci_mdio_default {
192 pinctrl-single,pins = <
193 /* MDIO */
194 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
195 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
196 >;
197 };
198
199 davinci_mdio_sleep: davinci_mdio_sleep {
200 pinctrl-single,pins = <
201 /* MDIO reset value */
202 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
203 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
204 >;
205 };
99ffa642
PG		 206
207 nand_flash_x8: nand_flash_x8 {
208 pinctrl-single,pins = <
209 0x26c(PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* spi2_cs0.gpio/eMMCorNANDsel */
210 0x0 (PIN_INPUT | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */
211 0x4 (PIN_INPUT | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */
212 0x8 (PIN_INPUT | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */
213 0xc (PIN_INPUT | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */
214 0x10 (PIN_INPUT | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */
215 0x14 (PIN_INPUT | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */
216 0x18 (PIN_INPUT | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */
217 0x1c (PIN_INPUT | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */
218 0x70 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */
219 0x74 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpmc_wpn */
220 0x7c (PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */
221 0x90 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */
222 0x94 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */
223 0x98 (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */
224 0x9c (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */
225 >;
226 };
0bacb529
SP		 227
228 dss_pins: dss_pins {
229 pinctrl-single,pins = <
230 0x020 (PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 8 -> DSS DATA 23 */
231 0x024 (PIN_OUTPUT_PULLUP | MUX_MODE1)
232 0x028 (PIN_OUTPUT_PULLUP | MUX_MODE1)
233 0x02c (PIN_OUTPUT_PULLUP | MUX_MODE1)
234 0x030 (PIN_OUTPUT_PULLUP | MUX_MODE1)
235 0x034 (PIN_OUTPUT_PULLUP | MUX_MODE1)
236 0x038 (PIN_OUTPUT_PULLUP | MUX_MODE1)
237 0x03c (PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 15 -> DSS DATA 16 */
238 0x0a0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 0 */
239 0x0a4 (PIN_OUTPUT_PULLUP | MUX_MODE0)
240 0x0a8 (PIN_OUTPUT_PULLUP | MUX_MODE0)
241 0x0ac (PIN_OUTPUT_PULLUP | MUX_MODE0)
242 0x0b0 (PIN_OUTPUT_PULLUP | MUX_MODE0)
243 0x0b4 (PIN_OUTPUT_PULLUP | MUX_MODE0)
244 0x0b8 (PIN_OUTPUT_PULLUP | MUX_MODE0)
245 0x0bc (PIN_OUTPUT_PULLUP | MUX_MODE0)
246 0x0c0 (PIN_OUTPUT_PULLUP | MUX_MODE0)
247 0x0c4 (PIN_OUTPUT_PULLUP | MUX_MODE0)
248 0x0c8 (PIN_OUTPUT_PULLUP | MUX_MODE0)
249 0x0cc (PIN_OUTPUT_PULLUP | MUX_MODE0)
250 0x0d0 (PIN_OUTPUT_PULLUP | MUX_MODE0)
251 0x0d4 (PIN_OUTPUT_PULLUP | MUX_MODE0)
252 0x0d8 (PIN_OUTPUT_PULLUP | MUX_MODE0)
253 0x0dc (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 15 */
254 0x0e0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS VSYNC */
255 0x0e4 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS HSYNC */
256 0x0e8 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS PCLK */
257 0x0ec (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS AC BIAS EN */
258
259 >;
260 };
261
593113e7 262 display_mux_pins: display_mux_pins {
0bacb529
SP		 263 pinctrl-single,pins = <
264 /* GPIO 5_8 to select LCD / HDMI */
265 0x238 (PIN_OUTPUT_PULLUP | MUX_MODE7)
266 >;
267 };
4b1ce235
M		 268
269 dcan0_default: dcan0_default_pins {
270 pinctrl-single,pins = <
271 0x178 (PIN_OUTPUT | MUX_MODE2) /* uart1_ctsn.d_can0_tx */
272 0x17c (PIN_INPUT_PULLUP | MUX_MODE2) /* uart1_rtsn.d_can0_rx */
273 >;
274 };
275
276 dcan1_default: dcan1_default_pins {
277 pinctrl-single,pins = <
278 0x180 (PIN_OUTPUT | MUX_MODE2) /* uart1_rxd.d_can1_tx */
279 0x184 (PIN_INPUT_PULLUP | MUX_MODE2) /* uart1_txd.d_can1_rx */
280 >;
281 };
c788a7f4
BP		 282
283 vpfe0_pins_default: vpfe0_pins_default {
284 pinctrl-single,pins = <
285 0x1B0 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_hd mode 0*/
286 0x1B4 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_vd mode 0*/
287 0x1C0 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_pclk mode 0*/
288 0x1C4 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data8 mode 0*/
289 0x1C8 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data9 mode 0*/
290 0x208 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data0 mode 0*/
291 0x20C (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data1 mode 0*/
292 0x210 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data2 mode 0*/
293 0x214 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data3 mode 0*/
294 0x218 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data4 mode 0*/
295 0x21C (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data5 mode 0*/
296 0x220 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data6 mode 0*/
297 0x224 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data7 mode 0*/
298 >;
299 };
300
301 vpfe0_pins_sleep: vpfe0_pins_sleep {
302 pinctrl-single,pins = <
303 0x1B0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_hd mode 0*/
304 0x1B4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_vd mode 0*/
305 0x1C0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_pclk mode 0*/
306 0x1C4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data8 mode 0*/
307 0x1C8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data9 mode 0*/
308 0x208 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data0 mode 0*/
309 0x20C (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data1 mode 0*/
310 0x210 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data2 mode 0*/
311 0x214 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data3 mode 0*/
312 0x218 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data4 mode 0*/
313 0x21C (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data5 mode 0*/
314 0x220 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data6 mode 0*/
315 0x224 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data7 mode 0*/
316 >;
317 };
318
319 vpfe1_pins_default: vpfe1_pins_default {
320 pinctrl-single,pins = <
321 0x1CC (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data9 mode 0*/
322 0x1D0 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data8 mode 0*/
323 0x1D4 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_hd mode 0*/
324 0x1D8 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_vd mode 0*/
325 0x1DC (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_pclk mode 0*/
326 0x1E8 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data0 mode 0*/
327 0x1EC (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data1 mode 0*/
328 0x1F0 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data2 mode 0*/
329 0x1F4 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data3 mode 0*/
330 0x1F8 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data4 mode 0*/
331 0x1FC (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data5 mode 0*/
332 0x200 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data6 mode 0*/
333 0x204 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data7 mode 0*/
334 >;
335 };
336
337 vpfe1_pins_sleep: vpfe1_pins_sleep {
338 pinctrl-single,pins = <
339 0x1CC (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data9 mode 0*/
340 0x1D0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data8 mode 0*/
341 0x1D4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_hd mode 0*/
342 0x1D8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_vd mode 0*/
343 0x1DC (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_pclk mode 0*/
344 0x1E8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data0 mode 0*/
345 0x1EC (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data1 mode 0*/
346 0x1F0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data2 mode 0*/
347 0x1F4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data3 mode 0*/
348 0x1F8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data4 mode 0*/
349 0x1FC (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data5 mode 0*/
350 0x200 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data6 mode 0*/
351 0x204 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data7 mode 0*/
352 >;
353 };
b6bbf598
ER		 354
355 mmc3_pins_default: pinmux_mmc3_pins_default {
356 pinctrl-single,pins = <
357 0x8c (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_clk.mmc2_clk */
358 0x88 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_csn3.mmc2_cmd */
359 0x44 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a1.mmc2_dat0 */
360 0x48 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a2.mmc2_dat1 */
361 0x4c (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a3.mmc2_dat2 */
362 0x78 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_be1n.mmc2_dat3 */
363 >;
364 };
365
366 mmc3_pins_sleep: pinmux_mmc3_pins_sleep {
367 pinctrl-single,pins = <
368 0x8c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_clk.mmc2_clk */
369 0x88 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_csn3.mmc2_cmd */
370 0x44 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a1.mmc2_dat0 */
371 0x48 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a2.mmc2_dat1 */
372 0x4c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a3.mmc2_dat2 */
373 0x78 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_be1n.mmc2_dat3 */
374 >;
375 };
376
377 wlan_pins_default: pinmux_wlan_pins_default {
378 pinctrl-single,pins = <
379 0x50 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a4.gpio1_20 WL_EN */
380 0x5c (PIN_INPUT | WAKEUP_ENABLE | MUX_MODE7) /* gpmc_a7.gpio1_23 WL_IRQ*/
381 0x40 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a0.gpio1_16 BT_EN*/
382 >;
383 };
384
385 wlan_pins_sleep: pinmux_wlan_pins_sleep {
386 pinctrl-single,pins = <
387 0x50 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a4.gpio1_20 WL_EN */
388 0x5c (PIN_INPUT | WAKEUP_ENABLE | MUX_MODE7) /* gpmc_a7.gpio1_23 WL_IRQ*/
389 0x40 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a0.gpio1_16 BT_EN*/
390 >;
391 };
392
393 uart3_pins: uart3_pins {
394 pinctrl-single,pins = <
395 0x228 (PIN_INPUT | MUX_MODE0) /* uart3_rxd.uart3_rxd */
396 0x22c (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart3_txd.uart3_txd */
397 0x230 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart3_ctsn.uart3_ctsn */
398 0x234 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart3_rtsn.uart3_rtsn */
399 >;
400 };
11e2191c
LV		 401};
402
403&i2c0 {
1fc98144
K		 404 status = "okay";
405 pinctrl-names = "default";
406 pinctrl-0 = <&i2c0_pins>;
93166413 407 clock-frequency = <100000>;
0e2da5e6
K		 408
409 tps65218: tps65218@24 {
410 reg = <0x24>;
411 compatible = "ti,tps65218";
412 interrupts = <GIC_SPI 7 IRQ_TYPE_NONE>; /* NMIn */
0e2da5e6
K		 413 interrupt-controller;
414 #interrupt-cells = <2>;
415
416 dcdc1: regulator-dcdc1 {
417 compatible = "ti,tps65218-dcdc1";
418 regulator-name = "vdd_core";
419 regulator-min-microvolt = <912000>;
420 regulator-max-microvolt = <1144000>;
421 regulator-boot-on;
422 regulator-always-on;
423 };
424
425 dcdc2: regulator-dcdc2 {
426 compatible = "ti,tps65218-dcdc2";
427 regulator-name = "vdd_mpu";
428 regulator-min-microvolt = <912000>;
429 regulator-max-microvolt = <1378000>;
430 regulator-boot-on;
431 regulator-always-on;
432 };
433
434 dcdc3: regulator-dcdc3 {
435 compatible = "ti,tps65218-dcdc3";
436 regulator-name = "vdcdc3";
3015ddbd
K		 437 regulator-min-microvolt = <1500000>;
438 regulator-max-microvolt = <1500000>;
0e2da5e6
K		 439 regulator-boot-on;
440 regulator-always-on;
441 };
442 dcdc5: regulator-dcdc5 {
443 compatible = "ti,tps65218-dcdc5";
444 regulator-name = "v1_0bat";
445 regulator-min-microvolt = <1000000>;
446 regulator-max-microvolt = <1000000>;
447 };
448
449 dcdc6: regulator-dcdc6 {
450 compatible = "ti,tps65218-dcdc6";
451 regulator-name = "v1_8bat";
452 regulator-min-microvolt = <1800000>;
453 regulator-max-microvolt = <1800000>;
454 };
455
456 ldo1: regulator-ldo1 {
457 compatible = "ti,tps65218-ldo1";
458 regulator-min-microvolt = <1800000>;
459 regulator-max-microvolt = <1800000>;
460 regulator-boot-on;
461 regulator-always-on;
462 };
463 };
3aa59200
LP		 464
465 ov2659@30 {
466 compatible = "ovti,ov2659";
467 reg = <0x30>;
468
469 clocks = <&refclk 0>;
470 clock-names = "xvclk";
471
472 port {
473 ov2659_0: endpoint {
474 remote-endpoint = <&vpfe1_ep>;
475 link-frequencies = /bits/ 64 <70000000>;
476 };
477 };
478 };
11e2191c
LV		 479};
480
481&i2c1 {
1fc98144
K		 482 status = "okay";
483 pinctrl-names = "default";
484 pinctrl-0 = <&i2c1_pins>;
0ebc1e25
SN		 485 pixcir_ts@5c {
486 compatible = "pixcir,pixcir_tangoc";
487 pinctrl-names = "default";
488 pinctrl-0 = <&pixcir_ts_pins>;
489 reg = <0x5c>;
490 interrupt-parent = <&gpio3>;
491 interrupts = <22 0>;
492
493 attb-gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
494
f048615e
RQ		 495 touchscreen-size-x = <1024>;
496 touchscreen-size-y = <600>;
0ebc1e25 497 };
3aa59200
LP		 498
499 ov2659@30 {
500 compatible = "ovti,ov2659";
501 reg = <0x30>;
502
503 clocks = <&refclk 0>;
504 clock-names = "xvclk";
505
506 port {
507 ov2659_1: endpoint {
508 remote-endpoint = <&vpfe0_ep>;
509 link-frequencies = /bits/ 64 <70000000>;
510 };
511 };
512 };
6076b159
PU		 513
514 tlv320aic3106: tlv320aic3106@1b {
515 compatible = "ti,tlv320aic3106";
516 reg = <0x1b>;
517 status = "okay";
518
519 /* Regulators */
520 IOVDD-supply = <&evm_v3_3d>; /* V3_3D -> <tps63031> EN: V1_8D -> VBAT */
521 AVDD-supply = <&evm_v3_3d>; /* v3_3AUD -> V3_3D -> ... */
522 DRVDD-supply = <&evm_v3_3d>; /* v3_3AUD -> V3_3D -> ... */
523 DVDD-supply = <&ldo1>; /* V1_8D -> LDO1 */
524 };
11e2191c 525};
c540b476
SP		 526
527&epwmss0 {
528 status = "okay";
529};
530
0f39f7b9
V		 531&tscadc {
532 status = "okay";
533
534 adc {
535 ti,adc-channels = <0 1 2 3 4 5 6 7>;
536 };
537};
538
c540b476
SP		 539&ecap0 {
540 status = "okay";
541 pinctrl-names = "default";
542 pinctrl-0 = <&ecap0_pins>;
543};
d3d46cca 544
506be3fb
B		 545&gpio0 {
546 status = "okay";
547};
548
b6bbf598
ER		 549&gpio1 {
550 status = "okay";
551};
552
d3d46cca
SP		 553&gpio3 {
554 status = "okay";
555};
556
557&gpio4 {
558 status = "okay";
559};
506be3fb 560
1ff3859e 561&gpio5 {
593113e7
PU		 562 pinctrl-names = "default";
563 pinctrl-0 = <&display_mux_pins>;
1ff3859e
DG		 564 status = "okay";
565 ti,no-reset-on-init;
593113e7
PU		 566
567 p8 {
568 /*
569 * SelLCDorHDMI selects between display and audio paths:
570 * Low: HDMI display with audio via HDMI
571 * High: LCD display with analog audio via aic3111 codec
572 */
573 gpio-hog;
574 gpios = <8 GPIO_ACTIVE_HIGH>;
575 output-high;
576 line-name = "SelLCDorHDMI";
577 };
1ff3859e
DG		 578};
579
506be3fb
B		 580&mmc1 {
581 status = "okay";
390810a9 582 vmmc-supply = <&evm_v3_3d>;
506be3fb
B		 583 bus-width = <4>;
584 pinctrl-names = "default";
585 pinctrl-0 = <&mmc1_pins>;
586 cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
587};
b5820d3a 588
b6bbf598
ER		 589&mmc3 {
590 status = "okay";
591 /* these are on the crossbar and are outlined in the
592 xbar-event-map element */
593 dmas = <&edma 30
594 &edma 31>;
595 dma-names = "tx", "rx";
596 vmmc-supply = <&vmmcwl_fixed>;
597 bus-width = <4>;
598 pinctrl-names = "default", "sleep";
599 pinctrl-0 = <&mmc3_pins_default>;
600 pinctrl-1 = <&mmc3_pins_sleep>;
601 cap-power-off-card;
602 keep-power-in-suspend;
603 ti,non-removable;
604
605 #address-cells = <1>;
606 #size-cells = <0>;
607 wlcore: wlcore@0 {
608 compatible = "ti,wl1835";
609 reg = <2>;
610 interrupt-parent = <&gpio1>;
611 interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;
612 };
613};
614
615&edma {
616 ti,edma-xbar-event-map = /bits/ 16 <1 30
617 2 31>;
618};
619
620&uart3 {
621 status = "okay";
622 pinctrl-names = "default";
623 pinctrl-0 = <&uart3_pins>;
624};
625
b5820d3a
GC		 626&usb2_phy1 {
627 status = "okay";
628};
629
630&usb1 {
631 dr_mode = "peripheral";
632 status = "okay";
633};
634
635&usb2_phy2 {
636 status = "okay";
637};
638
639&usb2 {
640 dr_mode = "host";
641 status = "okay";
642};
7b25babf
M		 643
644&mac {
645 slaves = <1>;
646 pinctrl-names = "default", "sleep";
647 pinctrl-0 = <&cpsw_default>;
648 pinctrl-1 = <&cpsw_sleep>;
649 status = "okay";
650};
651
652&davinci_mdio {
653 pinctrl-names = "default", "sleep";
654 pinctrl-0 = <&davinci_mdio_default>;
655 pinctrl-1 = <&davinci_mdio_sleep>;
656 status = "okay";
657};
658
659&cpsw_emac0 {
660 phy_id = <&davinci_mdio>, <0>;
661 phy-mode = "rgmii";
662};
99ffa642
PG		 663
664&elm {
665 status = "okay";
666};
667
668&gpmc {
669 status = "okay";
670 pinctrl-names = "default";
671 pinctrl-0 = <&nand_flash_x8>;
672 ranges = <0 0 0 0x01000000>; /* minimum GPMC partition = 16MB */
673 nand@0,0 {
674 reg = <0 0 4>; /* device IO registers */
6b869110 675 ti,nand-ecc-opt = "bch16";
99ffa642
PG		 676 ti,elm-id = <&elm>;
677 nand-bus-width = <8>;
678 gpmc,device-width = <1>;
679 gpmc,sync-clk-ps = <0>;
680 gpmc,cs-on-ns = <0>;
681 gpmc,cs-rd-off-ns = <40>;
682 gpmc,cs-wr-off-ns = <40>;
683 gpmc,adv-on-ns = <0>;
684 gpmc,adv-rd-off-ns = <25>;
685 gpmc,adv-wr-off-ns = <25>;
686 gpmc,we-on-ns = <0>;
687 gpmc,we-off-ns = <20>;
688 gpmc,oe-on-ns = <3>;
689 gpmc,oe-off-ns = <30>;
690 gpmc,access-ns = <30>;
691 gpmc,rd-cycle-ns = <40>;
692 gpmc,wr-cycle-ns = <40>;
693 gpmc,wait-pin = <0>;
99ffa642
PG		 694 gpmc,bus-turnaround-ns = <0>;
695 gpmc,cycle2cycle-delay-ns = <0>;
696 gpmc,clk-activation-ns = <0>;
697 gpmc,wait-monitoring-ns = <0>;
698 gpmc,wr-access-ns = <40>;
699 gpmc,wr-data-mux-bus-ns = <0>;
700 /* MTD partition table */
701 /* All SPL-* partitions are sized to minimal length
702 * which can be independently programmable. For
703 * NAND flash this is equal to size of erase-block */
704 #address-cells = <1>;
705 #size-cells = <1>;
706 partition@0 {
707 label = "NAND.SPL";
708 reg = <0x00000000 0x00040000>;
709 };
710 partition@1 {
711 label = "NAND.SPL.backup1";
712 reg = <0x00040000 0x00040000>;
713 };
714 partition@2 {
715 label = "NAND.SPL.backup2";
716 reg = <0x00080000 0x00040000>;
717 };
718 partition@3 {
719 label = "NAND.SPL.backup3";
720 reg = <0x000c0000 0x00040000>;
721 };
722 partition@4 {
723 label = "NAND.u-boot-spl-os";
724 reg = <0x00100000 0x00080000>;
725 };
726 partition@5 {
727 label = "NAND.u-boot";
728 reg = <0x00180000 0x00100000>;
729 };
730 partition@6 {
731 label = "NAND.u-boot-env";
732 reg = <0x00280000 0x00040000>;
733 };
734 partition@7 {
735 label = "NAND.u-boot-env.backup1";
736 reg = <0x002c0000 0x00040000>;
737 };
738 partition@8 {
739 label = "NAND.kernel";
740 reg = <0x00300000 0x00700000>;
741 };
742 partition@9 {
743 label = "NAND.file-system";
744 reg = <0x00a00000 0x1f600000>;
745 };
746 };
747};
0bacb529
SP		 748
749&dss {
750 status = "ok";
751
752 pinctrl-names = "default";
753 pinctrl-0 = <&dss_pins>;
754
755 port {
756 dpi_out: endpoint@0 {
757 remote-endpoint = <&lcd_in>;
758 data-lines = <24>;
759 };
760 };
761};
4b1ce235
M		 762
763&dcan0 {
764 pinctrl-names = "default";
765 pinctrl-0 = <&dcan0_default>;
766 status = "okay";
767};
768
769&dcan1 {
770 pinctrl-names = "default";
771 pinctrl-0 = <&dcan1_default>;
772 status = "okay";
773};
c788a7f4
BP		 774
775&vpfe0 {
776 status = "okay";
777 pinctrl-names = "default", "sleep";
778 pinctrl-0 = <&vpfe0_pins_default>;
779 pinctrl-1 = <&vpfe0_pins_sleep>;
780
781 port {
782 vpfe0_ep: endpoint {
3aa59200 783 remote-endpoint = <&ov2659_1>;
c788a7f4
BP		 784 ti,am437x-vpfe-interface = <0>;
785 bus-width = <8>;
786 hsync-active = <0>;
787 vsync-active = <0>;
788 };
789 };
790};
791
792&vpfe1 {
793 status = "okay";
794 pinctrl-names = "default", "sleep";
795 pinctrl-0 = <&vpfe1_pins_default>;
796 pinctrl-1 = <&vpfe1_pins_sleep>;
797
798 port {
799 vpfe1_ep: endpoint {
3aa59200 800 remote-endpoint = <&ov2659_0>;
c788a7f4
BP		 801 ti,am437x-vpfe-interface = <0>;
802 bus-width = <8>;
803 hsync-active = <0>;
804 vsync-active = <0>;
805 };
806 };
807};
Linux kernel - Deliverables
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