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ARM: dts: add DTS for Baltos IR5221
[deliverable/linux.git] / arch / arm / boot / dts / am437x-gp-evm.dts
CommitLineData
11e2191c
LV		 1/*
2 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9/* AM437x GP EVM */
10
11/dts-v1/;
12
13#include "am4372.dtsi"
14#include <dt-bindings/pinctrl/am43xx.h>
c540b476 15#include <dt-bindings/pwm/pwm.h>
51724dbb 16#include <dt-bindings/gpio/gpio.h>
11e2191c
LV		 17
18/ {
19 model = "TI AM437x GP EVM";
20 compatible = "ti,am437x-gp-evm","ti,am4372","ti,am43";
c540b476 21
0bacb529
SP		 22 aliases {
23 display0 = &lcd0;
b6bbf598 24 serial3 = &uart3;
0bacb529
SP		 25 };
26
506be3fb
B		 27 vmmcsd_fixed: fixedregulator-sd {
28 compatible = "regulator-fixed";
29 regulator-name = "vmmcsd_fixed";
30 regulator-min-microvolt = <3300000>;
31 regulator-max-microvolt = <3300000>;
32 enable-active-high;
33 };
34
b2873bfa
DG		 35 vtt_fixed: fixedregulator-vtt {
36 compatible = "regulator-fixed";
37 regulator-name = "vtt_fixed";
38 regulator-min-microvolt = <1500000>;
39 regulator-max-microvolt = <1500000>;
40 regulator-always-on;
41 regulator-boot-on;
42 enable-active-high;
43 gpio = <&gpio5 7 GPIO_ACTIVE_HIGH>;
44 };
45
b6bbf598
ER		 46 vmmcwl_fixed: fixedregulator-mmcwl {
47 compatible = "regulator-fixed";
48 regulator-name = "vmmcwl_fixed";
49 regulator-min-microvolt = <1800000>;
50 regulator-max-microvolt = <1800000>;
51 gpio = <&gpio1 20 GPIO_ACTIVE_HIGH>;
52 enable-active-high;
53 };
54
c540b476
SP		 55 backlight {
56 compatible = "pwm-backlight";
57 pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>;
58 brightness-levels = <0 51 53 56 62 75 101 152 255>;
59 default-brightness-level = <8>;
60 };
51724dbb
SP		 61
62 matrix_keypad: matrix_keypad@0 {
63 compatible = "gpio-matrix-keypad";
64 debounce-delay-ms = <5>;
65 col-scan-delay-us = <2>;
66
67 row-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH /* Bank3, pin21 */
68 &gpio4 3 GPIO_ACTIVE_HIGH /* Bank4, pin3 */
69 &gpio4 2 GPIO_ACTIVE_HIGH>; /* Bank4, pin2 */
70
71 col-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH /* Bank3, pin19 */
72 &gpio3 20 GPIO_ACTIVE_HIGH>; /* Bank3, pin20 */
73
74 linux,keymap = <0x00000201 /* P1 */
75 0x00010202 /* P2 */
76 0x01000067 /* UP */
77 0x0101006a /* RIGHT */
78 0x02000069 /* LEFT */
79 0x0201006c>; /* DOWN */
80 };
0bacb529
SP		 81
82 lcd0: display {
83 compatible = "osddisplays,osd057T0559-34ts", "panel-dpi";
84 label = "lcd";
85
86 pinctrl-names = "default";
87 pinctrl-0 = <&lcd_pins>;
88
89 /*
90 * SelLCDorHDMI, LOW to select HDMI. This is not really the
91 * panel's enable GPIO, but we don't have HDMI driver support nor
92 * support to switch between two displays, so using this gpio as
93 * panel's enable should be safe.
94 */
95 enable-gpios = <&gpio5 8 GPIO_ACTIVE_HIGH>;
96
97 panel-timing {
98 clock-frequency = <33000000>;
99 hactive = <800>;
100 vactive = <480>;
101 hfront-porch = <210>;
102 hback-porch = <16>;
103 hsync-len = <30>;
104 vback-porch = <10>;
105 vfront-porch = <22>;
106 vsync-len = <13>;
107 hsync-active = <0>;
108 vsync-active = <0>;
109 de-active = <1>;
110 pixelclk-active = <1>;
111 };
112
113 port {
114 lcd_in: endpoint {
115 remote-endpoint = <&dpi_out>;
116 };
117 };
118 };
11e2191c
LV		 119};
120
121&am43xx_pinmux {
b6bbf598
ER		 122 pinctrl-names = "default", "sleep";
123 pinctrl-0 = <&wlan_pins_default>;
124 pinctrl-1 = <&wlan_pins_sleep>;
125
11e2191c
LV		 126 i2c0_pins: i2c0_pins {
127 pinctrl-single,pins = <
128 0x188 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_sda.i2c0_sda */
129 0x18c (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */
130 >;
131 };
132
133 i2c1_pins: i2c1_pins {
134 pinctrl-single,pins = <
135 0x15c (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE2) /* spi0_cs0.i2c1_scl */
136 0x158 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE2) /* spi0_d1.i2c1_sda */
137 >;
138 };
c540b476 139
506be3fb
B		 140 mmc1_pins: pinmux_mmc1_pins {
141 pinctrl-single,pins = <
142 0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
143 >;
144 };
145
c540b476
SP		 146 ecap0_pins: backlight_pins {
147 pinctrl-single,pins = <
148 0x164 MUX_MODE0 /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */
149 >;
150 };
0ebc1e25
SN		 151
152 pixcir_ts_pins: pixcir_ts_pins {
153 pinctrl-single,pins = <
154 0x264 (PIN_INPUT_PULLUP | MUX_MODE7) /* spi2_d0.gpio3_22 */
155 >;
156 };
7b25babf
M		 157
158 cpsw_default: cpsw_default {
159 pinctrl-single,pins = <
160 /* Slave 1 */
161 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_txen */
162 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxdv.rgmii1_rxctl */
163 0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_txd3 */
164 0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_txd2 */
165 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_txd1 */
166 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_txd0 */
167 0x12c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rmii1_tclk */
168 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxclk.rmii1_rclk */
169 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rxd3 */
170 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rxd2 */
171 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rxd1 */
172 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rxd0 */
173 >;
174 };
175
176 cpsw_sleep: cpsw_sleep {
177 pinctrl-single,pins = <
178 /* Slave 1 reset value */
179 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
180 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
181 0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7)
182 0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7)
183 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
184 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
185 0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7)
186 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7)
187 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7)
188 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7)
189 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
190 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
191 >;
192 };
193
194 davinci_mdio_default: davinci_mdio_default {
195 pinctrl-single,pins = <
196 /* MDIO */
197 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
198 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
199 >;
200 };
201
202 davinci_mdio_sleep: davinci_mdio_sleep {
203 pinctrl-single,pins = <
204 /* MDIO reset value */
205 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
206 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
207 >;
208 };
99ffa642
PG		 209
210 nand_flash_x8: nand_flash_x8 {
211 pinctrl-single,pins = <
212 0x26c(PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* spi2_cs0.gpio/eMMCorNANDsel */
213 0x0 (PIN_INPUT | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */
214 0x4 (PIN_INPUT | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */
215 0x8 (PIN_INPUT | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */
216 0xc (PIN_INPUT | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */
217 0x10 (PIN_INPUT | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */
218 0x14 (PIN_INPUT | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */
219 0x18 (PIN_INPUT | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */
220 0x1c (PIN_INPUT | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */
221 0x70 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */
222 0x74 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpmc_wpn */
223 0x7c (PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */
224 0x90 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */
225 0x94 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */
226 0x98 (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */
227 0x9c (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */
228 >;
229 };
0bacb529
SP		 230
231 dss_pins: dss_pins {
232 pinctrl-single,pins = <
233 0x020 (PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 8 -> DSS DATA 23 */
234 0x024 (PIN_OUTPUT_PULLUP | MUX_MODE1)
235 0x028 (PIN_OUTPUT_PULLUP | MUX_MODE1)
236 0x02c (PIN_OUTPUT_PULLUP | MUX_MODE1)
237 0x030 (PIN_OUTPUT_PULLUP | MUX_MODE1)
238 0x034 (PIN_OUTPUT_PULLUP | MUX_MODE1)
239 0x038 (PIN_OUTPUT_PULLUP | MUX_MODE1)
240 0x03c (PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 15 -> DSS DATA 16 */
241 0x0a0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 0 */
242 0x0a4 (PIN_OUTPUT_PULLUP | MUX_MODE0)
243 0x0a8 (PIN_OUTPUT_PULLUP | MUX_MODE0)
244 0x0ac (PIN_OUTPUT_PULLUP | MUX_MODE0)
245 0x0b0 (PIN_OUTPUT_PULLUP | MUX_MODE0)
246 0x0b4 (PIN_OUTPUT_PULLUP | MUX_MODE0)
247 0x0b8 (PIN_OUTPUT_PULLUP | MUX_MODE0)
248 0x0bc (PIN_OUTPUT_PULLUP | MUX_MODE0)
249 0x0c0 (PIN_OUTPUT_PULLUP | MUX_MODE0)
250 0x0c4 (PIN_OUTPUT_PULLUP | MUX_MODE0)
251 0x0c8 (PIN_OUTPUT_PULLUP | MUX_MODE0)
252 0x0cc (PIN_OUTPUT_PULLUP | MUX_MODE0)
253 0x0d0 (PIN_OUTPUT_PULLUP | MUX_MODE0)
254 0x0d4 (PIN_OUTPUT_PULLUP | MUX_MODE0)
255 0x0d8 (PIN_OUTPUT_PULLUP | MUX_MODE0)
256 0x0dc (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 15 */
257 0x0e0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS VSYNC */
258 0x0e4 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS HSYNC */
259 0x0e8 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS PCLK */
260 0x0ec (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS AC BIAS EN */
261
262 >;
263 };
264
265 lcd_pins: lcd_pins {
266 pinctrl-single,pins = <
267 /* GPIO 5_8 to select LCD / HDMI */
268 0x238 (PIN_OUTPUT_PULLUP | MUX_MODE7)
269 >;
270 };
4b1ce235
M		 271
272 dcan0_default: dcan0_default_pins {
273 pinctrl-single,pins = <
274 0x178 (PIN_OUTPUT | MUX_MODE2) /* uart1_ctsn.d_can0_tx */
275 0x17c (PIN_INPUT_PULLUP | MUX_MODE2) /* uart1_rtsn.d_can0_rx */
276 >;
277 };
278
279 dcan1_default: dcan1_default_pins {
280 pinctrl-single,pins = <
281 0x180 (PIN_OUTPUT | MUX_MODE2) /* uart1_rxd.d_can1_tx */
282 0x184 (PIN_INPUT_PULLUP | MUX_MODE2) /* uart1_txd.d_can1_rx */
283 >;
284 };
c788a7f4
BP		 285
286 vpfe0_pins_default: vpfe0_pins_default {
287 pinctrl-single,pins = <
288 0x1B0 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_hd mode 0*/
289 0x1B4 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_vd mode 0*/
290 0x1C0 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_pclk mode 0*/
291 0x1C4 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data8 mode 0*/
292 0x1C8 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data9 mode 0*/
293 0x208 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data0 mode 0*/
294 0x20C (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data1 mode 0*/
295 0x210 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data2 mode 0*/
296 0x214 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data3 mode 0*/
297 0x218 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data4 mode 0*/
298 0x21C (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data5 mode 0*/
299 0x220 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data6 mode 0*/
300 0x224 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data7 mode 0*/
301 >;
302 };
303
304 vpfe0_pins_sleep: vpfe0_pins_sleep {
305 pinctrl-single,pins = <
306 0x1B0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_hd mode 0*/
307 0x1B4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_vd mode 0*/
308 0x1C0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_pclk mode 0*/
309 0x1C4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data8 mode 0*/
310 0x1C8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data9 mode 0*/
311 0x208 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data0 mode 0*/
312 0x20C (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data1 mode 0*/
313 0x210 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data2 mode 0*/
314 0x214 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data3 mode 0*/
315 0x218 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data4 mode 0*/
316 0x21C (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data5 mode 0*/
317 0x220 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data6 mode 0*/
318 0x224 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data7 mode 0*/
319 >;
320 };
321
322 vpfe1_pins_default: vpfe1_pins_default {
323 pinctrl-single,pins = <
324 0x1CC (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data9 mode 0*/
325 0x1D0 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data8 mode 0*/
326 0x1D4 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_hd mode 0*/
327 0x1D8 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_vd mode 0*/
328 0x1DC (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_pclk mode 0*/
329 0x1E8 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data0 mode 0*/
330 0x1EC (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data1 mode 0*/
331 0x1F0 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data2 mode 0*/
332 0x1F4 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data3 mode 0*/
333 0x1F8 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data4 mode 0*/
334 0x1FC (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data5 mode 0*/
335 0x200 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data6 mode 0*/
336 0x204 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data7 mode 0*/
337 >;
338 };
339
340 vpfe1_pins_sleep: vpfe1_pins_sleep {
341 pinctrl-single,pins = <
342 0x1CC (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data9 mode 0*/
343 0x1D0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data8 mode 0*/
344 0x1D4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_hd mode 0*/
345 0x1D8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_vd mode 0*/
346 0x1DC (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_pclk mode 0*/
347 0x1E8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data0 mode 0*/
348 0x1EC (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data1 mode 0*/
349 0x1F0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data2 mode 0*/
350 0x1F4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data3 mode 0*/
351 0x1F8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data4 mode 0*/
352 0x1FC (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data5 mode 0*/
353 0x200 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data6 mode 0*/
354 0x204 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data7 mode 0*/
355 >;
356 };
b6bbf598
ER		 357
358 mmc3_pins_default: pinmux_mmc3_pins_default {
359 pinctrl-single,pins = <
360 0x8c (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_clk.mmc2_clk */
361 0x88 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_csn3.mmc2_cmd */
362 0x44 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a1.mmc2_dat0 */
363 0x48 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a2.mmc2_dat1 */
364 0x4c (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a3.mmc2_dat2 */
365 0x78 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_be1n.mmc2_dat3 */
366 >;
367 };
368
369 mmc3_pins_sleep: pinmux_mmc3_pins_sleep {
370 pinctrl-single,pins = <
371 0x8c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_clk.mmc2_clk */
372 0x88 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_csn3.mmc2_cmd */
373 0x44 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a1.mmc2_dat0 */
374 0x48 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a2.mmc2_dat1 */
375 0x4c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a3.mmc2_dat2 */
376 0x78 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_be1n.mmc2_dat3 */
377 >;
378 };
379
380 wlan_pins_default: pinmux_wlan_pins_default {
381 pinctrl-single,pins = <
382 0x50 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a4.gpio1_20 WL_EN */
383 0x5c (PIN_INPUT | WAKEUP_ENABLE | MUX_MODE7) /* gpmc_a7.gpio1_23 WL_IRQ*/
384 0x40 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a0.gpio1_16 BT_EN*/
385 >;
386 };
387
388 wlan_pins_sleep: pinmux_wlan_pins_sleep {
389 pinctrl-single,pins = <
390 0x50 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a4.gpio1_20 WL_EN */
391 0x5c (PIN_INPUT | WAKEUP_ENABLE | MUX_MODE7) /* gpmc_a7.gpio1_23 WL_IRQ*/
392 0x40 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a0.gpio1_16 BT_EN*/
393 >;
394 };
395
396 uart3_pins: uart3_pins {
397 pinctrl-single,pins = <
398 0x228 (PIN_INPUT | MUX_MODE0) /* uart3_rxd.uart3_rxd */
399 0x22c (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart3_txd.uart3_txd */
400 0x230 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart3_ctsn.uart3_ctsn */
401 0x234 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart3_rtsn.uart3_rtsn */
402 >;
403 };
11e2191c
LV		 404};
405
406&i2c0 {
1fc98144
K		 407 status = "okay";
408 pinctrl-names = "default";
409 pinctrl-0 = <&i2c0_pins>;
93166413 410 clock-frequency = <100000>;
0e2da5e6
K		 411
412 tps65218: tps65218@24 {
413 reg = <0x24>;
414 compatible = "ti,tps65218";
415 interrupts = <GIC_SPI 7 IRQ_TYPE_NONE>; /* NMIn */
0e2da5e6
K		 416 interrupt-controller;
417 #interrupt-cells = <2>;
418
419 dcdc1: regulator-dcdc1 {
420 compatible = "ti,tps65218-dcdc1";
421 regulator-name = "vdd_core";
422 regulator-min-microvolt = <912000>;
423 regulator-max-microvolt = <1144000>;
424 regulator-boot-on;
425 regulator-always-on;
426 };
427
428 dcdc2: regulator-dcdc2 {
429 compatible = "ti,tps65218-dcdc2";
430 regulator-name = "vdd_mpu";
431 regulator-min-microvolt = <912000>;
432 regulator-max-microvolt = <1378000>;
433 regulator-boot-on;
434 regulator-always-on;
435 };
436
437 dcdc3: regulator-dcdc3 {
438 compatible = "ti,tps65218-dcdc3";
439 regulator-name = "vdcdc3";
3015ddbd
K		 440 regulator-min-microvolt = <1500000>;
441 regulator-max-microvolt = <1500000>;
0e2da5e6
K		 442 regulator-boot-on;
443 regulator-always-on;
444 };
445 dcdc5: regulator-dcdc5 {
446 compatible = "ti,tps65218-dcdc5";
447 regulator-name = "v1_0bat";
448 regulator-min-microvolt = <1000000>;
449 regulator-max-microvolt = <1000000>;
450 };
451
452 dcdc6: regulator-dcdc6 {
453 compatible = "ti,tps65218-dcdc6";
454 regulator-name = "v1_8bat";
455 regulator-min-microvolt = <1800000>;
456 regulator-max-microvolt = <1800000>;
457 };
458
459 ldo1: regulator-ldo1 {
460 compatible = "ti,tps65218-ldo1";
461 regulator-min-microvolt = <1800000>;
462 regulator-max-microvolt = <1800000>;
463 regulator-boot-on;
464 regulator-always-on;
465 };
466 };
11e2191c
LV		 467};
468
469&i2c1 {
1fc98144
K		 470 status = "okay";
471 pinctrl-names = "default";
472 pinctrl-0 = <&i2c1_pins>;
0ebc1e25
SN		 473 pixcir_ts@5c {
474 compatible = "pixcir,pixcir_tangoc";
475 pinctrl-names = "default";
476 pinctrl-0 = <&pixcir_ts_pins>;
477 reg = <0x5c>;
478 interrupt-parent = <&gpio3>;
479 interrupts = <22 0>;
480
481 attb-gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
482
f048615e
RQ		 483 touchscreen-size-x = <1024>;
484 touchscreen-size-y = <600>;
0ebc1e25 485 };
11e2191c 486};
c540b476
SP		 487
488&epwmss0 {
489 status = "okay";
490};
491
0f39f7b9
V		 492&tscadc {
493 status = "okay";
494
495 adc {
496 ti,adc-channels = <0 1 2 3 4 5 6 7>;
497 };
498};
499
c540b476
SP		 500&ecap0 {
501 status = "okay";
502 pinctrl-names = "default";
503 pinctrl-0 = <&ecap0_pins>;
504};
d3d46cca 505
506be3fb
B		 506&gpio0 {
507 status = "okay";
508};
509
b6bbf598
ER		 510&gpio1 {
511 status = "okay";
512};
513
d3d46cca
SP		 514&gpio3 {
515 status = "okay";
516};
517
518&gpio4 {
519 status = "okay";
520};
506be3fb 521
1ff3859e
DG		 522&gpio5 {
523 status = "okay";
524 ti,no-reset-on-init;
525};
526
506be3fb
B		 527&mmc1 {
528 status = "okay";
529 vmmc-supply = <&vmmcsd_fixed>;
530 bus-width = <4>;
531 pinctrl-names = "default";
532 pinctrl-0 = <&mmc1_pins>;
533 cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
534};
b5820d3a 535
b6bbf598
ER		 536&mmc3 {
537 status = "okay";
538 /* these are on the crossbar and are outlined in the
539 xbar-event-map element */
540 dmas = <&edma 30
541 &edma 31>;
542 dma-names = "tx", "rx";
543 vmmc-supply = <&vmmcwl_fixed>;
544 bus-width = <4>;
545 pinctrl-names = "default", "sleep";
546 pinctrl-0 = <&mmc3_pins_default>;
547 pinctrl-1 = <&mmc3_pins_sleep>;
548 cap-power-off-card;
549 keep-power-in-suspend;
550 ti,non-removable;
551
552 #address-cells = <1>;
553 #size-cells = <0>;
554 wlcore: wlcore@0 {
555 compatible = "ti,wl1835";
556 reg = <2>;
557 interrupt-parent = <&gpio1>;
558 interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;
559 };
560};
561
562&edma {
563 ti,edma-xbar-event-map = /bits/ 16 <1 30
564 2 31>;
565};
566
567&uart3 {
568 status = "okay";
569 pinctrl-names = "default";
570 pinctrl-0 = <&uart3_pins>;
571};
572
b5820d3a
GC		 573&usb2_phy1 {
574 status = "okay";
575};
576
577&usb1 {
578 dr_mode = "peripheral";
579 status = "okay";
580};
581
582&usb2_phy2 {
583 status = "okay";
584};
585
586&usb2 {
587 dr_mode = "host";
588 status = "okay";
589};
7b25babf
M		 590
591&mac {
592 slaves = <1>;
593 pinctrl-names = "default", "sleep";
594 pinctrl-0 = <&cpsw_default>;
595 pinctrl-1 = <&cpsw_sleep>;
596 status = "okay";
597};
598
599&davinci_mdio {
600 pinctrl-names = "default", "sleep";
601 pinctrl-0 = <&davinci_mdio_default>;
602 pinctrl-1 = <&davinci_mdio_sleep>;
603 status = "okay";
604};
605
606&cpsw_emac0 {
607 phy_id = <&davinci_mdio>, <0>;
608 phy-mode = "rgmii";
609};
99ffa642
PG		 610
611&elm {
612 status = "okay";
613};
614
615&gpmc {
616 status = "okay";
617 pinctrl-names = "default";
618 pinctrl-0 = <&nand_flash_x8>;
619 ranges = <0 0 0 0x01000000>; /* minimum GPMC partition = 16MB */
620 nand@0,0 {
621 reg = <0 0 4>; /* device IO registers */
6b869110 622 ti,nand-ecc-opt = "bch16";
99ffa642
PG		 623 ti,elm-id = <&elm>;
624 nand-bus-width = <8>;
625 gpmc,device-width = <1>;
626 gpmc,sync-clk-ps = <0>;
627 gpmc,cs-on-ns = <0>;
628 gpmc,cs-rd-off-ns = <40>;
629 gpmc,cs-wr-off-ns = <40>;
630 gpmc,adv-on-ns = <0>;
631 gpmc,adv-rd-off-ns = <25>;
632 gpmc,adv-wr-off-ns = <25>;
633 gpmc,we-on-ns = <0>;
634 gpmc,we-off-ns = <20>;
635 gpmc,oe-on-ns = <3>;
636 gpmc,oe-off-ns = <30>;
637 gpmc,access-ns = <30>;
638 gpmc,rd-cycle-ns = <40>;
639 gpmc,wr-cycle-ns = <40>;
640 gpmc,wait-pin = <0>;
99ffa642
PG		 641 gpmc,bus-turnaround-ns = <0>;
642 gpmc,cycle2cycle-delay-ns = <0>;
643 gpmc,clk-activation-ns = <0>;
644 gpmc,wait-monitoring-ns = <0>;
645 gpmc,wr-access-ns = <40>;
646 gpmc,wr-data-mux-bus-ns = <0>;
647 /* MTD partition table */
648 /* All SPL-* partitions are sized to minimal length
649 * which can be independently programmable. For
650 * NAND flash this is equal to size of erase-block */
651 #address-cells = <1>;
652 #size-cells = <1>;
653 partition@0 {
654 label = "NAND.SPL";
655 reg = <0x00000000 0x00040000>;
656 };
657 partition@1 {
658 label = "NAND.SPL.backup1";
659 reg = <0x00040000 0x00040000>;
660 };
661 partition@2 {
662 label = "NAND.SPL.backup2";
663 reg = <0x00080000 0x00040000>;
664 };
665 partition@3 {
666 label = "NAND.SPL.backup3";
667 reg = <0x000c0000 0x00040000>;
668 };
669 partition@4 {
670 label = "NAND.u-boot-spl-os";
671 reg = <0x00100000 0x00080000>;
672 };
673 partition@5 {
674 label = "NAND.u-boot";
675 reg = <0x00180000 0x00100000>;
676 };
677 partition@6 {
678 label = "NAND.u-boot-env";
679 reg = <0x00280000 0x00040000>;
680 };
681 partition@7 {
682 label = "NAND.u-boot-env.backup1";
683 reg = <0x002c0000 0x00040000>;
684 };
685 partition@8 {
686 label = "NAND.kernel";
687 reg = <0x00300000 0x00700000>;
688 };
689 partition@9 {
690 label = "NAND.file-system";
691 reg = <0x00a00000 0x1f600000>;
692 };
693 };
694};
0bacb529
SP		 695
696&dss {
697 status = "ok";
698
699 pinctrl-names = "default";
700 pinctrl-0 = <&dss_pins>;
701
702 port {
703 dpi_out: endpoint@0 {
704 remote-endpoint = <&lcd_in>;
705 data-lines = <24>;
706 };
707 };
708};
4b1ce235
M		 709
710&dcan0 {
711 pinctrl-names = "default";
712 pinctrl-0 = <&dcan0_default>;
713 status = "okay";
714};
715
716&dcan1 {
717 pinctrl-names = "default";
718 pinctrl-0 = <&dcan1_default>;
719 status = "okay";
720};
c788a7f4
BP		 721
722&vpfe0 {
723 status = "okay";
724 pinctrl-names = "default", "sleep";
725 pinctrl-0 = <&vpfe0_pins_default>;
726 pinctrl-1 = <&vpfe0_pins_sleep>;
727
728 port {
729 vpfe0_ep: endpoint {
730 /* remote-endpoint = <&sensor>; add once we have it */
731 ti,am437x-vpfe-interface = <0>;
732 bus-width = <8>;
733 hsync-active = <0>;
734 vsync-active = <0>;
735 };
736 };
737};
738
739&vpfe1 {
740 status = "okay";
741 pinctrl-names = "default", "sleep";
742 pinctrl-0 = <&vpfe1_pins_default>;
743 pinctrl-1 = <&vpfe1_pins_sleep>;
744
745 port {
746 vpfe1_ep: endpoint {
747 /* remote-endpoint = <&sensor>; add once we have it */
748 ti,am437x-vpfe-interface = <0>;
749 bus-width = <8>;
750 hsync-active = <0>;
751 vsync-active = <0>;
752 };
753 };
754};
Linux kernel - Deliverables
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