Commit | Line | Data |
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4a45787d FB |
1 | /* |
2 | * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | */ | |
8 | ||
9 | /* AM437x SK EVM */ | |
10 | ||
11 | /dts-v1/; | |
12 | ||
13 | #include "am4372.dtsi" | |
14 | #include <dt-bindings/pinctrl/am43xx.h> | |
15 | #include <dt-bindings/pwm/pwm.h> | |
16 | #include <dt-bindings/gpio/gpio.h> | |
17 | #include <dt-bindings/input/input.h> | |
18 | ||
19 | / { | |
20 | model = "TI AM437x SK EVM"; | |
21 | compatible = "ti,am437x-sk-evm","ti,am4372","ti,am43"; | |
22 | ||
23 | aliases { | |
24 | display0 = &lcd0; | |
25 | }; | |
26 | ||
27 | backlight { | |
28 | compatible = "pwm-backlight"; | |
29 | pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>; | |
30 | brightness-levels = <0 51 53 56 62 75 101 152 255>; | |
31 | default-brightness-level = <8>; | |
32 | }; | |
33 | ||
34 | sound { | |
35 | compatible = "ti,da830-evm-audio"; | |
36 | ti,model = "AM437x-SK-EVM"; | |
37 | ti,audio-codec = <&tlv320aic3106>; | |
38 | ti,mcasp-controller = <&mcasp1>; | |
39 | ti,codec-clock-rate = <24000000>; | |
40 | ti,audio-routing = | |
41 | "Headphone Jack", "HPLOUT", | |
42 | "Headphone Jack", "HPROUT"; | |
43 | }; | |
44 | ||
45 | matrix_keypad: matrix_keypad@0 { | |
46 | compatible = "gpio-matrix-keypad"; | |
47 | ||
48 | pinctrl-names = "default"; | |
49 | pinctrl-0 = <&matrix_keypad_pins>; | |
50 | ||
51 | debounce-delay-ms = <5>; | |
52 | col-scan-delay-us = <1500>; | |
53 | ||
54 | row-gpios = <&gpio5 5 GPIO_ACTIVE_HIGH /* Bank5, pin5 */ | |
55 | &gpio5 6 GPIO_ACTIVE_HIGH>; /* Bank5, pin6 */ | |
56 | ||
57 | col-gpios = <&gpio5 13 GPIO_ACTIVE_HIGH /* Bank5, pin13 */ | |
58 | &gpio5 4 GPIO_ACTIVE_HIGH>; /* Bank5, pin4 */ | |
59 | ||
60 | linux,keymap = < | |
61 | MATRIX_KEY(0, 0, KEY_DOWN) | |
62 | MATRIX_KEY(0, 1, KEY_RIGHT) | |
63 | MATRIX_KEY(1, 0, KEY_LEFT) | |
64 | MATRIX_KEY(1, 1, KEY_UP) | |
65 | >; | |
66 | }; | |
67 | ||
68 | leds { | |
69 | compatible = "gpio-leds"; | |
70 | ||
71 | pinctrl-names = "default"; | |
72 | pinctrl-0 = <&leds_pins>; | |
73 | ||
74 | led@0 { | |
75 | label = "am437x-sk:red:heartbeat"; | |
76 | gpios = <&gpio5 0 GPIO_ACTIVE_HIGH>; /* Bank 5, pin 0 */ | |
77 | linux,default-trigger = "heartbeat"; | |
78 | default-state = "off"; | |
79 | }; | |
80 | ||
81 | led@1 { | |
82 | label = "am437x-sk:green:mmc1"; | |
83 | gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; /* Bank 5, pin 1 */ | |
84 | linux,default-trigger = "mmc0"; | |
85 | default-state = "off"; | |
86 | }; | |
87 | ||
88 | led@2 { | |
89 | label = "am437x-sk:blue:cpu0"; | |
90 | gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>; /* Bank 5, pin 2 */ | |
91 | linux,default-trigger = "cpu0"; | |
92 | default-state = "off"; | |
93 | }; | |
94 | ||
95 | led@3 { | |
96 | label = "am437x-sk:blue:usr3"; | |
97 | gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>; /* Bank 5, pin 3 */ | |
98 | default-state = "off"; | |
99 | }; | |
100 | }; | |
101 | ||
102 | lcd0: display { | |
d73f825e | 103 | compatible = "newhaven,nhd-4.3-480272ef-atxl", "panel-dpi"; |
4a45787d FB |
104 | label = "lcd"; |
105 | ||
106 | pinctrl-names = "default"; | |
107 | pinctrl-0 = <&lcd_pins>; | |
108 | ||
109 | enable-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; | |
110 | ||
111 | panel-timing { | |
112 | clock-frequency = <9000000>; | |
113 | hactive = <480>; | |
114 | vactive = <272>; | |
d73f825e TV |
115 | hfront-porch = <2>; |
116 | hback-porch = <2>; | |
117 | hsync-len = <41>; | |
118 | vfront-porch = <2>; | |
119 | vback-porch = <2>; | |
4a45787d FB |
120 | vsync-len = <10>; |
121 | hsync-active = <0>; | |
122 | vsync-active = <0>; | |
123 | de-active = <1>; | |
124 | pixelclk-active = <1>; | |
125 | }; | |
126 | ||
127 | port { | |
128 | lcd_in: endpoint { | |
129 | remote-endpoint = <&dpi_out>; | |
130 | }; | |
131 | }; | |
132 | }; | |
133 | }; | |
134 | ||
135 | &am43xx_pinmux { | |
136 | matrix_keypad_pins: matrix_keypad_pins { | |
137 | pinctrl-single,pins = < | |
138 | 0x24c (PIN_OUTPUT | MUX_MODE7) /* gpio5_13.gpio5_13 */ | |
139 | 0x250 (PIN_OUTPUT | MUX_MODE7) /* spi4_sclk.gpio5_4 */ | |
140 | 0x254 (PIN_INPUT | MUX_MODE7) /* spi4_d0.gpio5_5 */ | |
141 | 0x258 (PIN_INPUT | MUX_MODE7) /* spi4_d1.gpio5_5 */ | |
142 | >; | |
143 | }; | |
144 | ||
145 | leds_pins: leds_pins { | |
146 | pinctrl-single,pins = < | |
147 | 0x228 (PIN_OUTPUT | MUX_MODE7) /* uart3_rxd.gpio5_2 */ | |
148 | 0x22c (PIN_OUTPUT | MUX_MODE7) /* uart3_txd.gpio5_3 */ | |
149 | 0x230 (PIN_OUTPUT | MUX_MODE7) /* uart3_ctsn.gpio5_0 */ | |
150 | 0x234 (PIN_OUTPUT | MUX_MODE7) /* uart3_rtsn.gpio5_1 */ | |
151 | >; | |
152 | }; | |
153 | ||
154 | i2c0_pins: i2c0_pins { | |
155 | pinctrl-single,pins = < | |
3cca412e FB |
156 | 0x188 (PIN_INPUT | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_sda.i2c0_sda */ |
157 | 0x18c (PIN_INPUT | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */ | |
4a45787d FB |
158 | >; |
159 | }; | |
160 | ||
161 | i2c1_pins: i2c1_pins { | |
162 | pinctrl-single,pins = < | |
3cca412e FB |
163 | 0x15c (PIN_INPUT | SLEWCTRL_FAST | MUX_MODE2) /* spi0_cs0.i2c1_scl */ |
164 | 0x158 (PIN_INPUT | SLEWCTRL_FAST | MUX_MODE2) /* spi0_d1.i2c1_sda */ | |
4a45787d FB |
165 | >; |
166 | }; | |
167 | ||
168 | mmc1_pins: pinmux_mmc1_pins { | |
169 | pinctrl-single,pins = < | |
fb135053 FB |
170 | 0x0f0 (PIN_INPUT | MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */ |
171 | 0x0f4 (PIN_INPUT | MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */ | |
172 | 0x0f8 (PIN_INPUT | MUX_MODE0) /* mmc0_dat1.mmc0_dat1 */ | |
173 | 0x0fc (PIN_INPUT | MUX_MODE0) /* mmc0_dat0.mmc0_dat0 */ | |
174 | 0x100 (PIN_INPUT | MUX_MODE0) /* mmc0_clk.mmc0_clk */ | |
175 | 0x104 (PIN_INPUT | MUX_MODE0) /* mmc0_cmd.mmc0_cmd */ | |
4a45787d FB |
176 | 0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */ |
177 | >; | |
178 | }; | |
179 | ||
180 | ecap0_pins: backlight_pins { | |
181 | pinctrl-single,pins = < | |
182 | 0x164 (PIN_OUTPUT | MUX_MODE0) /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out */ | |
183 | >; | |
184 | }; | |
185 | ||
186 | edt_ft5306_ts_pins: edt_ft5306_ts_pins { | |
187 | pinctrl-single,pins = < | |
188 | 0x74 (PIN_INPUT | MUX_MODE7) /* gpmc_wpn.gpio0_31 */ | |
189 | 0x78 (PIN_OUTPUT | MUX_MODE7) /* gpmc_be1n.gpio1_28 */ | |
190 | >; | |
191 | }; | |
192 | ||
5ccaa6ec DE |
193 | vpfe0_pins_default: vpfe0_pins_default { |
194 | pinctrl-single,pins = < | |
195 | 0x1b0 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_hd mode 0*/ | |
196 | 0x1b4 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_vd mode 0*/ | |
197 | 0x1b8 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_field mode 0*/ | |
198 | 0x1bc (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_wen mode 0*/ | |
199 | 0x1c0 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_pclk mode 0*/ | |
200 | 0x1c4 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data8 mode 0*/ | |
201 | 0x1c8 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data9 mode 0*/ | |
202 | 0x208 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data0 mode 0*/ | |
203 | 0x20c (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data1 mode 0*/ | |
204 | 0x210 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data2 mode 0*/ | |
205 | 0x214 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data3 mode 0*/ | |
206 | 0x218 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data4 mode 0*/ | |
207 | 0x21c (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data5 mode 0*/ | |
208 | 0x220 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data6 mode 0*/ | |
209 | 0x224 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data7 mode 0*/ | |
210 | >; | |
211 | }; | |
212 | ||
213 | vpfe0_pins_sleep: vpfe0_pins_sleep { | |
214 | pinctrl-single,pins = < | |
215 | 0x1b0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) | |
216 | 0x1b4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) | |
217 | 0x1b8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) | |
218 | 0x1bc (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) | |
219 | 0x1c0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) | |
220 | 0x1c4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) | |
221 | 0x1c8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) | |
222 | 0x208 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) | |
223 | 0x20c (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) | |
224 | 0x210 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) | |
225 | 0x214 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) | |
226 | 0x218 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) | |
227 | 0x21c (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) | |
228 | 0x220 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) | |
229 | 0x224 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) | |
230 | >; | |
231 | }; | |
232 | ||
4a45787d FB |
233 | cpsw_default: cpsw_default { |
234 | pinctrl-single,pins = < | |
235 | /* Slave 1 */ | |
a2db983a FB |
236 | 0x12c (PIN_OUTPUT | MUX_MODE2) /* mii1_txclk.rmii1_tclk */ |
237 | 0x114 (PIN_OUTPUT | MUX_MODE2) /* mii1_txen.rgmii1_tctl */ | |
238 | 0x128 (PIN_OUTPUT | MUX_MODE2) /* mii1_txd0.rgmii1_td0 */ | |
239 | 0x124 (PIN_OUTPUT | MUX_MODE2) /* mii1_txd1.rgmii1_td1 */ | |
240 | 0x120 (PIN_OUTPUT | MUX_MODE2) /* mii1_txd0.rgmii1_td2 */ | |
241 | 0x11c (PIN_OUTPUT | MUX_MODE2) /* mii1_txd1.rgmii1_td3 */ | |
242 | 0x130 (PIN_INPUT | MUX_MODE2) /* mii1_rxclk.rmii1_rclk */ | |
243 | 0x118 (PIN_INPUT | MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */ | |
244 | 0x140 (PIN_INPUT | MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */ | |
245 | 0x13c (PIN_INPUT | MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */ | |
246 | 0x138 (PIN_INPUT | MUX_MODE2) /* mii1_rxd0.rgmii1_rd2 */ | |
247 | 0x134 (PIN_INPUT | MUX_MODE2) /* mii1_rxd1.rgmii1_rd3 */ | |
4a45787d FB |
248 | |
249 | /* Slave 2 */ | |
a2db983a FB |
250 | 0x58 (PIN_OUTPUT | MUX_MODE2) /* gpmc_a6.rgmii2_tclk */ |
251 | 0x40 (PIN_OUTPUT | MUX_MODE2) /* gpmc_a0.rgmii2_tctl */ | |
252 | 0x54 (PIN_OUTPUT | MUX_MODE2) /* gpmc_a5.rgmii2_td0 */ | |
253 | 0x50 (PIN_OUTPUT | MUX_MODE2) /* gpmc_a4.rgmii2_td1 */ | |
254 | 0x4c (PIN_OUTPUT | MUX_MODE2) /* gpmc_a3.rgmii2_td2 */ | |
255 | 0x48 (PIN_OUTPUT | MUX_MODE2) /* gpmc_a2.rgmii2_td3 */ | |
256 | 0x5c (PIN_INPUT | MUX_MODE2) /* gpmc_a7.rgmii2_rclk */ | |
257 | 0x44 (PIN_INPUT | MUX_MODE2) /* gpmc_a1.rgmii2_rtcl */ | |
258 | 0x6c (PIN_INPUT | MUX_MODE2) /* gpmc_a11.rgmii2_rd0 */ | |
259 | 0x68 (PIN_INPUT | MUX_MODE2) /* gpmc_a10.rgmii2_rd1 */ | |
260 | 0x64 (PIN_INPUT | MUX_MODE2) /* gpmc_a9.rgmii2_rd2 */ | |
261 | 0x60 (PIN_INPUT | MUX_MODE2) /* gpmc_a8.rgmii2_rd3 */ | |
4a45787d FB |
262 | >; |
263 | }; | |
264 | ||
265 | cpsw_sleep: cpsw_sleep { | |
266 | pinctrl-single,pins = < | |
267 | /* Slave 1 reset value */ | |
268 | 0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7) | |
269 | 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7) | |
270 | 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7) | |
271 | 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7) | |
272 | 0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7) | |
273 | 0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7) | |
274 | 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7) | |
275 | 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7) | |
276 | 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7) | |
277 | 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7) | |
278 | 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7) | |
279 | 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7) | |
280 | ||
281 | /* Slave 2 reset value */ | |
282 | 0x58 (PIN_INPUT_PULLDOWN | MUX_MODE7) | |
283 | 0x40 (PIN_INPUT_PULLDOWN | MUX_MODE7) | |
284 | 0x54 (PIN_INPUT_PULLDOWN | MUX_MODE7) | |
285 | 0x50 (PIN_INPUT_PULLDOWN | MUX_MODE7) | |
286 | 0x4c (PIN_INPUT_PULLDOWN | MUX_MODE7) | |
287 | 0x48 (PIN_INPUT_PULLDOWN | MUX_MODE7) | |
288 | 0x5c (PIN_INPUT_PULLDOWN | MUX_MODE7) | |
289 | 0x44 (PIN_INPUT_PULLDOWN | MUX_MODE7) | |
290 | 0x6c (PIN_INPUT_PULLDOWN | MUX_MODE7) | |
291 | 0x68 (PIN_INPUT_PULLDOWN | MUX_MODE7) | |
292 | 0x64 (PIN_INPUT_PULLDOWN | MUX_MODE7) | |
293 | 0x60 (PIN_INPUT_PULLDOWN | MUX_MODE7) | |
294 | >; | |
295 | }; | |
296 | ||
297 | davinci_mdio_default: davinci_mdio_default { | |
298 | pinctrl-single,pins = < | |
299 | /* MDIO */ | |
a2db983a FB |
300 | 0x148 (PIN_INPUT | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ |
301 | 0x14c (PIN_OUTPUT | MUX_MODE0) /* mdio_clk.mdio_clk */ | |
4a45787d FB |
302 | >; |
303 | }; | |
304 | ||
305 | davinci_mdio_sleep: davinci_mdio_sleep { | |
306 | pinctrl-single,pins = < | |
307 | /* MDIO reset value */ | |
308 | 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7) | |
309 | 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7) | |
310 | >; | |
311 | }; | |
312 | ||
313 | dss_pins: dss_pins { | |
314 | pinctrl-single,pins = < | |
2d8a28c2 FB |
315 | 0x020 (PIN_OUTPUT | MUX_MODE1) /* gpmc ad 8 -> DSS DATA 23 */ |
316 | 0x024 (PIN_OUTPUT | MUX_MODE1) | |
317 | 0x028 (PIN_OUTPUT | MUX_MODE1) | |
318 | 0x02c (PIN_OUTPUT | MUX_MODE1) | |
319 | 0x030 (PIN_OUTPUT | MUX_MODE1) | |
320 | 0x034 (PIN_OUTPUT | MUX_MODE1) | |
321 | 0x038 (PIN_OUTPUT | MUX_MODE1) | |
322 | 0x03c (PIN_OUTPUT | MUX_MODE1) /* gpmc ad 15 -> DSS DATA 16 */ | |
323 | 0x0a0 (PIN_OUTPUT | MUX_MODE0) /* DSS DATA 0 */ | |
324 | 0x0a4 (PIN_OUTPUT | MUX_MODE0) | |
325 | 0x0a8 (PIN_OUTPUT | MUX_MODE0) | |
326 | 0x0ac (PIN_OUTPUT | MUX_MODE0) | |
327 | 0x0b0 (PIN_OUTPUT | MUX_MODE0) | |
328 | 0x0b4 (PIN_OUTPUT | MUX_MODE0) | |
329 | 0x0b8 (PIN_OUTPUT | MUX_MODE0) | |
330 | 0x0bc (PIN_OUTPUT | MUX_MODE0) | |
331 | 0x0c0 (PIN_OUTPUT | MUX_MODE0) | |
332 | 0x0c4 (PIN_OUTPUT | MUX_MODE0) | |
333 | 0x0c8 (PIN_OUTPUT | MUX_MODE0) | |
334 | 0x0cc (PIN_OUTPUT | MUX_MODE0) | |
335 | 0x0d0 (PIN_OUTPUT | MUX_MODE0) | |
336 | 0x0d4 (PIN_OUTPUT | MUX_MODE0) | |
337 | 0x0d8 (PIN_OUTPUT | MUX_MODE0) | |
338 | 0x0dc (PIN_OUTPUT | MUX_MODE0) /* DSS DATA 15 */ | |
339 | 0x0e0 (PIN_OUTPUT | MUX_MODE0) /* DSS VSYNC */ | |
340 | 0x0e4 (PIN_OUTPUT | MUX_MODE0) /* DSS HSYNC */ | |
341 | 0x0e8 (PIN_OUTPUT | MUX_MODE0) /* DSS PCLK */ | |
342 | 0x0ec (PIN_OUTPUT | MUX_MODE0) /* DSS AC BIAS EN */ | |
4a45787d FB |
343 | |
344 | >; | |
345 | }; | |
346 | ||
347 | qspi_pins: qspi_pins { | |
348 | pinctrl-single,pins = < | |
fad7ca8b FB |
349 | 0x7c (PIN_OUTPUT | MUX_MODE3) /* gpmc_csn0.qspi_csn */ |
350 | 0x88 (PIN_OUTPUT | MUX_MODE2) /* gpmc_csn3.qspi_clk */ | |
351 | 0x90 (PIN_INPUT | MUX_MODE3) /* gpmc_advn_ale.qspi_d0 */ | |
352 | 0x94 (PIN_INPUT | MUX_MODE3) /* gpmc_oen_ren.qspi_d1 */ | |
353 | 0x98 (PIN_INPUT | MUX_MODE3) /* gpmc_wen.qspi_d2 */ | |
354 | 0x9c (PIN_INPUT | MUX_MODE3) /* gpmc_be0n_cle.qspi_d3 */ | |
4a45787d FB |
355 | >; |
356 | }; | |
357 | ||
358 | mcasp1_pins: mcasp1_pins { | |
359 | pinctrl-single,pins = < | |
360 | 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_crs.mcasp1_aclkx */ | |
361 | 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_rxerr.mcasp1_fsx */ | |
362 | 0x108 (PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* mii1_col.mcasp1_axr2 */ | |
363 | 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */ | |
364 | >; | |
365 | }; | |
366 | ||
367 | lcd_pins: lcd_pins { | |
368 | pinctrl-single,pins = < | |
58230c2c | 369 | 0x1c (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpcm_ad7.gpio1_7 */ |
4a45787d FB |
370 | >; |
371 | }; | |
221fed3c FB |
372 | |
373 | usb1_pins: usb1_pins { | |
374 | pinctrl-single,pins = < | |
375 | 0x2c0 (PIN_OUTPUT | MUX_MODE0) /* usb0_drvvbus.usb0_drvvbus */ | |
376 | >; | |
377 | }; | |
378 | ||
379 | usb2_pins: usb2_pins { | |
380 | pinctrl-single,pins = < | |
381 | 0x2c4 (PIN_OUTPUT | MUX_MODE0) /* usb0_drvvbus.usb0_drvvbus */ | |
382 | >; | |
383 | }; | |
4a45787d FB |
384 | }; |
385 | ||
386 | &i2c0 { | |
387 | status = "okay"; | |
388 | pinctrl-names = "default"; | |
389 | pinctrl-0 = <&i2c0_pins>; | |
390 | clock-frequency = <400000>; | |
391 | ||
392 | tps@24 { | |
393 | compatible = "ti,tps65218"; | |
394 | reg = <0x24>; | |
395 | interrupt-parent = <&gic>; | |
396 | interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; | |
397 | interrupt-controller; | |
398 | #interrupt-cells = <2>; | |
399 | ||
400 | dcdc1: regulator-dcdc1 { | |
401 | compatible = "ti,tps65218-dcdc1"; | |
402 | /* VDD_CORE limits min of OPP50 and max of OPP100 */ | |
403 | regulator-name = "vdd_core"; | |
404 | regulator-min-microvolt = <912000>; | |
405 | regulator-max-microvolt = <1144000>; | |
406 | regulator-boot-on; | |
407 | regulator-always-on; | |
408 | }; | |
409 | ||
410 | dcdc2: regulator-dcdc2 { | |
411 | compatible = "ti,tps65218-dcdc2"; | |
412 | /* VDD_MPU limits min of OPP50 and max of OPP_NITRO */ | |
413 | regulator-name = "vdd_mpu"; | |
414 | regulator-min-microvolt = <912000>; | |
415 | regulator-max-microvolt = <1378000>; | |
416 | regulator-boot-on; | |
417 | regulator-always-on; | |
418 | }; | |
419 | ||
420 | dcdc3: regulator-dcdc3 { | |
421 | compatible = "ti,tps65218-dcdc3"; | |
422 | regulator-name = "vdds_ddr"; | |
5cd98a7a K |
423 | regulator-min-microvolt = <1500000>; |
424 | regulator-max-microvolt = <1500000>; | |
4a45787d FB |
425 | regulator-boot-on; |
426 | regulator-always-on; | |
427 | }; | |
428 | ||
429 | dcdc4: regulator-dcdc4 { | |
430 | compatible = "ti,tps65218-dcdc4"; | |
431 | regulator-name = "v3_3d"; | |
432 | regulator-min-microvolt = <3300000>; | |
433 | regulator-max-microvolt = <3300000>; | |
434 | regulator-boot-on; | |
435 | regulator-always-on; | |
436 | }; | |
437 | ||
438 | ldo1: regulator-ldo1 { | |
439 | compatible = "ti,tps65218-ldo1"; | |
440 | regulator-name = "v1_8d"; | |
441 | regulator-min-microvolt = <1800000>; | |
442 | regulator-max-microvolt = <1800000>; | |
443 | regulator-boot-on; | |
444 | regulator-always-on; | |
445 | }; | |
446 | ||
bb1c5fe1 FB |
447 | power-button { |
448 | compatible = "ti,tps65218-pwrbutton"; | |
449 | status = "okay"; | |
450 | interrupts = <3 IRQ_TYPE_EDGE_BOTH>; | |
451 | }; | |
4a45787d FB |
452 | }; |
453 | ||
454 | at24@50 { | |
455 | compatible = "at24,24c256"; | |
456 | pagesize = <64>; | |
457 | reg = <0x50>; | |
458 | }; | |
459 | }; | |
460 | ||
461 | &i2c1 { | |
462 | status = "okay"; | |
463 | pinctrl-names = "default"; | |
464 | pinctrl-0 = <&i2c1_pins>; | |
465 | clock-frequency = <400000>; | |
466 | ||
467 | edt-ft5306@38 { | |
468 | status = "okay"; | |
469 | compatible = "edt,edt-ft5306", "edt,edt-ft5x06"; | |
470 | pinctrl-names = "default"; | |
471 | pinctrl-0 = <&edt_ft5306_ts_pins>; | |
472 | ||
473 | reg = <0x38>; | |
474 | interrupt-parent = <&gpio0>; | |
475 | interrupts = <31 0>; | |
476 | ||
477 | wake-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>; | |
478 | ||
479 | touchscreen-size-x = <480>; | |
480 | touchscreen-size-y = <272>; | |
481 | }; | |
482 | ||
483 | tlv320aic3106: tlv320aic3106@1b { | |
484 | compatible = "ti,tlv320aic3106"; | |
485 | reg = <0x1b>; | |
486 | status = "okay"; | |
487 | ||
488 | /* Regulators */ | |
489 | AVDD-supply = <&dcdc4>; | |
490 | IOVDD-supply = <&dcdc4>; | |
491 | DRVDD-supply = <&dcdc4>; | |
492 | DVDD-supply = <&ldo1>; | |
493 | }; | |
494 | ||
495 | lis331dlh@18 { | |
496 | compatible = "st,lis331dlh"; | |
497 | reg = <0x18>; | |
498 | status = "okay"; | |
499 | ||
500 | Vdd-supply = <&dcdc4>; | |
501 | Vdd_IO-supply = <&dcdc4>; | |
502 | interrupts-extended = <&gpio1 6 0>, <&gpio2 1 0>; | |
503 | }; | |
504 | }; | |
505 | ||
506 | &epwmss0 { | |
507 | status = "okay"; | |
508 | }; | |
509 | ||
510 | &ecap0 { | |
511 | status = "okay"; | |
512 | pinctrl-names = "default"; | |
513 | pinctrl-0 = <&ecap0_pins>; | |
514 | }; | |
515 | ||
516 | &gpio0 { | |
517 | status = "okay"; | |
518 | }; | |
519 | ||
520 | &gpio1 { | |
521 | status = "okay"; | |
522 | }; | |
523 | ||
524 | &gpio5 { | |
525 | status = "okay"; | |
526 | }; | |
527 | ||
528 | &mmc1 { | |
529 | status = "okay"; | |
530 | pinctrl-names = "default"; | |
531 | pinctrl-0 = <&mmc1_pins>; | |
532 | ||
533 | vmmc-supply = <&dcdc4>; | |
534 | bus-width = <4>; | |
535 | cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>; | |
536 | }; | |
537 | ||
538 | &usb2_phy1 { | |
539 | status = "okay"; | |
540 | }; | |
541 | ||
542 | &usb1 { | |
543 | dr_mode = "peripheral"; | |
544 | status = "okay"; | |
221fed3c FB |
545 | pinctrl-names = "default"; |
546 | pinctrl-0 = <&usb1_pins>; | |
4a45787d FB |
547 | }; |
548 | ||
549 | &usb2_phy2 { | |
550 | status = "okay"; | |
551 | }; | |
552 | ||
553 | &usb2 { | |
554 | dr_mode = "host"; | |
555 | status = "okay"; | |
221fed3c FB |
556 | pinctrl-names = "default"; |
557 | pinctrl-0 = <&usb2_pins>; | |
4a45787d FB |
558 | }; |
559 | ||
560 | &qspi { | |
561 | status = "okay"; | |
562 | pinctrl-names = "default"; | |
563 | pinctrl-0 = <&qspi_pins>; | |
564 | ||
565 | spi-max-frequency = <48000000>; | |
566 | m25p80@0 { | |
567 | compatible = "mx66l51235l"; | |
568 | spi-max-frequency = <48000000>; | |
569 | reg = <0>; | |
570 | spi-cpol; | |
571 | spi-cpha; | |
572 | spi-tx-bus-width = <1>; | |
573 | spi-rx-bus-width = <4>; | |
574 | #address-cells = <1>; | |
575 | #size-cells = <1>; | |
576 | ||
577 | /* MTD partition table. | |
578 | * The ROM checks the first 512KiB | |
579 | * for a valid file to boot(XIP). | |
580 | */ | |
581 | partition@0 { | |
582 | label = "QSPI.U_BOOT"; | |
583 | reg = <0x00000000 0x000080000>; | |
584 | }; | |
585 | partition@1 { | |
586 | label = "QSPI.U_BOOT.backup"; | |
587 | reg = <0x00080000 0x00080000>; | |
588 | }; | |
589 | partition@2 { | |
590 | label = "QSPI.U-BOOT-SPL_OS"; | |
591 | reg = <0x00100000 0x00010000>; | |
592 | }; | |
593 | partition@3 { | |
594 | label = "QSPI.U_BOOT_ENV"; | |
595 | reg = <0x00110000 0x00010000>; | |
596 | }; | |
597 | partition@4 { | |
598 | label = "QSPI.U-BOOT-ENV.backup"; | |
599 | reg = <0x00120000 0x00010000>; | |
600 | }; | |
601 | partition@5 { | |
602 | label = "QSPI.KERNEL"; | |
603 | reg = <0x00130000 0x0800000>; | |
604 | }; | |
605 | partition@6 { | |
606 | label = "QSPI.FILESYSTEM"; | |
607 | reg = <0x00930000 0x36D0000>; | |
608 | }; | |
609 | }; | |
610 | }; | |
611 | ||
612 | &mac { | |
613 | pinctrl-names = "default", "sleep"; | |
614 | pinctrl-0 = <&cpsw_default>; | |
615 | pinctrl-1 = <&cpsw_sleep>; | |
616 | dual_emac = <1>; | |
617 | status = "okay"; | |
618 | }; | |
619 | ||
620 | &davinci_mdio { | |
621 | pinctrl-names = "default", "sleep"; | |
622 | pinctrl-0 = <&davinci_mdio_default>; | |
623 | pinctrl-1 = <&davinci_mdio_sleep>; | |
624 | status = "okay"; | |
625 | }; | |
626 | ||
627 | &cpsw_emac0 { | |
628 | phy_id = <&davinci_mdio>, <4>; | |
629 | phy-mode = "rgmii"; | |
630 | dual_emac_res_vlan = <1>; | |
631 | }; | |
632 | ||
633 | &cpsw_emac1 { | |
634 | phy_id = <&davinci_mdio>, <5>; | |
635 | phy-mode = "rgmii"; | |
636 | dual_emac_res_vlan = <2>; | |
637 | }; | |
638 | ||
639 | &elm { | |
640 | status = "okay"; | |
641 | }; | |
642 | ||
643 | &mcasp1 { | |
644 | pinctrl-names = "default"; | |
645 | pinctrl-0 = <&mcasp1_pins>; | |
646 | ||
647 | status = "okay"; | |
648 | ||
649 | op-mode = <0>; | |
650 | tdm-slots = <2>; | |
651 | serial-dir = < | |
652 | 0 0 1 2 | |
653 | >; | |
654 | ||
655 | tx-num-evt = <1>; | |
656 | rx-num-evt = <1>; | |
657 | }; | |
658 | ||
659 | &dss { | |
660 | status = "okay"; | |
661 | ||
662 | pinctrl-names = "default"; | |
663 | pinctrl-0 = <&dss_pins>; | |
664 | ||
665 | port { | |
666 | dpi_out: endpoint@0 { | |
667 | remote-endpoint = <&lcd_in>; | |
668 | data-lines = <24>; | |
669 | }; | |
670 | }; | |
671 | }; | |
672 | ||
673 | &rtc { | |
674 | status = "okay"; | |
675 | }; | |
676 | ||
677 | &wdt { | |
678 | status = "okay"; | |
679 | }; | |
3e1fe451 DG |
680 | |
681 | &cpu { | |
682 | cpu0-supply = <&dcdc2>; | |
683 | }; | |
5ccaa6ec DE |
684 | |
685 | &vpfe0 { | |
686 | status = "okay"; | |
687 | pinctrl-names = "default", "sleep"; | |
688 | pinctrl-0 = <&vpfe0_pins_default>; | |
689 | pinctrl-1 = <&vpfe0_pins_sleep>; | |
690 | ||
691 | /* Camera port */ | |
692 | port { | |
693 | vpfe0_ep: endpoint { | |
694 | /* remote-endpoint = <&sensor>; add once we have it */ | |
695 | ti,am437x-vpfe-interface = <0>; | |
696 | bus-width = <8>; | |
697 | hsync-active = <0>; | |
698 | vsync-active = <0>; | |
699 | }; | |
700 | }; | |
701 | }; |