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rtc: s5m: fix to update ctrl register
[deliverable/linux.git] / arch / arm / boot / dts / am437x-sk-evm.dts
CommitLineData
4a45787d
FB		 1/*
2 * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9/* AM437x SK EVM */
10
11/dts-v1/;
12
13#include "am4372.dtsi"
14#include <dt-bindings/pinctrl/am43xx.h>
15#include <dt-bindings/pwm/pwm.h>
16#include <dt-bindings/gpio/gpio.h>
17#include <dt-bindings/input/input.h>
18
19/ {
20 model = "TI AM437x SK EVM";
21 compatible = "ti,am437x-sk-evm","ti,am4372","ti,am43";
22
23 aliases {
24 display0 = &lcd0;
25 };
26
27 backlight {
28 compatible = "pwm-backlight";
29 pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>;
30 brightness-levels = <0 51 53 56 62 75 101 152 255>;
31 default-brightness-level = <8>;
32 };
33
34 sound {
20746c50
PU		 35 compatible = "simple-audio-card";
36 simple-audio-card,name = "AM437x-SK-EVM";
37 simple-audio-card,widgets =
38 "Headphone", "Headphone Jack",
39 "Line", "Line In";
40 simple-audio-card,routing =
41 "Headphone Jack", "HPLOUT",
42 "Headphone Jack", "HPROUT",
43 "LINE1L", "Line In",
44 "LINE1R", "Line In";
45 simple-audio-card,format = "dsp_b";
46 simple-audio-card,bitclock-master = <&sound_master>;
47 simple-audio-card,frame-master = <&sound_master>;
48 simple-audio-card,bitclock-inversion;
49
50 simple-audio-card,cpu {
51 sound-dai = <&mcasp1>;
52 };
53
54 sound_master: simple-audio-card,codec {
55 sound-dai = <&tlv320aic3106>;
56 system-clock-frequency = <24000000>;
57 };
4a45787d
FB		 58 };
59
60 matrix_keypad: matrix_keypad@0 {
61 compatible = "gpio-matrix-keypad";
62
63 pinctrl-names = "default";
64 pinctrl-0 = <&matrix_keypad_pins>;
65
66 debounce-delay-ms = <5>;
f6b957fd 67 col-scan-delay-us = <5>;
4a45787d
FB		 68
69 row-gpios = <&gpio5 5 GPIO_ACTIVE_HIGH /* Bank5, pin5 */
70 &gpio5 6 GPIO_ACTIVE_HIGH>; /* Bank5, pin6 */
71
72 col-gpios = <&gpio5 13 GPIO_ACTIVE_HIGH /* Bank5, pin13 */
73 &gpio5 4 GPIO_ACTIVE_HIGH>; /* Bank5, pin4 */
74
75 linux,keymap = <
76 MATRIX_KEY(0, 0, KEY_DOWN)
77 MATRIX_KEY(0, 1, KEY_RIGHT)
78 MATRIX_KEY(1, 0, KEY_LEFT)
79 MATRIX_KEY(1, 1, KEY_UP)
80 >;
81 };
82
83 leds {
84 compatible = "gpio-leds";
85
86 pinctrl-names = "default";
87 pinctrl-0 = <&leds_pins>;
88
89 led@0 {
90 label = "am437x-sk:red:heartbeat";
91 gpios = <&gpio5 0 GPIO_ACTIVE_HIGH>; /* Bank 5, pin 0 */
92 linux,default-trigger = "heartbeat";
93 default-state = "off";
94 };
95
96 led@1 {
97 label = "am437x-sk:green:mmc1";
98 gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; /* Bank 5, pin 1 */
99 linux,default-trigger = "mmc0";
100 default-state = "off";
101 };
102
103 led@2 {
104 label = "am437x-sk:blue:cpu0";
105 gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>; /* Bank 5, pin 2 */
106 linux,default-trigger = "cpu0";
107 default-state = "off";
108 };
109
110 led@3 {
111 label = "am437x-sk:blue:usr3";
112 gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>; /* Bank 5, pin 3 */
113 default-state = "off";
114 };
115 };
116
117 lcd0: display {
d73f825e 118 compatible = "newhaven,nhd-4.3-480272ef-atxl", "panel-dpi";
4a45787d
FB		 119 label = "lcd";
120
121 pinctrl-names = "default";
122 pinctrl-0 = <&lcd_pins>;
123
124 enable-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
125
126 panel-timing {
127 clock-frequency = <9000000>;
128 hactive = <480>;
129 vactive = <272>;
d73f825e
TV		 130 hfront-porch = <2>;
131 hback-porch = <2>;
132 hsync-len = <41>;
133 vfront-porch = <2>;
134 vback-porch = <2>;
4a45787d
FB		 135 vsync-len = <10>;
136 hsync-active = <0>;
137 vsync-active = <0>;
138 de-active = <1>;
139 pixelclk-active = <1>;
140 };
141
142 port {
143 lcd_in: endpoint {
144 remote-endpoint = <&dpi_out>;
145 };
146 };
147 };
148};
149
150&am43xx_pinmux {
151 matrix_keypad_pins: matrix_keypad_pins {
152 pinctrl-single,pins = <
153 0x24c (PIN_OUTPUT | MUX_MODE7) /* gpio5_13.gpio5_13 */
154 0x250 (PIN_OUTPUT | MUX_MODE7) /* spi4_sclk.gpio5_4 */
155 0x254 (PIN_INPUT | MUX_MODE7) /* spi4_d0.gpio5_5 */
156 0x258 (PIN_INPUT | MUX_MODE7) /* spi4_d1.gpio5_5 */
157 >;
158 };
159
160 leds_pins: leds_pins {
161 pinctrl-single,pins = <
162 0x228 (PIN_OUTPUT | MUX_MODE7) /* uart3_rxd.gpio5_2 */
163 0x22c (PIN_OUTPUT | MUX_MODE7) /* uart3_txd.gpio5_3 */
164 0x230 (PIN_OUTPUT | MUX_MODE7) /* uart3_ctsn.gpio5_0 */
165 0x234 (PIN_OUTPUT | MUX_MODE7) /* uart3_rtsn.gpio5_1 */
166 >;
167 };
168
169 i2c0_pins: i2c0_pins {
170 pinctrl-single,pins = <
3cca412e
FB		 171 0x188 (PIN_INPUT | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_sda.i2c0_sda */
172 0x18c (PIN_INPUT | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */
4a45787d
FB		 173 >;
174 };
175
176 i2c1_pins: i2c1_pins {
177 pinctrl-single,pins = <
3cca412e
FB		 178 0x15c (PIN_INPUT | SLEWCTRL_FAST | MUX_MODE2) /* spi0_cs0.i2c1_scl */
179 0x158 (PIN_INPUT | SLEWCTRL_FAST | MUX_MODE2) /* spi0_d1.i2c1_sda */
4a45787d
FB		 180 >;
181 };
182
183 mmc1_pins: pinmux_mmc1_pins {
184 pinctrl-single,pins = <
fb135053
FB		 185 0x0f0 (PIN_INPUT | MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */
186 0x0f4 (PIN_INPUT | MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */
187 0x0f8 (PIN_INPUT | MUX_MODE0) /* mmc0_dat1.mmc0_dat1 */
188 0x0fc (PIN_INPUT | MUX_MODE0) /* mmc0_dat0.mmc0_dat0 */
189 0x100 (PIN_INPUT | MUX_MODE0) /* mmc0_clk.mmc0_clk */
190 0x104 (PIN_INPUT | MUX_MODE0) /* mmc0_cmd.mmc0_cmd */
4a45787d
FB		 191 0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
192 >;
193 };
194
195 ecap0_pins: backlight_pins {
196 pinctrl-single,pins = <
197 0x164 (PIN_OUTPUT | MUX_MODE0) /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out */
198 >;
199 };
200
201 edt_ft5306_ts_pins: edt_ft5306_ts_pins {
202 pinctrl-single,pins = <
203 0x74 (PIN_INPUT | MUX_MODE7) /* gpmc_wpn.gpio0_31 */
204 0x78 (PIN_OUTPUT | MUX_MODE7) /* gpmc_be1n.gpio1_28 */
205 >;
206 };
207
5ccaa6ec
DE		 208 vpfe0_pins_default: vpfe0_pins_default {
209 pinctrl-single,pins = <
210 0x1b0 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_hd mode 0*/
211 0x1b4 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_vd mode 0*/
212 0x1b8 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_field mode 0*/
213 0x1bc (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_wen mode 0*/
214 0x1c0 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_pclk mode 0*/
215 0x1c4 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data8 mode 0*/
216 0x1c8 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data9 mode 0*/
217 0x208 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data0 mode 0*/
218 0x20c (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data1 mode 0*/
219 0x210 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data2 mode 0*/
220 0x214 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data3 mode 0*/
221 0x218 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data4 mode 0*/
222 0x21c (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data5 mode 0*/
223 0x220 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data6 mode 0*/
224 0x224 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data7 mode 0*/
225 >;
226 };
227
228 vpfe0_pins_sleep: vpfe0_pins_sleep {
229 pinctrl-single,pins = <
230 0x1b0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
231 0x1b4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
232 0x1b8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
233 0x1bc (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
234 0x1c0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
235 0x1c4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
236 0x1c8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
237 0x208 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
238 0x20c (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
239 0x210 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
240 0x214 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
241 0x218 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
242 0x21c (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
243 0x220 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
244 0x224 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
245 >;
246 };
247
4a45787d
FB		 248 cpsw_default: cpsw_default {
249 pinctrl-single,pins = <
250 /* Slave 1 */
a2db983a
FB		 251 0x12c (PIN_OUTPUT | MUX_MODE2) /* mii1_txclk.rmii1_tclk */
252 0x114 (PIN_OUTPUT | MUX_MODE2) /* mii1_txen.rgmii1_tctl */
253 0x128 (PIN_OUTPUT | MUX_MODE2) /* mii1_txd0.rgmii1_td0 */
254 0x124 (PIN_OUTPUT | MUX_MODE2) /* mii1_txd1.rgmii1_td1 */
255 0x120 (PIN_OUTPUT | MUX_MODE2) /* mii1_txd0.rgmii1_td2 */
256 0x11c (PIN_OUTPUT | MUX_MODE2) /* mii1_txd1.rgmii1_td3 */
257 0x130 (PIN_INPUT | MUX_MODE2) /* mii1_rxclk.rmii1_rclk */
258 0x118 (PIN_INPUT | MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */
259 0x140 (PIN_INPUT | MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */
260 0x13c (PIN_INPUT | MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */
261 0x138 (PIN_INPUT | MUX_MODE2) /* mii1_rxd0.rgmii1_rd2 */
262 0x134 (PIN_INPUT | MUX_MODE2) /* mii1_rxd1.rgmii1_rd3 */
4a45787d
FB		 263
264 /* Slave 2 */
a2db983a
FB		 265 0x58 (PIN_OUTPUT | MUX_MODE2) /* gpmc_a6.rgmii2_tclk */
266 0x40 (PIN_OUTPUT | MUX_MODE2) /* gpmc_a0.rgmii2_tctl */
267 0x54 (PIN_OUTPUT | MUX_MODE2) /* gpmc_a5.rgmii2_td0 */
268 0x50 (PIN_OUTPUT | MUX_MODE2) /* gpmc_a4.rgmii2_td1 */
269 0x4c (PIN_OUTPUT | MUX_MODE2) /* gpmc_a3.rgmii2_td2 */
270 0x48 (PIN_OUTPUT | MUX_MODE2) /* gpmc_a2.rgmii2_td3 */
271 0x5c (PIN_INPUT | MUX_MODE2) /* gpmc_a7.rgmii2_rclk */
272 0x44 (PIN_INPUT | MUX_MODE2) /* gpmc_a1.rgmii2_rtcl */
273 0x6c (PIN_INPUT | MUX_MODE2) /* gpmc_a11.rgmii2_rd0 */
274 0x68 (PIN_INPUT | MUX_MODE2) /* gpmc_a10.rgmii2_rd1 */
275 0x64 (PIN_INPUT | MUX_MODE2) /* gpmc_a9.rgmii2_rd2 */
276 0x60 (PIN_INPUT | MUX_MODE2) /* gpmc_a8.rgmii2_rd3 */
4a45787d
FB		 277 >;
278 };
279
280 cpsw_sleep: cpsw_sleep {
281 pinctrl-single,pins = <
282 /* Slave 1 reset value */
283 0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7)
284 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
285 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
286 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
287 0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7)
288 0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7)
289 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7)
290 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
291 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
292 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
293 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7)
294 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7)
295
296 /* Slave 2 reset value */
297 0x58 (PIN_INPUT_PULLDOWN | MUX_MODE7)
298 0x40 (PIN_INPUT_PULLDOWN | MUX_MODE7)
299 0x54 (PIN_INPUT_PULLDOWN | MUX_MODE7)
300 0x50 (PIN_INPUT_PULLDOWN | MUX_MODE7)
301 0x4c (PIN_INPUT_PULLDOWN | MUX_MODE7)
302 0x48 (PIN_INPUT_PULLDOWN | MUX_MODE7)
303 0x5c (PIN_INPUT_PULLDOWN | MUX_MODE7)
304 0x44 (PIN_INPUT_PULLDOWN | MUX_MODE7)
305 0x6c (PIN_INPUT_PULLDOWN | MUX_MODE7)
306 0x68 (PIN_INPUT_PULLDOWN | MUX_MODE7)
307 0x64 (PIN_INPUT_PULLDOWN | MUX_MODE7)
308 0x60 (PIN_INPUT_PULLDOWN | MUX_MODE7)
309 >;
310 };
311
312 davinci_mdio_default: davinci_mdio_default {
313 pinctrl-single,pins = <
314 /* MDIO */
a2db983a
FB		 315 0x148 (PIN_INPUT | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
316 0x14c (PIN_OUTPUT | MUX_MODE0) /* mdio_clk.mdio_clk */
4a45787d
FB		 317 >;
318 };
319
320 davinci_mdio_sleep: davinci_mdio_sleep {
321 pinctrl-single,pins = <
322 /* MDIO reset value */
323 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
324 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
325 >;
326 };
327
328 dss_pins: dss_pins {
329 pinctrl-single,pins = <
2d8a28c2
FB		 330 0x020 (PIN_OUTPUT | MUX_MODE1) /* gpmc ad 8 -> DSS DATA 23 */
331 0x024 (PIN_OUTPUT | MUX_MODE1)
332 0x028 (PIN_OUTPUT | MUX_MODE1)
333 0x02c (PIN_OUTPUT | MUX_MODE1)
334 0x030 (PIN_OUTPUT | MUX_MODE1)
335 0x034 (PIN_OUTPUT | MUX_MODE1)
336 0x038 (PIN_OUTPUT | MUX_MODE1)
337 0x03c (PIN_OUTPUT | MUX_MODE1) /* gpmc ad 15 -> DSS DATA 16 */
338 0x0a0 (PIN_OUTPUT | MUX_MODE0) /* DSS DATA 0 */
339 0x0a4 (PIN_OUTPUT | MUX_MODE0)
340 0x0a8 (PIN_OUTPUT | MUX_MODE0)
341 0x0ac (PIN_OUTPUT | MUX_MODE0)
342 0x0b0 (PIN_OUTPUT | MUX_MODE0)
343 0x0b4 (PIN_OUTPUT | MUX_MODE0)
344 0x0b8 (PIN_OUTPUT | MUX_MODE0)
345 0x0bc (PIN_OUTPUT | MUX_MODE0)
346 0x0c0 (PIN_OUTPUT | MUX_MODE0)
347 0x0c4 (PIN_OUTPUT | MUX_MODE0)
348 0x0c8 (PIN_OUTPUT | MUX_MODE0)
349 0x0cc (PIN_OUTPUT | MUX_MODE0)
350 0x0d0 (PIN_OUTPUT | MUX_MODE0)
351 0x0d4 (PIN_OUTPUT | MUX_MODE0)
352 0x0d8 (PIN_OUTPUT | MUX_MODE0)
353 0x0dc (PIN_OUTPUT | MUX_MODE0) /* DSS DATA 15 */
354 0x0e0 (PIN_OUTPUT | MUX_MODE0) /* DSS VSYNC */
355 0x0e4 (PIN_OUTPUT | MUX_MODE0) /* DSS HSYNC */
356 0x0e8 (PIN_OUTPUT | MUX_MODE0) /* DSS PCLK */
357 0x0ec (PIN_OUTPUT | MUX_MODE0) /* DSS AC BIAS EN */
4a45787d
FB		 358
359 >;
360 };
361
362 qspi_pins: qspi_pins {
363 pinctrl-single,pins = <
fad7ca8b
FB		 364 0x7c (PIN_OUTPUT | MUX_MODE3) /* gpmc_csn0.qspi_csn */
365 0x88 (PIN_OUTPUT | MUX_MODE2) /* gpmc_csn3.qspi_clk */
366 0x90 (PIN_INPUT | MUX_MODE3) /* gpmc_advn_ale.qspi_d0 */
367 0x94 (PIN_INPUT | MUX_MODE3) /* gpmc_oen_ren.qspi_d1 */
368 0x98 (PIN_INPUT | MUX_MODE3) /* gpmc_wen.qspi_d2 */
369 0x9c (PIN_INPUT | MUX_MODE3) /* gpmc_be0n_cle.qspi_d3 */
4a45787d
FB		 370 >;
371 };
372
373 mcasp1_pins: mcasp1_pins {
374 pinctrl-single,pins = <
375 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_crs.mcasp1_aclkx */
376 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_rxerr.mcasp1_fsx */
377 0x108 (PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* mii1_col.mcasp1_axr2 */
378 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */
379 >;
380 };
381
7155ace4
PU		 382 mcasp1_pins_sleep: mcasp1_pins_sleep {
383 pinctrl-single,pins = <
384 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE7)
385 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE7)
386 0x108 (PIN_INPUT_PULLDOWN | MUX_MODE7)
387 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE7)
388 >;
389 };
390
4a45787d
FB		 391 lcd_pins: lcd_pins {
392 pinctrl-single,pins = <
58230c2c 393 0x1c (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpcm_ad7.gpio1_7 */
4a45787d
FB		 394 >;
395 };
221fed3c
FB		 396
397 usb1_pins: usb1_pins {
398 pinctrl-single,pins = <
399 0x2c0 (PIN_OUTPUT | MUX_MODE0) /* usb0_drvvbus.usb0_drvvbus */
400 >;
401 };
402
403 usb2_pins: usb2_pins {
404 pinctrl-single,pins = <
405 0x2c4 (PIN_OUTPUT | MUX_MODE0) /* usb0_drvvbus.usb0_drvvbus */
406 >;
407 };
4a45787d
FB		 408};
409
410&i2c0 {
411 status = "okay";
412 pinctrl-names = "default";
413 pinctrl-0 = <&i2c0_pins>;
414 clock-frequency = <400000>;
415
416 tps@24 {
417 compatible = "ti,tps65218";
418 reg = <0x24>;
4a45787d
FB		 419 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
420 interrupt-controller;
421 #interrupt-cells = <2>;
422
423 dcdc1: regulator-dcdc1 {
424 compatible = "ti,tps65218-dcdc1";
425 /* VDD_CORE limits min of OPP50 and max of OPP100 */
426 regulator-name = "vdd_core";
427 regulator-min-microvolt = <912000>;
428 regulator-max-microvolt = <1144000>;
429 regulator-boot-on;
430 regulator-always-on;
431 };
432
433 dcdc2: regulator-dcdc2 {
434 compatible = "ti,tps65218-dcdc2";
435 /* VDD_MPU limits min of OPP50 and max of OPP_NITRO */
436 regulator-name = "vdd_mpu";
437 regulator-min-microvolt = <912000>;
438 regulator-max-microvolt = <1378000>;
439 regulator-boot-on;
440 regulator-always-on;
441 };
442
443 dcdc3: regulator-dcdc3 {
444 compatible = "ti,tps65218-dcdc3";
445 regulator-name = "vdds_ddr";
5cd98a7a
K		 446 regulator-min-microvolt = <1500000>;
447 regulator-max-microvolt = <1500000>;
4a45787d
FB		 448 regulator-boot-on;
449 regulator-always-on;
450 };
451
452 dcdc4: regulator-dcdc4 {
453 compatible = "ti,tps65218-dcdc4";
454 regulator-name = "v3_3d";
455 regulator-min-microvolt = <3300000>;
456 regulator-max-microvolt = <3300000>;
457 regulator-boot-on;
458 regulator-always-on;
459 };
460
461 ldo1: regulator-ldo1 {
462 compatible = "ti,tps65218-ldo1";
463 regulator-name = "v1_8d";
464 regulator-min-microvolt = <1800000>;
465 regulator-max-microvolt = <1800000>;
466 regulator-boot-on;
467 regulator-always-on;
468 };
469
bb1c5fe1
FB		 470 power-button {
471 compatible = "ti,tps65218-pwrbutton";
472 status = "okay";
473 interrupts = <3 IRQ_TYPE_EDGE_BOTH>;
474 };
4a45787d
FB		 475 };
476
477 at24@50 {
478 compatible = "at24,24c256";
479 pagesize = <64>;
480 reg = <0x50>;
481 };
482};
483
484&i2c1 {
485 status = "okay";
486 pinctrl-names = "default";
487 pinctrl-0 = <&i2c1_pins>;
488 clock-frequency = <400000>;
489
490 edt-ft5306@38 {
491 status = "okay";
492 compatible = "edt,edt-ft5306", "edt,edt-ft5x06";
493 pinctrl-names = "default";
494 pinctrl-0 = <&edt_ft5306_ts_pins>;
495
496 reg = <0x38>;
497 interrupt-parent = <&gpio0>;
498 interrupts = <31 0>;
499
faa4ec1e 500 reset-gpios = <&gpio1 28 GPIO_ACTIVE_LOW>;
4a45787d
FB		 501
502 touchscreen-size-x = <480>;
503 touchscreen-size-y = <272>;
504 };
505
506 tlv320aic3106: tlv320aic3106@1b {
20746c50 507 #sound-dai-cells = <0>;
4a45787d
FB		 508 compatible = "ti,tlv320aic3106";
509 reg = <0x1b>;
510 status = "okay";
511
512 /* Regulators */
513 AVDD-supply = <&dcdc4>;
514 IOVDD-supply = <&dcdc4>;
515 DRVDD-supply = <&dcdc4>;
516 DVDD-supply = <&ldo1>;
517 };
518
519 lis331dlh@18 {
520 compatible = "st,lis331dlh";
521 reg = <0x18>;
522 status = "okay";
523
524 Vdd-supply = <&dcdc4>;
525 Vdd_IO-supply = <&dcdc4>;
526 interrupts-extended = <&gpio1 6 0>, <&gpio2 1 0>;
527 };
528};
529
530&epwmss0 {
531 status = "okay";
532};
533
534&ecap0 {
535 status = "okay";
536 pinctrl-names = "default";
537 pinctrl-0 = <&ecap0_pins>;
538};
539
540&gpio0 {
541 status = "okay";
542};
543
544&gpio1 {
545 status = "okay";
546};
547
548&gpio5 {
549 status = "okay";
550};
551
552&mmc1 {
553 status = "okay";
554 pinctrl-names = "default";
555 pinctrl-0 = <&mmc1_pins>;
556
557 vmmc-supply = <&dcdc4>;
558 bus-width = <4>;
559 cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
560};
561
562&usb2_phy1 {
563 status = "okay";
564};
565
566&usb1 {
567 dr_mode = "peripheral";
568 status = "okay";
221fed3c
FB		 569 pinctrl-names = "default";
570 pinctrl-0 = <&usb1_pins>;
4a45787d
FB		 571};
572
573&usb2_phy2 {
574 status = "okay";
575};
576
577&usb2 {
578 dr_mode = "host";
579 status = "okay";
221fed3c
FB		 580 pinctrl-names = "default";
581 pinctrl-0 = <&usb2_pins>;
4a45787d
FB		 582};
583
584&qspi {
585 status = "okay";
586 pinctrl-names = "default";
587 pinctrl-0 = <&qspi_pins>;
588
589 spi-max-frequency = <48000000>;
590 m25p80@0 {
591 compatible = "mx66l51235l";
592 spi-max-frequency = <48000000>;
593 reg = <0>;
594 spi-cpol;
595 spi-cpha;
596 spi-tx-bus-width = <1>;
597 spi-rx-bus-width = <4>;
598 #address-cells = <1>;
599 #size-cells = <1>;
600
601 /* MTD partition table.
602 * The ROM checks the first 512KiB
603 * for a valid file to boot(XIP).
604 */
605 partition@0 {
606 label = "QSPI.U_BOOT";
607 reg = <0x00000000 0x000080000>;
608 };
609 partition@1 {
610 label = "QSPI.U_BOOT.backup";
611 reg = <0x00080000 0x00080000>;
612 };
613 partition@2 {
614 label = "QSPI.U-BOOT-SPL_OS";
615 reg = <0x00100000 0x00010000>;
616 };
617 partition@3 {
618 label = "QSPI.U_BOOT_ENV";
619 reg = <0x00110000 0x00010000>;
620 };
621 partition@4 {
622 label = "QSPI.U-BOOT-ENV.backup";
623 reg = <0x00120000 0x00010000>;
624 };
625 partition@5 {
626 label = "QSPI.KERNEL";
627 reg = <0x00130000 0x0800000>;
628 };
629 partition@6 {
630 label = "QSPI.FILESYSTEM";
631 reg = <0x00930000 0x36D0000>;
632 };
633 };
634};
635
636&mac {
637 pinctrl-names = "default", "sleep";
638 pinctrl-0 = <&cpsw_default>;
639 pinctrl-1 = <&cpsw_sleep>;
640 dual_emac = <1>;
641 status = "okay";
642};
643
644&davinci_mdio {
645 pinctrl-names = "default", "sleep";
646 pinctrl-0 = <&davinci_mdio_default>;
647 pinctrl-1 = <&davinci_mdio_sleep>;
648 status = "okay";
649};
650
651&cpsw_emac0 {
652 phy_id = <&davinci_mdio>, <4>;
653 phy-mode = "rgmii";
654 dual_emac_res_vlan = <1>;
655};
656
657&cpsw_emac1 {
658 phy_id = <&davinci_mdio>, <5>;
659 phy-mode = "rgmii";
660 dual_emac_res_vlan = <2>;
661};
662
663&elm {
664 status = "okay";
665};
666
667&mcasp1 {
20746c50 668 #sound-dai-cells = <0>;
7155ace4 669 pinctrl-names = "default", "sleep";
4a45787d 670 pinctrl-0 = <&mcasp1_pins>;
7155ace4 671 pinctrl-1 = <&mcasp1_pins_sleep>;
4a45787d
FB		 672
673 status = "okay";
674
675 op-mode = <0>;
676 tdm-slots = <2>;
677 serial-dir = <
678 0 0 1 2
679 >;
680
681 tx-num-evt = <1>;
682 rx-num-evt = <1>;
683};
684
685&dss {
686 status = "okay";
687
688 pinctrl-names = "default";
689 pinctrl-0 = <&dss_pins>;
690
691 port {
692 dpi_out: endpoint@0 {
693 remote-endpoint = <&lcd_in>;
694 data-lines = <24>;
695 };
696 };
697};
698
699&rtc {
700 status = "okay";
701};
702
703&wdt {
704 status = "okay";
705};
3e1fe451
DG		 706
707&cpu {
708 cpu0-supply = <&dcdc2>;
709};
5ccaa6ec
DE		 710
711&vpfe0 {
712 status = "okay";
713 pinctrl-names = "default", "sleep";
714 pinctrl-0 = <&vpfe0_pins_default>;
715 pinctrl-1 = <&vpfe0_pins_sleep>;
716
717 /* Camera port */
718 port {
719 vpfe0_ep: endpoint {
720 /* remote-endpoint = <&sensor>; add once we have it */
721 ti,am437x-vpfe-interface = <0>;
722 bus-width = <8>;
723 hsync-active = <0>;
724 vsync-active = <0>;
725 };
726 };
727};
Linux kernel - Deliverables
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