projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 6a679208 TK |
1 | /* |
| 2 | * Device Tree Source for AM43xx clock data | |
| 3 | * | |
| 4 | * Copyright (C) 2013 Texas Instruments, Inc. | |
| 5 | * | |
| 6 | * This program is free software; you can redistribute it and/or modify | |
| 7 | * it under the terms of the GNU General Public License version 2 as | |
| 8 | * published by the Free Software Foundation. | |
| 9 | */ | |
| 83a5d6c9 | 10 | &scm_clocks { |
| c5670481 | 11 | sys_clkin_ck: sys_clkin_ck@40 { |
| f7c66b71 AM |
12 | #clock-cells = <0>; |
| 13 | compatible = "ti,mux-clock"; | |
| 14 | clocks = <&sysboot_freq_sel_ck>, <&crystal_freq_sel_ck>; | |
| 15 | ti,bit-shift = <31>; | |
| 16 | reg = <0x0040>; | |
| 17 | }; | |
| 18 | ||
| c5670481 | 19 | crystal_freq_sel_ck: crystal_freq_sel_ck@40 { |
| f7c66b71 AM |
20 | #clock-cells = <0>; |
| 21 | compatible = "ti,mux-clock"; | |
| 22 | clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>; | |
| 23 | ti,bit-shift = <29>; | |
| 24 | reg = <0x0040>; | |
| 25 | }; | |
| 26 | ||
| 27 | sysboot_freq_sel_ck: sysboot_freq_sel_ck@44e10040 { | |
| 6a679208 TK |
28 | #clock-cells = <0>; |
| 29 | compatible = "ti,mux-clock"; | |
| 30 | clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>; | |
| 31 | ti,bit-shift = <22>; | |
| 32 | reg = <0x0040>; | |
| 33 | }; | |
| 34 | ||
| 35 | adc_tsc_fck: adc_tsc_fck { | |
| 36 | #clock-cells = <0>; | |
| 37 | compatible = "fixed-factor-clock"; | |
| 38 | clocks = <&sys_clkin_ck>; | |
| 39 | clock-mult = <1>; | |
| 40 | clock-div = <1>; | |
| 41 | }; | |
| 42 | ||
| 43 | dcan0_fck: dcan0_fck { | |
| 44 | #clock-cells = <0>; | |
| 45 | compatible = "fixed-factor-clock"; | |
| 46 | clocks = <&sys_clkin_ck>; | |
| 47 | clock-mult = <1>; | |
| 48 | clock-div = <1>; | |
| 49 | }; | |
| 50 | ||
| 51 | dcan1_fck: dcan1_fck { | |
| 52 | #clock-cells = <0>; | |
| 53 | compatible = "fixed-factor-clock"; | |
| 54 | clocks = <&sys_clkin_ck>; | |
| 55 | clock-mult = <1>; | |
| 56 | clock-div = <1>; | |
| 57 | }; | |
| 58 | ||
| 59 | mcasp0_fck: mcasp0_fck { | |
| 60 | #clock-cells = <0>; | |
| 61 | compatible = "fixed-factor-clock"; | |
| 62 | clocks = <&sys_clkin_ck>; | |
| 63 | clock-mult = <1>; | |
| 64 | clock-div = <1>; | |
| 65 | }; | |
| 66 | ||
| 67 | mcasp1_fck: mcasp1_fck { | |
| 68 | #clock-cells = <0>; | |
| 69 | compatible = "fixed-factor-clock"; | |
| 70 | clocks = <&sys_clkin_ck>; | |
| 71 | clock-mult = <1>; | |
| 72 | clock-div = <1>; | |
| 73 | }; | |
| 74 | ||
| 75 | smartreflex0_fck: smartreflex0_fck { | |
| 76 | #clock-cells = <0>; | |
| 77 | compatible = "fixed-factor-clock"; | |
| 78 | clocks = <&sys_clkin_ck>; | |
| 79 | clock-mult = <1>; | |
| 80 | clock-div = <1>; | |
| 81 | }; | |
| 82 | ||
| 83 | smartreflex1_fck: smartreflex1_fck { | |
| 84 | #clock-cells = <0>; | |
| 85 | compatible = "fixed-factor-clock"; | |
| 86 | clocks = <&sys_clkin_ck>; | |
| 87 | clock-mult = <1>; | |
| 88 | clock-div = <1>; | |
| 89 | }; | |
| 90 | ||
| 91 | sha0_fck: sha0_fck { | |
| 92 | #clock-cells = <0>; | |
| 93 | compatible = "fixed-factor-clock"; | |
| 94 | clocks = <&sys_clkin_ck>; | |
| 95 | clock-mult = <1>; | |
| 96 | clock-div = <1>; | |
| 97 | }; | |
| 98 | ||
| 99 | aes0_fck: aes0_fck { | |
| 100 | #clock-cells = <0>; | |
| 101 | compatible = "fixed-factor-clock"; | |
| 102 | clocks = <&sys_clkin_ck>; | |
| 103 | clock-mult = <1>; | |
| 104 | clock-div = <1>; | |
| 105 | }; | |
| 4da1c677 | 106 | |
| c5670481 | 107 | ehrpwm0_tbclk: ehrpwm0_tbclk@664 { |
| 4da1c677 PS |
108 | #clock-cells = <0>; |
| 109 | compatible = "ti,gate-clock"; | |
| 7d53d255 | 110 | clocks = <&l4ls_gclk>; |
| 4da1c677 PS |
111 | ti,bit-shift = <0>; |
| 112 | reg = <0x0664>; | |
| 113 | }; | |
| 114 | ||
| c5670481 | 115 | ehrpwm1_tbclk: ehrpwm1_tbclk@664 { |
| 4da1c677 PS |
116 | #clock-cells = <0>; |
| 117 | compatible = "ti,gate-clock"; | |
| 7d53d255 | 118 | clocks = <&l4ls_gclk>; |
| 4da1c677 PS |
119 | ti,bit-shift = <1>; |
| 120 | reg = <0x0664>; | |
| 121 | }; | |
| 122 | ||
| c5670481 | 123 | ehrpwm2_tbclk: ehrpwm2_tbclk@664 { |
| 4da1c677 PS |
124 | #clock-cells = <0>; |
| 125 | compatible = "ti,gate-clock"; | |
| 7d53d255 | 126 | clocks = <&l4ls_gclk>; |
| 4da1c677 PS |
127 | ti,bit-shift = <2>; |
| 128 | reg = <0x0664>; | |
| 129 | }; | |
| 130 | ||
| c5670481 | 131 | ehrpwm3_tbclk: ehrpwm3_tbclk@664 { |
| 4da1c677 PS |
132 | #clock-cells = <0>; |
| 133 | compatible = "ti,gate-clock"; | |
| 7d53d255 | 134 | clocks = <&l4ls_gclk>; |
| 4da1c677 PS |
135 | ti,bit-shift = <4>; |
| 136 | reg = <0x0664>; | |
| 137 | }; | |
| 138 | ||
| c5670481 | 139 | ehrpwm4_tbclk: ehrpwm4_tbclk@664 { |
| 4da1c677 PS |
140 | #clock-cells = <0>; |
| 141 | compatible = "ti,gate-clock"; | |
| 7d53d255 | 142 | clocks = <&l4ls_gclk>; |
| 4da1c677 PS |
143 | ti,bit-shift = <5>; |
| 144 | reg = <0x0664>; | |
| 145 | }; | |
| 146 | ||
| c5670481 | 147 | ehrpwm5_tbclk: ehrpwm5_tbclk@664 { |
| 4da1c677 PS |
148 | #clock-cells = <0>; |
| 149 | compatible = "ti,gate-clock"; | |
| 7d53d255 | 150 | clocks = <&l4ls_gclk>; |
| 4da1c677 PS |
151 | ti,bit-shift = <6>; |
| 152 | reg = <0x0664>; | |
| 153 | }; | |
| 6a679208 TK |
154 | }; |
| 155 | &prcm_clocks { | |
| 156 | clk_32768_ck: clk_32768_ck { | |
| 157 | #clock-cells = <0>; | |
| 158 | compatible = "fixed-clock"; | |
| 159 | clock-frequency = <32768>; | |
| 160 | }; | |
| 161 | ||
| 162 | clk_rc32k_ck: clk_rc32k_ck { | |
| 163 | #clock-cells = <0>; | |
| 164 | compatible = "fixed-clock"; | |
| 165 | clock-frequency = <32768>; | |
| 166 | }; | |
| 167 | ||
| 168 | virt_19200000_ck: virt_19200000_ck { | |
| 169 | #clock-cells = <0>; | |
| 170 | compatible = "fixed-clock"; | |
| 171 | clock-frequency = <19200000>; | |
| 172 | }; | |
| 173 | ||
| 174 | virt_24000000_ck: virt_24000000_ck { | |
| 175 | #clock-cells = <0>; | |
| 176 | compatible = "fixed-clock"; | |
| 177 | clock-frequency = <24000000>; | |
| 178 | }; | |
| 179 | ||
| 180 | virt_25000000_ck: virt_25000000_ck { | |
| 181 | #clock-cells = <0>; | |
| 182 | compatible = "fixed-clock"; | |
| 183 | clock-frequency = <25000000>; | |
| 184 | }; | |
| 185 | ||
| 186 | virt_26000000_ck: virt_26000000_ck { | |
| 187 | #clock-cells = <0>; | |
| 188 | compatible = "fixed-clock"; | |
| 189 | clock-frequency = <26000000>; | |
| 190 | }; | |
| 191 | ||
| 192 | tclkin_ck: tclkin_ck { | |
| 193 | #clock-cells = <0>; | |
| 194 | compatible = "fixed-clock"; | |
| 195 | clock-frequency = <26000000>; | |
| 196 | }; | |
| 197 | ||
| c5670481 | 198 | dpll_core_ck: dpll_core_ck@2d20 { |
| 6a679208 TK |
199 | #clock-cells = <0>; |
| 200 | compatible = "ti,am3-dpll-core-clock"; | |
| 201 | clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; | |
| 202 | reg = <0x2d20>, <0x2d24>, <0x2d2c>; | |
| 203 | }; | |
| 204 | ||
| 205 | dpll_core_x2_ck: dpll_core_x2_ck { | |
| 206 | #clock-cells = <0>; | |
| 207 | compatible = "ti,am3-dpll-x2-clock"; | |
| 208 | clocks = <&dpll_core_ck>; | |
| 209 | }; | |
| 210 | ||
| c5670481 | 211 | dpll_core_m4_ck: dpll_core_m4_ck@2d38 { |
| 6a679208 TK |
212 | #clock-cells = <0>; |
| 213 | compatible = "ti,divider-clock"; | |
| 214 | clocks = <&dpll_core_x2_ck>; | |
| 215 | ti,max-div = <31>; | |
| 216 | ti,autoidle-shift = <8>; | |
| 217 | reg = <0x2d38>; | |
| 218 | ti,index-starts-at-one; | |
| 219 | ti,invert-autoidle-bit; | |
| 220 | }; | |
| 221 | ||
| c5670481 | 222 | dpll_core_m5_ck: dpll_core_m5_ck@2d3c { |
| 6a679208 TK |
223 | #clock-cells = <0>; |
| 224 | compatible = "ti,divider-clock"; | |
| 225 | clocks = <&dpll_core_x2_ck>; | |
| 226 | ti,max-div = <31>; | |
| 227 | ti,autoidle-shift = <8>; | |
| 228 | reg = <0x2d3c>; | |
| 229 | ti,index-starts-at-one; | |
| 230 | ti,invert-autoidle-bit; | |
| 231 | }; | |
| 232 | ||
| c5670481 | 233 | dpll_core_m6_ck: dpll_core_m6_ck@2d40 { |
| 6a679208 TK |
234 | #clock-cells = <0>; |
| 235 | compatible = "ti,divider-clock"; | |
| 236 | clocks = <&dpll_core_x2_ck>; | |
| 237 | ti,max-div = <31>; | |
| 238 | ti,autoidle-shift = <8>; | |
| 239 | reg = <0x2d40>; | |
| 240 | ti,index-starts-at-one; | |
| 241 | ti,invert-autoidle-bit; | |
| 242 | }; | |
| 243 | ||
| c5670481 | 244 | dpll_mpu_ck: dpll_mpu_ck@2d60 { |
| 6a679208 TK |
245 | #clock-cells = <0>; |
| 246 | compatible = "ti,am3-dpll-clock"; | |
| 247 | clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; | |
| 248 | reg = <0x2d60>, <0x2d64>, <0x2d6c>; | |
| 249 | }; | |
| 250 | ||
| c5670481 | 251 | dpll_mpu_m2_ck: dpll_mpu_m2_ck@2d70 { |
| 6a679208 TK |
252 | #clock-cells = <0>; |
| 253 | compatible = "ti,divider-clock"; | |
| 254 | clocks = <&dpll_mpu_ck>; | |
| 255 | ti,max-div = <31>; | |
| 256 | ti,autoidle-shift = <8>; | |
| 257 | reg = <0x2d70>; | |
| 258 | ti,index-starts-at-one; | |
| 259 | ti,invert-autoidle-bit; | |
| 260 | }; | |
| 261 | ||
| 14054fb1 GS |
262 | mpu_periphclk: mpu_periphclk { |
| 263 | #clock-cells = <0>; | |
| 264 | compatible = "fixed-factor-clock"; | |
| 265 | clocks = <&dpll_mpu_m2_ck>; | |
| 266 | clock-mult = <1>; | |
| 267 | clock-div = <2>; | |
| 268 | }; | |
| 269 | ||
| c5670481 | 270 | dpll_ddr_ck: dpll_ddr_ck@2da0 { |
| 6a679208 TK |
271 | #clock-cells = <0>; |
| 272 | compatible = "ti,am3-dpll-clock"; | |
| 273 | clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; | |
| 274 | reg = <0x2da0>, <0x2da4>, <0x2dac>; | |
| 275 | }; | |
| 276 | ||
| c5670481 | 277 | dpll_ddr_m2_ck: dpll_ddr_m2_ck@2db0 { |
| 6a679208 TK |
278 | #clock-cells = <0>; |
| 279 | compatible = "ti,divider-clock"; | |
| 280 | clocks = <&dpll_ddr_ck>; | |
| 281 | ti,max-div = <31>; | |
| 282 | ti,autoidle-shift = <8>; | |
| 283 | reg = <0x2db0>; | |
| 284 | ti,index-starts-at-one; | |
| 285 | ti,invert-autoidle-bit; | |
| 286 | }; | |
| 287 | ||
| c5670481 | 288 | dpll_disp_ck: dpll_disp_ck@2e20 { |
| 6a679208 TK |
289 | #clock-cells = <0>; |
| 290 | compatible = "ti,am3-dpll-clock"; | |
| 291 | clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; | |
| 292 | reg = <0x2e20>, <0x2e24>, <0x2e2c>; | |
| 293 | }; | |
| 294 | ||
| c5670481 | 295 | dpll_disp_m2_ck: dpll_disp_m2_ck@2e30 { |
| 6a679208 TK |
296 | #clock-cells = <0>; |
| 297 | compatible = "ti,divider-clock"; | |
| 298 | clocks = <&dpll_disp_ck>; | |
| 299 | ti,max-div = <31>; | |
| 300 | ti,autoidle-shift = <8>; | |
| 301 | reg = <0x2e30>; | |
| 302 | ti,index-starts-at-one; | |
| 303 | ti,invert-autoidle-bit; | |
| 10a6e183 | 304 | ti,set-rate-parent; |
| 6a679208 TK |
305 | }; |
| 306 | ||
| c5670481 | 307 | dpll_per_ck: dpll_per_ck@2de0 { |
| 6a679208 TK |
308 | #clock-cells = <0>; |
| 309 | compatible = "ti,am3-dpll-j-type-clock"; | |
| 310 | clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; | |
| 311 | reg = <0x2de0>, <0x2de4>, <0x2dec>; | |
| 312 | }; | |
| 313 | ||
| c5670481 | 314 | dpll_per_m2_ck: dpll_per_m2_ck@2df0 { |
| 6a679208 TK |
315 | #clock-cells = <0>; |
| 316 | compatible = "ti,divider-clock"; | |
| 317 | clocks = <&dpll_per_ck>; | |
| 318 | ti,max-div = <127>; | |
| 319 | ti,autoidle-shift = <8>; | |
| 320 | reg = <0x2df0>; | |
| 321 | ti,index-starts-at-one; | |
| 322 | ti,invert-autoidle-bit; | |
| 323 | }; | |
| 324 | ||
| 325 | dpll_per_m2_div4_wkupdm_ck: dpll_per_m2_div4_wkupdm_ck { | |
| 326 | #clock-cells = <0>; | |
| 327 | compatible = "fixed-factor-clock"; | |
| 328 | clocks = <&dpll_per_m2_ck>; | |
| 329 | clock-mult = <1>; | |
| 330 | clock-div = <4>; | |
| 331 | }; | |
| 332 | ||
| 333 | dpll_per_m2_div4_ck: dpll_per_m2_div4_ck { | |
| 334 | #clock-cells = <0>; | |
| 335 | compatible = "fixed-factor-clock"; | |
| 336 | clocks = <&dpll_per_m2_ck>; | |
| 337 | clock-mult = <1>; | |
| 338 | clock-div = <4>; | |
| 339 | }; | |
| 340 | ||
| 341 | clk_24mhz: clk_24mhz { | |
| 342 | #clock-cells = <0>; | |
| 343 | compatible = "fixed-factor-clock"; | |
| 344 | clocks = <&dpll_per_m2_ck>; | |
| 345 | clock-mult = <1>; | |
| 346 | clock-div = <8>; | |
| 347 | }; | |
| 348 | ||
| 349 | clkdiv32k_ck: clkdiv32k_ck { | |
| 350 | #clock-cells = <0>; | |
| 351 | compatible = "fixed-factor-clock"; | |
| 352 | clocks = <&clk_24mhz>; | |
| 353 | clock-mult = <1>; | |
| 354 | clock-div = <732>; | |
| 355 | }; | |
| 356 | ||
| c5670481 | 357 | clkdiv32k_ick: clkdiv32k_ick@2a38 { |
| 6a679208 TK |
358 | #clock-cells = <0>; |
| 359 | compatible = "ti,gate-clock"; | |
| 360 | clocks = <&clkdiv32k_ck>; | |
| 361 | ti,bit-shift = <8>; | |
| 362 | reg = <0x2a38>; | |
| 363 | }; | |
| 364 | ||
| 365 | sysclk_div: sysclk_div { | |
| 366 | #clock-cells = <0>; | |
| 367 | compatible = "fixed-factor-clock"; | |
| 368 | clocks = <&dpll_core_m4_ck>; | |
| 369 | clock-mult = <1>; | |
| 370 | clock-div = <1>; | |
| 371 | }; | |
| 372 | ||
| c5670481 | 373 | pruss_ocp_gclk: pruss_ocp_gclk@4248 { |
| 6a679208 TK |
374 | #clock-cells = <0>; |
| 375 | compatible = "ti,mux-clock"; | |
| 376 | clocks = <&sysclk_div>, <&dpll_disp_m2_ck>; | |
| 377 | reg = <0x4248>; | |
| 378 | }; | |
| 379 | ||
| 380 | clk_32k_tpm_ck: clk_32k_tpm_ck { | |
| 381 | #clock-cells = <0>; | |
| 382 | compatible = "fixed-clock"; | |
| 383 | clock-frequency = <32768>; | |
| 384 | }; | |
| 385 | ||
| c5670481 | 386 | timer1_fck: timer1_fck@4200 { |
| 6a679208 TK |
387 | #clock-cells = <0>; |
| 388 | compatible = "ti,mux-clock"; | |
| 389 | clocks = <&sys_clkin_ck>, <&clkdiv32k_ick>, <&tclkin_ck>, <&clk_rc32k_ck>, <&clk_32768_ck>, <&clk_32k_tpm_ck>; | |
| 390 | reg = <0x4200>; | |
| 391 | }; | |
| 392 | ||
| c5670481 | 393 | timer2_fck: timer2_fck@4204 { |
| 6a679208 TK |
394 | #clock-cells = <0>; |
| 395 | compatible = "ti,mux-clock"; | |
| 396 | clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; | |
| 397 | reg = <0x4204>; | |
| 398 | }; | |
| 399 | ||
| c5670481 | 400 | timer3_fck: timer3_fck@4208 { |
| 6a679208 TK |
401 | #clock-cells = <0>; |
| 402 | compatible = "ti,mux-clock"; | |
| 403 | clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; | |
| 404 | reg = <0x4208>; | |
| 405 | }; | |
| 406 | ||
| c5670481 | 407 | timer4_fck: timer4_fck@420c { |
| 6a679208 TK |
408 | #clock-cells = <0>; |
| 409 | compatible = "ti,mux-clock"; | |
| 410 | clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; | |
| 411 | reg = <0x420c>; | |
| 412 | }; | |
| 413 | ||
| c5670481 | 414 | timer5_fck: timer5_fck@4210 { |
| 6a679208 TK |
415 | #clock-cells = <0>; |
| 416 | compatible = "ti,mux-clock"; | |
| 417 | clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; | |
| 418 | reg = <0x4210>; | |
| 419 | }; | |
| 420 | ||
| c5670481 | 421 | timer6_fck: timer6_fck@4214 { |
| 6a679208 TK |
422 | #clock-cells = <0>; |
| 423 | compatible = "ti,mux-clock"; | |
| 424 | clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; | |
| 425 | reg = <0x4214>; | |
| 426 | }; | |
| 427 | ||
| c5670481 | 428 | timer7_fck: timer7_fck@4218 { |
| 6a679208 TK |
429 | #clock-cells = <0>; |
| 430 | compatible = "ti,mux-clock"; | |
| 431 | clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; | |
| 432 | reg = <0x4218>; | |
| 433 | }; | |
| 434 | ||
| c5670481 | 435 | wdt1_fck: wdt1_fck@422c { |
| 6a679208 TK |
436 | #clock-cells = <0>; |
| 437 | compatible = "ti,mux-clock"; | |
| 438 | clocks = <&clk_rc32k_ck>, <&clkdiv32k_ick>; | |
| 439 | reg = <0x422c>; | |
| 440 | }; | |
| 441 | ||
| 442 | l3_gclk: l3_gclk { | |
| 443 | #clock-cells = <0>; | |
| 444 | compatible = "fixed-factor-clock"; | |
| 445 | clocks = <&dpll_core_m4_ck>; | |
| 446 | clock-mult = <1>; | |
| 447 | clock-div = <1>; | |
| 448 | }; | |
| 449 | ||
| 450 | dpll_core_m4_div2_ck: dpll_core_m4_div2_ck { | |
| 451 | #clock-cells = <0>; | |
| 452 | compatible = "fixed-factor-clock"; | |
| 453 | clocks = <&sysclk_div>; | |
| 454 | clock-mult = <1>; | |
| 455 | clock-div = <2>; | |
| 456 | }; | |
| 457 | ||
| 458 | l4hs_gclk: l4hs_gclk { | |
| 459 | #clock-cells = <0>; | |
| 460 | compatible = "fixed-factor-clock"; | |
| 461 | clocks = <&dpll_core_m4_ck>; | |
| 462 | clock-mult = <1>; | |
| 463 | clock-div = <1>; | |
| 464 | }; | |
| 465 | ||
| 466 | l3s_gclk: l3s_gclk { | |
| 467 | #clock-cells = <0>; | |
| 468 | compatible = "fixed-factor-clock"; | |
| 469 | clocks = <&dpll_core_m4_div2_ck>; | |
| 470 | clock-mult = <1>; | |
| 471 | clock-div = <1>; | |
| 472 | }; | |
| 473 | ||
| 474 | l4ls_gclk: l4ls_gclk { | |
| 475 | #clock-cells = <0>; | |
| 476 | compatible = "fixed-factor-clock"; | |
| 477 | clocks = <&dpll_core_m4_div2_ck>; | |
| 478 | clock-mult = <1>; | |
| 479 | clock-div = <1>; | |
| 480 | }; | |
| 481 | ||
| 482 | cpsw_125mhz_gclk: cpsw_125mhz_gclk { | |
| 483 | #clock-cells = <0>; | |
| 484 | compatible = "fixed-factor-clock"; | |
| 485 | clocks = <&dpll_core_m5_ck>; | |
| 486 | clock-mult = <1>; | |
| 487 | clock-div = <2>; | |
| 488 | }; | |
| 489 | ||
| c5670481 | 490 | cpsw_cpts_rft_clk: cpsw_cpts_rft_clk@4238 { |
| 6a679208 TK |
491 | #clock-cells = <0>; |
| 492 | compatible = "ti,mux-clock"; | |
| 493 | clocks = <&sysclk_div>, <&dpll_core_m5_ck>, <&dpll_disp_m2_ck>; | |
| 494 | reg = <0x4238>; | |
| 495 | }; | |
| 496 | ||
| c5670481 | 497 | dpll_clksel_mac_clk: dpll_clksel_mac_clk@4234 { |
| 93c03a2c K |
498 | #clock-cells = <0>; |
| 499 | compatible = "ti,divider-clock"; | |
| 500 | clocks = <&dpll_core_m5_ck>; | |
| 501 | reg = <0x4234>; | |
| 502 | ti,bit-shift = <2>; | |
| 503 | ti,dividers = <2>, <5>; | |
| 504 | }; | |
| 505 | ||
| 6a679208 TK |
506 | clk_32k_mosc_ck: clk_32k_mosc_ck { |
| 507 | #clock-cells = <0>; | |
| 508 | compatible = "fixed-clock"; | |
| 509 | clock-frequency = <32768>; | |
| 510 | }; | |
| 511 | ||
| c5670481 | 512 | gpio0_dbclk_mux_ck: gpio0_dbclk_mux_ck@4240 { |
| 6a679208 TK |
513 | #clock-cells = <0>; |
| 514 | compatible = "ti,mux-clock"; | |
| 515 | clocks = <&clk_rc32k_ck>, <&clk_32768_ck>, <&clkdiv32k_ick>, <&clk_32k_mosc_ck>, <&clk_32k_tpm_ck>; | |
| 516 | reg = <0x4240>; | |
| 517 | }; | |
| 518 | ||
| c5670481 | 519 | gpio0_dbclk: gpio0_dbclk@2b68 { |
| 6a679208 TK |
520 | #clock-cells = <0>; |
| 521 | compatible = "ti,gate-clock"; | |
| 522 | clocks = <&gpio0_dbclk_mux_ck>; | |
| 523 | ti,bit-shift = <8>; | |
| 524 | reg = <0x2b68>; | |
| 525 | }; | |
| 526 | ||
| c5670481 | 527 | gpio1_dbclk: gpio1_dbclk@8c78 { |
| 6a679208 TK |
528 | #clock-cells = <0>; |
| 529 | compatible = "ti,gate-clock"; | |
| 530 | clocks = <&clkdiv32k_ick>; | |
| 531 | ti,bit-shift = <8>; | |
| 532 | reg = <0x8c78>; | |
| 533 | }; | |
| 534 | ||
| c5670481 | 535 | gpio2_dbclk: gpio2_dbclk@8c80 { |
| 6a679208 TK |
536 | #clock-cells = <0>; |
| 537 | compatible = "ti,gate-clock"; | |
| 538 | clocks = <&clkdiv32k_ick>; | |
| 539 | ti,bit-shift = <8>; | |
| 540 | reg = <0x8c80>; | |
| 541 | }; | |
| 542 | ||
| c5670481 | 543 | gpio3_dbclk: gpio3_dbclk@8c88 { |
| 6a679208 TK |
544 | #clock-cells = <0>; |
| 545 | compatible = "ti,gate-clock"; | |
| 546 | clocks = <&clkdiv32k_ick>; | |
| 547 | ti,bit-shift = <8>; | |
| 548 | reg = <0x8c88>; | |
| 549 | }; | |
| 550 | ||
| c5670481 | 551 | gpio4_dbclk: gpio4_dbclk@8c90 { |
| 6a679208 TK |
552 | #clock-cells = <0>; |
| 553 | compatible = "ti,gate-clock"; | |
| 554 | clocks = <&clkdiv32k_ick>; | |
| 555 | ti,bit-shift = <8>; | |
| 556 | reg = <0x8c90>; | |
| 557 | }; | |
| 558 | ||
| c5670481 | 559 | gpio5_dbclk: gpio5_dbclk@8c98 { |
| 6a679208 TK |
560 | #clock-cells = <0>; |
| 561 | compatible = "ti,gate-clock"; | |
| 562 | clocks = <&clkdiv32k_ick>; | |
| 563 | ti,bit-shift = <8>; | |
| 564 | reg = <0x8c98>; | |
| 565 | }; | |
| 566 | ||
| 567 | mmc_clk: mmc_clk { | |
| 568 | #clock-cells = <0>; | |
| 569 | compatible = "fixed-factor-clock"; | |
| 570 | clocks = <&dpll_per_m2_ck>; | |
| 571 | clock-mult = <1>; | |
| 572 | clock-div = <2>; | |
| 573 | }; | |
| 574 | ||
| c5670481 | 575 | gfx_fclk_clksel_ck: gfx_fclk_clksel_ck@423c { |
| 6a679208 TK |
576 | #clock-cells = <0>; |
| 577 | compatible = "ti,mux-clock"; | |
| 578 | clocks = <&sysclk_div>, <&dpll_per_m2_ck>; | |
| 579 | ti,bit-shift = <1>; | |
| 580 | reg = <0x423c>; | |
| 581 | }; | |
| 582 | ||
| c5670481 | 583 | gfx_fck_div_ck: gfx_fck_div_ck@423c { |
| 6a679208 TK |
584 | #clock-cells = <0>; |
| 585 | compatible = "ti,divider-clock"; | |
| 586 | clocks = <&gfx_fclk_clksel_ck>; | |
| 587 | reg = <0x423c>; | |
| 588 | ti,max-div = <2>; | |
| 589 | }; | |
| 590 | ||
| c5670481 | 591 | disp_clk: disp_clk@4244 { |
| 6a679208 TK |
592 | #clock-cells = <0>; |
| 593 | compatible = "ti,mux-clock"; | |
| 594 | clocks = <&dpll_disp_m2_ck>, <&dpll_core_m5_ck>, <&dpll_per_m2_ck>; | |
| 595 | reg = <0x4244>; | |
| 10a6e183 | 596 | ti,set-rate-parent; |
| 6a679208 TK |
597 | }; |
| 598 | ||
| c5670481 | 599 | dpll_extdev_ck: dpll_extdev_ck@2e60 { |
| 6a679208 TK |
600 | #clock-cells = <0>; |
| 601 | compatible = "ti,am3-dpll-clock"; | |
| 602 | clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; | |
| 603 | reg = <0x2e60>, <0x2e64>, <0x2e6c>; | |
| 604 | }; | |
| 605 | ||
| c5670481 | 606 | dpll_extdev_m2_ck: dpll_extdev_m2_ck@2e70 { |
| 6a679208 TK |
607 | #clock-cells = <0>; |
| 608 | compatible = "ti,divider-clock"; | |
| 609 | clocks = <&dpll_extdev_ck>; | |
| 610 | ti,max-div = <127>; | |
| 611 | ti,autoidle-shift = <8>; | |
| 612 | reg = <0x2e70>; | |
| 613 | ti,index-starts-at-one; | |
| 614 | ti,invert-autoidle-bit; | |
| 615 | }; | |
| 616 | ||
| c5670481 | 617 | mux_synctimer32k_ck: mux_synctimer32k_ck@4230 { |
| 6a679208 TK |
618 | #clock-cells = <0>; |
| 619 | compatible = "ti,mux-clock"; | |
| 620 | clocks = <&clk_32768_ck>, <&clk_32k_tpm_ck>, <&clkdiv32k_ick>; | |
| 621 | reg = <0x4230>; | |
| 622 | }; | |
| 623 | ||
| c5670481 | 624 | synctimer_32kclk: synctimer_32kclk@2a30 { |
| 6a679208 TK |
625 | #clock-cells = <0>; |
| 626 | compatible = "ti,gate-clock"; | |
| 627 | clocks = <&mux_synctimer32k_ck>; | |
| 628 | ti,bit-shift = <8>; | |
| 629 | reg = <0x2a30>; | |
| 630 | }; | |
| 631 | ||
| c5670481 | 632 | timer8_fck: timer8_fck@421c { |
| 6a679208 TK |
633 | #clock-cells = <0>; |
| 634 | compatible = "ti,mux-clock"; | |
| 635 | clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>; | |
| 636 | reg = <0x421c>; | |
| 637 | }; | |
| 638 | ||
| c5670481 | 639 | timer9_fck: timer9_fck@4220 { |
| 6a679208 TK |
640 | #clock-cells = <0>; |
| 641 | compatible = "ti,mux-clock"; | |
| 642 | clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>; | |
| 643 | reg = <0x4220>; | |
| 644 | }; | |
| 645 | ||
| c5670481 | 646 | timer10_fck: timer10_fck@4224 { |
| 6a679208 TK |
647 | #clock-cells = <0>; |
| 648 | compatible = "ti,mux-clock"; | |
| 649 | clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>; | |
| 650 | reg = <0x4224>; | |
| 651 | }; | |
| 652 | ||
| c5670481 | 653 | timer11_fck: timer11_fck@4228 { |
| 6a679208 TK |
654 | #clock-cells = <0>; |
| 655 | compatible = "ti,mux-clock"; | |
| 656 | clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>; | |
| 657 | reg = <0x4228>; | |
| 658 | }; | |
| 659 | ||
| 660 | cpsw_50m_clkdiv: cpsw_50m_clkdiv { | |
| 661 | #clock-cells = <0>; | |
| 662 | compatible = "fixed-factor-clock"; | |
| 663 | clocks = <&dpll_core_m5_ck>; | |
| 664 | clock-mult = <1>; | |
| 665 | clock-div = <1>; | |
| 666 | }; | |
| 667 | ||
| 668 | cpsw_5m_clkdiv: cpsw_5m_clkdiv { | |
| 669 | #clock-cells = <0>; | |
| 670 | compatible = "fixed-factor-clock"; | |
| 671 | clocks = <&cpsw_50m_clkdiv>; | |
| 672 | clock-mult = <1>; | |
| 673 | clock-div = <10>; | |
| 674 | }; | |
| 675 | ||
| 676 | dpll_ddr_x2_ck: dpll_ddr_x2_ck { | |
| 677 | #clock-cells = <0>; | |
| 678 | compatible = "ti,am3-dpll-x2-clock"; | |
| 679 | clocks = <&dpll_ddr_ck>; | |
| 680 | }; | |
| 681 | ||
| c5670481 | 682 | dpll_ddr_m4_ck: dpll_ddr_m4_ck@2db8 { |
| 6a679208 TK |
683 | #clock-cells = <0>; |
| 684 | compatible = "ti,divider-clock"; | |
| 685 | clocks = <&dpll_ddr_x2_ck>; | |
| 686 | ti,max-div = <31>; | |
| 687 | ti,autoidle-shift = <8>; | |
| 688 | reg = <0x2db8>; | |
| 689 | ti,index-starts-at-one; | |
| 690 | ti,invert-autoidle-bit; | |
| 691 | }; | |
| 692 | ||
| c5670481 | 693 | dpll_per_clkdcoldo: dpll_per_clkdcoldo@2e14 { |
| 6a679208 | 694 | #clock-cells = <0>; |
| 50b96894 | 695 | compatible = "ti,fixed-factor-clock"; |
| 6a679208 | 696 | clocks = <&dpll_per_ck>; |
| 50b96894 DG |
697 | ti,clock-mult = <1>; |
| 698 | ti,clock-div = <1>; | |
| 699 | ti,autoidle-shift = <8>; | |
| 700 | reg = <0x2e14>; | |
| 701 | ti,invert-autoidle-bit; | |
| 6a679208 TK |
702 | }; |
| 703 | ||
| c5670481 | 704 | dll_aging_clk_div: dll_aging_clk_div@4250 { |
| 6a679208 TK |
705 | #clock-cells = <0>; |
| 706 | compatible = "ti,divider-clock"; | |
| 707 | clocks = <&sys_clkin_ck>; | |
| 708 | reg = <0x4250>; | |
| 709 | ti,dividers = <8>, <16>, <32>; | |
| 710 | }; | |
| 711 | ||
| 712 | div_core_25m_ck: div_core_25m_ck { | |
| 713 | #clock-cells = <0>; | |
| 714 | compatible = "fixed-factor-clock"; | |
| 715 | clocks = <&sysclk_div>; | |
| 716 | clock-mult = <1>; | |
| 717 | clock-div = <8>; | |
| 718 | }; | |
| 719 | ||
| 720 | func_12m_clk: func_12m_clk { | |
| 721 | #clock-cells = <0>; | |
| 722 | compatible = "fixed-factor-clock"; | |
| 723 | clocks = <&dpll_per_m2_ck>; | |
| 724 | clock-mult = <1>; | |
| 725 | clock-div = <16>; | |
| 726 | }; | |
| 727 | ||
| 728 | vtp_clk_div: vtp_clk_div { | |
| 729 | #clock-cells = <0>; | |
| 730 | compatible = "fixed-factor-clock"; | |
| 731 | clocks = <&sys_clkin_ck>; | |
| 732 | clock-mult = <1>; | |
| 733 | clock-div = <2>; | |
| 734 | }; | |
| 735 | ||
| c5670481 | 736 | usbphy_32khz_clkmux: usbphy_32khz_clkmux@4260 { |
| 6a679208 TK |
737 | #clock-cells = <0>; |
| 738 | compatible = "ti,mux-clock"; | |
| 739 | clocks = <&clk_32768_ck>, <&clk_32k_tpm_ck>; | |
| 740 | reg = <0x4260>; | |
| 741 | }; | |
| eac1cd3b | 742 | |
| c5670481 | 743 | usb_phy0_always_on_clk32k: usb_phy0_always_on_clk32k@2a40 { |
| eac1cd3b GC |
744 | #clock-cells = <0>; |
| 745 | compatible = "ti,gate-clock"; | |
| 746 | clocks = <&usbphy_32khz_clkmux>; | |
| 747 | ti,bit-shift = <8>; | |
| 748 | reg = <0x2a40>; | |
| 749 | }; | |
| 750 | ||
| c5670481 | 751 | usb_phy1_always_on_clk32k: usb_phy1_always_on_clk32k@2a48 { |
| eac1cd3b GC |
752 | #clock-cells = <0>; |
| 753 | compatible = "ti,gate-clock"; | |
| 754 | clocks = <&usbphy_32khz_clkmux>; | |
| 755 | ti,bit-shift = <8>; | |
| 756 | reg = <0x2a48>; | |
| 757 | }; | |
| 758 | ||
| c5670481 | 759 | usb_otg_ss0_refclk960m: usb_otg_ss0_refclk960m@8a60 { |
| eac1cd3b GC |
760 | #clock-cells = <0>; |
| 761 | compatible = "ti,gate-clock"; | |
| 762 | clocks = <&dpll_per_clkdcoldo>; | |
| 763 | ti,bit-shift = <8>; | |
| 764 | reg = <0x8a60>; | |
| 765 | }; | |
| 766 | ||
| c5670481 | 767 | usb_otg_ss1_refclk960m: usb_otg_ss1_refclk960m@8a68 { |
| eac1cd3b GC |
768 | #clock-cells = <0>; |
| 769 | compatible = "ti,gate-clock"; | |
| 770 | clocks = <&dpll_per_clkdcoldo>; | |
| 771 | ti,bit-shift = <8>; | |
| 772 | reg = <0x8a68>; | |
| 773 | }; | |
| 8010f13a TK |
774 | |
| 775 | clkout1_osc_div_ck: clkout1_osc_div_ck { | |
| 776 | #clock-cells = <0>; | |
| 777 | compatible = "ti,divider-clock"; | |
| 778 | clocks = <&sys_clkin_ck>; | |
| 779 | ti,bit-shift = <20>; | |
| 780 | ti,max-div = <4>; | |
| 781 | reg = <0x4100>; | |
| 782 | }; | |
| 783 | ||
| 784 | clkout1_src2_mux_ck: clkout1_src2_mux_ck { | |
| 785 | #clock-cells = <0>; | |
| 786 | compatible = "ti,mux-clock"; | |
| 787 | clocks = <&clk_rc32k_ck>, <&sysclk_div>, <&dpll_ddr_m2_ck>, | |
| 788 | <&dpll_per_m2_ck>, <&dpll_disp_m2_ck>, | |
| 789 | <&dpll_mpu_m2_ck>; | |
| 790 | reg = <0x4100>; | |
| 791 | }; | |
| 792 | ||
| 793 | clkout1_src2_pre_div_ck: clkout1_src2_pre_div_ck { | |
| 794 | #clock-cells = <0>; | |
| 795 | compatible = "ti,divider-clock"; | |
| 796 | clocks = <&clkout1_src2_mux_ck>; | |
| 797 | ti,bit-shift = <4>; | |
| 798 | ti,max-div = <8>; | |
| 799 | reg = <0x4100>; | |
| 800 | }; | |
| 801 | ||
| 802 | clkout1_src2_post_div_ck: clkout1_src2_post_div_ck { | |
| 803 | #clock-cells = <0>; | |
| 804 | compatible = "ti,divider-clock"; | |
| 805 | clocks = <&clkout1_src2_pre_div_ck>; | |
| 806 | ti,bit-shift = <8>; | |
| 807 | ti,max-div = <32>; | |
| 808 | ti,index-power-of-two; | |
| 809 | reg = <0x4100>; | |
| 810 | }; | |
| 811 | ||
| 812 | clkout1_mux_ck: clkout1_mux_ck { | |
| 813 | #clock-cells = <0>; | |
| 814 | compatible = "ti,mux-clock"; | |
| 815 | clocks = <&clkout1_osc_div_ck>, <&clk_rc32k_ck>, | |
| 816 | <&clkout1_src2_post_div_ck>, <&dpll_extdev_m2_ck>; | |
| 817 | ti,bit-shift = <16>; | |
| 818 | reg = <0x4100>; | |
| 819 | }; | |
| 820 | ||
| 821 | clkout1_ck: clkout1_ck { | |
| 822 | #clock-cells = <0>; | |
| 823 | compatible = "ti,gate-clock"; | |
| 824 | clocks = <&clkout1_mux_ck>; | |
| 825 | ti,bit-shift = <23>; | |
| 826 | reg = <0x4100>; | |
| 827 | }; | |
| 6a679208 | 828 | }; |