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5a0f93c6 NM |
1 | /* |
2 | * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | */ | |
8 | /dts-v1/; | |
9 | ||
10 | #include "dra74x.dtsi" | |
266e62f9 | 11 | #include "am57xx-commercial-grade.dtsi" |
5a0f93c6 NM |
12 | #include <dt-bindings/gpio/gpio.h> |
13 | #include <dt-bindings/interrupt-controller/irq.h> | |
14 | ||
15 | / { | |
16 | model = "TI AM5728 BeagleBoard-X15"; | |
17 | compatible = "ti,am572x-beagle-x15", "ti,am5728", "ti,dra742", "ti,dra74", "ti,dra7"; | |
18 | ||
19 | aliases { | |
20 | rtc0 = &mcp_rtc; | |
21 | rtc1 = &tps659038_rtc; | |
00edd317 | 22 | rtc2 = &rtc; |
0c534938 | 23 | display0 = &hdmi0; |
5a0f93c6 NM |
24 | }; |
25 | ||
26 | memory { | |
27 | device_type = "memory"; | |
dae320ec | 28 | reg = <0x0 0x80000000 0x0 0x80000000>; |
5a0f93c6 NM |
29 | }; |
30 | ||
31 | vdd_3v3: fixedregulator-vdd_3v3 { | |
32 | compatible = "regulator-fixed"; | |
33 | regulator-name = "vdd_3v3"; | |
34 | vin-supply = <®en1>; | |
35 | regulator-min-microvolt = <3300000>; | |
36 | regulator-max-microvolt = <3300000>; | |
37 | }; | |
38 | ||
d929e8bb PU |
39 | aic_dvdd: fixedregulator-aic_dvdd { |
40 | compatible = "regulator-fixed"; | |
41 | regulator-name = "aic_dvdd_fixed"; | |
42 | vin-supply = <&vdd_3v3>; | |
43 | regulator-min-microvolt = <1800000>; | |
44 | regulator-max-microvolt = <1800000>; | |
45 | }; | |
46 | ||
5a0f93c6 NM |
47 | vtt_fixed: fixedregulator-vtt { |
48 | /* TPS51200 */ | |
49 | compatible = "regulator-fixed"; | |
50 | regulator-name = "vtt_fixed"; | |
51 | vin-supply = <&smps3_reg>; | |
52 | regulator-min-microvolt = <3300000>; | |
53 | regulator-max-microvolt = <3300000>; | |
54 | regulator-always-on; | |
55 | regulator-boot-on; | |
56 | enable-active-high; | |
57 | gpio = <&gpio7 11 GPIO_ACTIVE_HIGH>; | |
58 | }; | |
59 | ||
60 | leds { | |
61 | compatible = "gpio-leds"; | |
62 | pinctrl-names = "default"; | |
63 | pinctrl-0 = <&leds_pins_default>; | |
64 | ||
65 | led@0 { | |
66 | label = "beagle-x15:usr0"; | |
67 | gpios = <&gpio7 9 GPIO_ACTIVE_HIGH>; | |
68 | linux,default-trigger = "heartbeat"; | |
69 | default-state = "off"; | |
70 | }; | |
71 | ||
72 | led@1 { | |
73 | label = "beagle-x15:usr1"; | |
74 | gpios = <&gpio7 8 GPIO_ACTIVE_HIGH>; | |
75 | linux,default-trigger = "cpu0"; | |
76 | default-state = "off"; | |
77 | }; | |
78 | ||
79 | led@2 { | |
80 | label = "beagle-x15:usr2"; | |
81 | gpios = <&gpio7 14 GPIO_ACTIVE_HIGH>; | |
82 | linux,default-trigger = "mmc0"; | |
83 | default-state = "off"; | |
84 | }; | |
85 | ||
86 | led@3 { | |
87 | label = "beagle-x15:usr3"; | |
88 | gpios = <&gpio7 15 GPIO_ACTIVE_HIGH>; | |
89 | linux,default-trigger = "ide-disk"; | |
90 | default-state = "off"; | |
91 | }; | |
92 | }; | |
7a03f2c0 NM |
93 | |
94 | gpio_fan: gpio_fan { | |
95 | /* Based on 5v 500mA AFB02505HHB */ | |
96 | compatible = "gpio-fan"; | |
ed12f102 | 97 | gpios = <&tps659038_gpio 2 GPIO_ACTIVE_HIGH>; |
7a03f2c0 NM |
98 | gpio-fan,speed-map = <0 0>, |
99 | <13000 1>; | |
d723cfea | 100 | #cooling-cells = <2>; |
7a03f2c0 | 101 | }; |
f60db98e | 102 | |
0c534938 TV |
103 | hdmi0: connector { |
104 | compatible = "hdmi-connector"; | |
105 | label = "hdmi"; | |
106 | ||
107 | type = "a"; | |
108 | ||
109 | port { | |
110 | hdmi_connector_in: endpoint { | |
111 | remote-endpoint = <&tpd12s015_out>; | |
112 | }; | |
113 | }; | |
114 | }; | |
115 | ||
116 | tpd12s015: encoder { | |
117 | compatible = "ti,tpd12s015"; | |
118 | ||
119 | pinctrl-names = "default"; | |
120 | pinctrl-0 = <&tpd12s015_pins>; | |
121 | ||
122 | gpios = <&gpio7 10 GPIO_ACTIVE_HIGH>, /* gpio7_10, CT CP HPD */ | |
123 | <&gpio6 28 GPIO_ACTIVE_HIGH>, /* gpio6_28, LS OE */ | |
124 | <&gpio7 12 GPIO_ACTIVE_HIGH>; /* gpio7_12/sp1_cs2, HPD */ | |
125 | ||
126 | ports { | |
127 | #address-cells = <1>; | |
128 | #size-cells = <0>; | |
129 | ||
130 | port@0 { | |
131 | reg = <0>; | |
132 | ||
133 | tpd12s015_in: endpoint { | |
134 | remote-endpoint = <&hdmi_out>; | |
135 | }; | |
136 | }; | |
137 | ||
138 | port@1 { | |
139 | reg = <1>; | |
140 | ||
141 | tpd12s015_out: endpoint { | |
142 | remote-endpoint = <&hdmi_connector_in>; | |
143 | }; | |
144 | }; | |
145 | }; | |
146 | }; | |
a00e368c | 147 | |
4e8603ef | 148 | sound0: sound0 { |
a00e368c PU |
149 | compatible = "simple-audio-card"; |
150 | simple-audio-card,name = "BeagleBoard-X15"; | |
151 | simple-audio-card,widgets = | |
152 | "Line", "Line Out", | |
153 | "Line", "Line In"; | |
154 | simple-audio-card,routing = | |
155 | "Line Out", "LLOUT", | |
156 | "Line Out", "RLOUT", | |
157 | "MIC2L", "Line In", | |
158 | "MIC2R", "Line In"; | |
159 | simple-audio-card,format = "dsp_b"; | |
160 | simple-audio-card,bitclock-master = <&sound0_master>; | |
161 | simple-audio-card,frame-master = <&sound0_master>; | |
162 | simple-audio-card,bitclock-inversion; | |
163 | ||
164 | simple-audio-card,cpu { | |
165 | sound-dai = <&mcasp3>; | |
166 | }; | |
167 | ||
168 | sound0_master: simple-audio-card,codec { | |
169 | sound-dai = <&tlv320aic3104>; | |
170 | clocks = <&clkout2_clk>; | |
171 | }; | |
172 | }; | |
5a0f93c6 NM |
173 | }; |
174 | ||
175 | &dra7_pmx_core { | |
176 | leds_pins_default: leds_pins_default { | |
177 | pinctrl-single,pins = < | |
f70dfa66 JMC |
178 | DRA7XX_CORE_IOPAD(0x37a8, PIN_OUTPUT | MUX_MODE14) /* spi1_d1.gpio7_8 */ |
179 | DRA7XX_CORE_IOPAD(0x37ac, PIN_OUTPUT | MUX_MODE14) /* spi1_d0.gpio7_9 */ | |
180 | DRA7XX_CORE_IOPAD(0x37c0, PIN_OUTPUT | MUX_MODE14) /* spi2_sclk.gpio7_14 */ | |
181 | DRA7XX_CORE_IOPAD(0x37c4, PIN_OUTPUT | MUX_MODE14) /* spi2_d1.gpio7_15 */ | |
5a0f93c6 NM |
182 | >; |
183 | }; | |
184 | ||
185 | i2c1_pins_default: i2c1_pins_default { | |
186 | pinctrl-single,pins = < | |
f70dfa66 JMC |
187 | DRA7XX_CORE_IOPAD(0x3800, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda.sda */ |
188 | DRA7XX_CORE_IOPAD(0x3804, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl.scl */ | |
5a0f93c6 NM |
189 | >; |
190 | }; | |
191 | ||
0c534938 TV |
192 | hdmi_pins: pinmux_hdmi_pins { |
193 | pinctrl-single,pins = < | |
f70dfa66 JMC |
194 | DRA7XX_CORE_IOPAD(0x3808, PIN_INPUT | MUX_MODE1) /* i2c2_sda.hdmi1_ddc_scl */ |
195 | DRA7XX_CORE_IOPAD(0x380c, PIN_INPUT | MUX_MODE1) /* i2c2_scl.hdmi1_ddc_sda */ | |
0c534938 TV |
196 | >; |
197 | }; | |
198 | ||
5a0f93c6 NM |
199 | i2c3_pins_default: i2c3_pins_default { |
200 | pinctrl-single,pins = < | |
f70dfa66 JMC |
201 | DRA7XX_CORE_IOPAD(0x36a4, PIN_INPUT| MUX_MODE10) /* mcasp1_aclkx.i2c3_sda */ |
202 | DRA7XX_CORE_IOPAD(0x36a8, PIN_INPUT| MUX_MODE10) /* mcasp1_fsx.i2c3_scl */ | |
5a0f93c6 NM |
203 | >; |
204 | }; | |
205 | ||
206 | uart3_pins_default: uart3_pins_default { | |
207 | pinctrl-single,pins = < | |
f70dfa66 JMC |
208 | DRA7XX_CORE_IOPAD(0x37f8, PIN_INPUT_SLEW | MUX_MODE2) /* uart2_ctsn.uart3_rxd */ |
209 | DRA7XX_CORE_IOPAD(0x37fc, PIN_INPUT_SLEW | MUX_MODE1) /* uart2_rtsn.uart3_txd */ | |
5a0f93c6 NM |
210 | >; |
211 | }; | |
212 | ||
213 | mmc1_pins_default: mmc1_pins_default { | |
214 | pinctrl-single,pins = < | |
f70dfa66 JMC |
215 | DRA7XX_CORE_IOPAD(0x376c, PIN_INPUT | MUX_MODE14) /* mmc1sdcd.gpio219 */ |
216 | DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ | |
217 | DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ | |
218 | DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */ | |
219 | DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */ | |
220 | DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */ | |
221 | DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */ | |
5a0f93c6 NM |
222 | >; |
223 | }; | |
224 | ||
225 | mmc2_pins_default: mmc2_pins_default { | |
226 | pinctrl-single,pins = < | |
f70dfa66 JMC |
227 | DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */ |
228 | DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ | |
229 | DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ | |
230 | DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ | |
231 | DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ | |
232 | DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ | |
233 | DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ | |
234 | DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ | |
235 | DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ | |
236 | DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ | |
5a0f93c6 NM |
237 | >; |
238 | }; | |
239 | ||
a75dacf8 FB |
240 | cpsw_pins_default: cpsw_pins_default { |
241 | pinctrl-single,pins = < | |
242 | /* Slave 1 */ | |
f70dfa66 JMC |
243 | DRA7XX_CORE_IOPAD(0x3650, PIN_OUTPUT | MUX_MODE0) /* rgmii1_tclk */ |
244 | DRA7XX_CORE_IOPAD(0x3654, PIN_OUTPUT | MUX_MODE0) /* rgmii1_tctl */ | |
245 | DRA7XX_CORE_IOPAD(0x3658, PIN_OUTPUT | MUX_MODE0) /* rgmii1_td3 */ | |
246 | DRA7XX_CORE_IOPAD(0x365c, PIN_OUTPUT | MUX_MODE0) /* rgmii1_td2 */ | |
247 | DRA7XX_CORE_IOPAD(0x3660, PIN_OUTPUT | MUX_MODE0) /* rgmii1_td1 */ | |
248 | DRA7XX_CORE_IOPAD(0x3664, PIN_OUTPUT | MUX_MODE0) /* rgmii1_td0 */ | |
249 | DRA7XX_CORE_IOPAD(0x3668, PIN_INPUT | MUX_MODE0) /* rgmii1_rclk */ | |
250 | DRA7XX_CORE_IOPAD(0x366c, PIN_INPUT | MUX_MODE0) /* rgmii1_rctl */ | |
251 | DRA7XX_CORE_IOPAD(0x3670, PIN_INPUT | MUX_MODE0) /* rgmii1_rd3 */ | |
252 | DRA7XX_CORE_IOPAD(0x3674, PIN_INPUT | MUX_MODE0) /* rgmii1_rd2 */ | |
253 | DRA7XX_CORE_IOPAD(0x3678, PIN_INPUT | MUX_MODE0) /* rgmii1_rd1 */ | |
254 | DRA7XX_CORE_IOPAD(0x367c, PIN_INPUT | MUX_MODE0) /* rgmii1_rd0 */ | |
a75dacf8 FB |
255 | |
256 | /* Slave 2 */ | |
f70dfa66 JMC |
257 | DRA7XX_CORE_IOPAD(0x3598, PIN_OUTPUT | MUX_MODE3) /* rgmii2_tclk */ |
258 | DRA7XX_CORE_IOPAD(0x359c, PIN_OUTPUT | MUX_MODE3) /* rgmii2_tctl */ | |
259 | DRA7XX_CORE_IOPAD(0x35a0, PIN_OUTPUT | MUX_MODE3) /* rgmii2_td3 */ | |
260 | DRA7XX_CORE_IOPAD(0x35a4, PIN_OUTPUT | MUX_MODE3) /* rgmii2_td2 */ | |
261 | DRA7XX_CORE_IOPAD(0x35a8, PIN_OUTPUT | MUX_MODE3) /* rgmii2_td1 */ | |
262 | DRA7XX_CORE_IOPAD(0x35ac, PIN_OUTPUT | MUX_MODE3) /* rgmii2_td0 */ | |
263 | DRA7XX_CORE_IOPAD(0x35b0, PIN_INPUT | MUX_MODE3) /* rgmii2_rclk */ | |
264 | DRA7XX_CORE_IOPAD(0x35b4, PIN_INPUT | MUX_MODE3) /* rgmii2_rctl */ | |
265 | DRA7XX_CORE_IOPAD(0x35b8, PIN_INPUT | MUX_MODE3) /* rgmii2_rd3 */ | |
266 | DRA7XX_CORE_IOPAD(0x35bc, PIN_INPUT | MUX_MODE3) /* rgmii2_rd2 */ | |
267 | DRA7XX_CORE_IOPAD(0x35c0, PIN_INPUT | MUX_MODE3) /* rgmii2_rd1 */ | |
268 | DRA7XX_CORE_IOPAD(0x35c4, PIN_INPUT | MUX_MODE3) /* rgmii2_rd0 */ | |
a75dacf8 FB |
269 | >; |
270 | ||
271 | }; | |
272 | ||
273 | cpsw_pins_sleep: cpsw_pins_sleep { | |
274 | pinctrl-single,pins = < | |
275 | /* Slave 1 */ | |
f70dfa66 JMC |
276 | DRA7XX_CORE_IOPAD(0x3650, PIN_INPUT | MUX_MODE15) |
277 | DRA7XX_CORE_IOPAD(0x3654, PIN_INPUT | MUX_MODE15) | |
278 | DRA7XX_CORE_IOPAD(0x3658, PIN_INPUT | MUX_MODE15) | |
279 | DRA7XX_CORE_IOPAD(0x365c, PIN_INPUT | MUX_MODE15) | |
280 | DRA7XX_CORE_IOPAD(0x3660, PIN_INPUT | MUX_MODE15) | |
281 | DRA7XX_CORE_IOPAD(0x3664, PIN_INPUT | MUX_MODE15) | |
282 | DRA7XX_CORE_IOPAD(0x3668, PIN_INPUT | MUX_MODE15) | |
283 | DRA7XX_CORE_IOPAD(0x366c, PIN_INPUT | MUX_MODE15) | |
284 | DRA7XX_CORE_IOPAD(0x3670, PIN_INPUT | MUX_MODE15) | |
285 | DRA7XX_CORE_IOPAD(0x3674, PIN_INPUT | MUX_MODE15) | |
286 | DRA7XX_CORE_IOPAD(0x3678, PIN_INPUT | MUX_MODE15) | |
287 | DRA7XX_CORE_IOPAD(0x367c, PIN_INPUT | MUX_MODE15) | |
a75dacf8 FB |
288 | |
289 | /* Slave 2 */ | |
f70dfa66 JMC |
290 | DRA7XX_CORE_IOPAD(0x3598, PIN_INPUT | MUX_MODE15) |
291 | DRA7XX_CORE_IOPAD(0x359c, PIN_INPUT | MUX_MODE15) | |
292 | DRA7XX_CORE_IOPAD(0x35a0, PIN_INPUT | MUX_MODE15) | |
293 | DRA7XX_CORE_IOPAD(0x35a4, PIN_INPUT | MUX_MODE15) | |
294 | DRA7XX_CORE_IOPAD(0x35a8, PIN_INPUT | MUX_MODE15) | |
295 | DRA7XX_CORE_IOPAD(0x35ac, PIN_INPUT | MUX_MODE15) | |
296 | DRA7XX_CORE_IOPAD(0x35b0, PIN_INPUT | MUX_MODE15) | |
297 | DRA7XX_CORE_IOPAD(0x35b4, PIN_INPUT | MUX_MODE15) | |
298 | DRA7XX_CORE_IOPAD(0x35b8, PIN_INPUT | MUX_MODE15) | |
299 | DRA7XX_CORE_IOPAD(0x35bc, PIN_INPUT | MUX_MODE15) | |
300 | DRA7XX_CORE_IOPAD(0x35c0, PIN_INPUT | MUX_MODE15) | |
301 | DRA7XX_CORE_IOPAD(0x35c4, PIN_INPUT | MUX_MODE15) | |
a75dacf8 FB |
302 | >; |
303 | }; | |
304 | ||
305 | davinci_mdio_pins_default: davinci_mdio_pins_default { | |
306 | pinctrl-single,pins = < | |
307 | /* MDIO */ | |
f70dfa66 JMC |
308 | DRA7XX_CORE_IOPAD(0x363c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_mclk */ |
309 | DRA7XX_CORE_IOPAD(0x3640, PIN_INPUT_PULLUP | MUX_MODE0) /* mdio_d */ | |
a75dacf8 FB |
310 | >; |
311 | }; | |
312 | ||
313 | davinci_mdio_pins_sleep: davinci_mdio_pins_sleep { | |
314 | pinctrl-single,pins = < | |
f70dfa66 JMC |
315 | DRA7XX_CORE_IOPAD(0x363c, PIN_INPUT | MUX_MODE15) |
316 | DRA7XX_CORE_IOPAD(0x3640, PIN_INPUT | MUX_MODE15) | |
a75dacf8 FB |
317 | >; |
318 | }; | |
319 | ||
5a0f93c6 NM |
320 | tps659038_pins_default: tps659038_pins_default { |
321 | pinctrl-single,pins = < | |
f70dfa66 | 322 | DRA7XX_CORE_IOPAD(0x3818, PIN_INPUT_PULLUP | MUX_MODE14) /* wakeup0.gpio1_0 */ |
5a0f93c6 NM |
323 | >; |
324 | }; | |
325 | ||
326 | tmp102_pins_default: tmp102_pins_default { | |
327 | pinctrl-single,pins = < | |
f70dfa66 | 328 | DRA7XX_CORE_IOPAD(0x37c8, PIN_INPUT_PULLUP | MUX_MODE14) /* spi2_d0.gpio7_16 */ |
5a0f93c6 NM |
329 | >; |
330 | }; | |
331 | ||
332 | mcp79410_pins_default: mcp79410_pins_default { | |
333 | pinctrl-single,pins = < | |
f70dfa66 | 334 | DRA7XX_CORE_IOPAD(0x3824, PIN_INPUT_PULLUP | MUX_MODE1) /* wakeup3.sys_nirq1 */ |
5a0f93c6 NM |
335 | >; |
336 | }; | |
337 | ||
338 | usb1_pins: pinmux_usb1_pins { | |
339 | pinctrl-single,pins = < | |
f70dfa66 | 340 | DRA7XX_CORE_IOPAD(0x3680, PIN_INPUT_SLEW | MUX_MODE0) /* usb1_drvvbus */ |
5a0f93c6 NM |
341 | >; |
342 | }; | |
343 | ||
0c534938 TV |
344 | tpd12s015_pins: pinmux_tpd12s015_pins { |
345 | pinctrl-single,pins = < | |
f70dfa66 JMC |
346 | DRA7XX_CORE_IOPAD(0x37b0, PIN_OUTPUT | MUX_MODE14) /* gpio7_10 CT_CP_HPD */ |
347 | DRA7XX_CORE_IOPAD(0x37b8, PIN_INPUT_PULLDOWN | MUX_MODE14) /* gpio7_12 HPD */ | |
348 | DRA7XX_CORE_IOPAD(0x3770, PIN_OUTPUT | MUX_MODE14) /* gpio6_28 LS_OE */ | |
0c534938 TV |
349 | >; |
350 | }; | |
a00e368c PU |
351 | |
352 | clkout2_pins_default: clkout2_pins_default { | |
353 | pinctrl-single,pins = < | |
f70dfa66 | 354 | DRA7XX_CORE_IOPAD(0x3694, PIN_OUTPUT_PULLDOWN | MUX_MODE9) /* xref_clk0.clkout2 */ |
a00e368c PU |
355 | >; |
356 | }; | |
357 | ||
358 | clkout2_pins_sleep: clkout2_pins_sleep { | |
359 | pinctrl-single,pins = < | |
f70dfa66 | 360 | DRA7XX_CORE_IOPAD(0x3694, PIN_INPUT | MUX_MODE15) /* xref_clk0.clkout2 */ |
a00e368c PU |
361 | >; |
362 | }; | |
363 | ||
364 | mcasp3_pins_default: mcasp3_pins_default { | |
365 | pinctrl-single,pins = < | |
f70dfa66 JMC |
366 | DRA7XX_CORE_IOPAD(0x3724, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp3_aclkx.mcasp3_aclkx */ |
367 | DRA7XX_CORE_IOPAD(0x3728, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp3_fsx.mcasp3_fsx */ | |
368 | DRA7XX_CORE_IOPAD(0x372c, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_axr0.mcasp3_axr0 */ | |
369 | DRA7XX_CORE_IOPAD(0x3730, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp3_axr1.mcasp3_axr1 */ | |
a00e368c PU |
370 | >; |
371 | }; | |
372 | ||
373 | mcasp3_pins_sleep: mcasp3_pins_sleep { | |
374 | pinctrl-single,pins = < | |
f70dfa66 JMC |
375 | DRA7XX_CORE_IOPAD(0x3724, PIN_INPUT | MUX_MODE15) |
376 | DRA7XX_CORE_IOPAD(0x3728, PIN_INPUT | MUX_MODE15) | |
377 | DRA7XX_CORE_IOPAD(0x372c, PIN_INPUT | MUX_MODE15) | |
378 | DRA7XX_CORE_IOPAD(0x3730, PIN_INPUT | MUX_MODE15) | |
a00e368c PU |
379 | >; |
380 | }; | |
5a0f93c6 NM |
381 | }; |
382 | ||
383 | &i2c1 { | |
384 | status = "okay"; | |
385 | pinctrl-names = "default"; | |
386 | pinctrl-0 = <&i2c1_pins_default>; | |
387 | clock-frequency = <400000>; | |
388 | ||
389 | tps659038: tps659038@58 { | |
390 | compatible = "ti,tps659038"; | |
391 | reg = <0x58>; | |
392 | interrupt-parent = <&gpio1>; | |
393 | interrupts = <0 IRQ_TYPE_LEVEL_LOW>; | |
394 | ||
395 | pinctrl-names = "default"; | |
396 | pinctrl-0 = <&tps659038_pins_default>; | |
397 | ||
398 | #interrupt-cells = <2>; | |
399 | interrupt-controller; | |
400 | ||
401 | ti,system-power-controller; | |
402 | ||
403 | tps659038_pmic { | |
404 | compatible = "ti,tps659038-pmic"; | |
405 | ||
406 | regulators { | |
407 | smps12_reg: smps12 { | |
408 | /* VDD_MPU */ | |
409 | regulator-name = "smps12"; | |
410 | regulator-min-microvolt = < 850000>; | |
411 | regulator-max-microvolt = <1250000>; | |
412 | regulator-always-on; | |
413 | regulator-boot-on; | |
414 | }; | |
415 | ||
416 | smps3_reg: smps3 { | |
417 | /* VDD_DDR */ | |
418 | regulator-name = "smps3"; | |
419 | regulator-min-microvolt = <1350000>; | |
420 | regulator-max-microvolt = <1350000>; | |
421 | regulator-always-on; | |
422 | regulator-boot-on; | |
423 | }; | |
424 | ||
425 | smps45_reg: smps45 { | |
426 | /* VDD_DSPEVE, VDD_IVA, VDD_GPU */ | |
427 | regulator-name = "smps45"; | |
428 | regulator-min-microvolt = < 850000>; | |
54d03c5d | 429 | regulator-max-microvolt = <1250000>; |
5a0f93c6 NM |
430 | regulator-always-on; |
431 | regulator-boot-on; | |
432 | }; | |
433 | ||
434 | smps6_reg: smps6 { | |
435 | /* VDD_CORE */ | |
436 | regulator-name = "smps6"; | |
437 | regulator-min-microvolt = <850000>; | |
54d03c5d | 438 | regulator-max-microvolt = <1150000>; |
5a0f93c6 NM |
439 | regulator-always-on; |
440 | regulator-boot-on; | |
441 | }; | |
442 | ||
443 | /* SMPS7 unused */ | |
444 | ||
445 | smps8_reg: smps8 { | |
446 | /* VDD_1V8 */ | |
447 | regulator-name = "smps8"; | |
448 | regulator-min-microvolt = <1800000>; | |
449 | regulator-max-microvolt = <1800000>; | |
450 | regulator-always-on; | |
451 | regulator-boot-on; | |
452 | }; | |
453 | ||
454 | /* SMPS9 unused */ | |
455 | ||
456 | ldo1_reg: ldo1 { | |
7e381ec6 | 457 | /* VDD_SD / VDDSHV8 */ |
5a0f93c6 NM |
458 | regulator-name = "ldo1"; |
459 | regulator-min-microvolt = <1800000>; | |
460 | regulator-max-microvolt = <3300000>; | |
461 | regulator-boot-on; | |
7e381ec6 | 462 | regulator-always-on; |
5a0f93c6 NM |
463 | }; |
464 | ||
465 | ldo2_reg: ldo2 { | |
466 | /* VDD_SHV5 */ | |
467 | regulator-name = "ldo2"; | |
468 | regulator-min-microvolt = <3300000>; | |
469 | regulator-max-microvolt = <3300000>; | |
470 | regulator-always-on; | |
471 | regulator-boot-on; | |
472 | }; | |
473 | ||
474 | ldo3_reg: ldo3 { | |
5005296e | 475 | /* VDDA_1V8_PHYA */ |
5a0f93c6 NM |
476 | regulator-name = "ldo3"; |
477 | regulator-min-microvolt = <1800000>; | |
478 | regulator-max-microvolt = <1800000>; | |
479 | regulator-always-on; | |
480 | regulator-boot-on; | |
481 | }; | |
482 | ||
5005296e NM |
483 | ldo4_reg: ldo4 { |
484 | /* VDDA_1V8_PHYB */ | |
485 | regulator-name = "ldo4"; | |
486 | regulator-min-microvolt = <1800000>; | |
487 | regulator-max-microvolt = <1800000>; | |
488 | regulator-always-on; | |
489 | regulator-boot-on; | |
490 | }; | |
491 | ||
5a0f93c6 NM |
492 | ldo9_reg: ldo9 { |
493 | /* VDD_RTC */ | |
494 | regulator-name = "ldo9"; | |
495 | regulator-min-microvolt = <1050000>; | |
496 | regulator-max-microvolt = <1050000>; | |
497 | regulator-always-on; | |
498 | regulator-boot-on; | |
499 | }; | |
500 | ||
501 | ldoln_reg: ldoln { | |
502 | /* VDDA_1V8_PLL */ | |
503 | regulator-name = "ldoln"; | |
504 | regulator-min-microvolt = <1800000>; | |
505 | regulator-max-microvolt = <1800000>; | |
506 | regulator-always-on; | |
507 | regulator-boot-on; | |
508 | }; | |
509 | ||
510 | ldousb_reg: ldousb { | |
511 | /* VDDA_3V_USB: VDDA_USBHS33 */ | |
512 | regulator-name = "ldousb"; | |
513 | regulator-min-microvolt = <3300000>; | |
514 | regulator-max-microvolt = <3300000>; | |
515 | regulator-boot-on; | |
516 | }; | |
517 | ||
518 | regen1: regen1 { | |
519 | /* VDD_3V3_ON */ | |
520 | regulator-name = "regen1"; | |
521 | regulator-boot-on; | |
522 | regulator-always-on; | |
523 | }; | |
524 | }; | |
525 | }; | |
526 | ||
527 | tps659038_rtc: tps659038_rtc { | |
528 | compatible = "ti,palmas-rtc"; | |
529 | interrupt-parent = <&tps659038>; | |
530 | interrupts = <8 IRQ_TYPE_EDGE_FALLING>; | |
531 | wakeup-source; | |
532 | }; | |
533 | ||
534 | tps659038_pwr_button: tps659038_pwr_button { | |
535 | compatible = "ti,palmas-pwrbutton"; | |
536 | interrupt-parent = <&tps659038>; | |
537 | interrupts = <1 IRQ_TYPE_EDGE_FALLING>; | |
538 | wakeup-source; | |
539 | ti,palmas-long-press-seconds = <12>; | |
540 | }; | |
7a03f2c0 NM |
541 | |
542 | tps659038_gpio: tps659038_gpio { | |
543 | compatible = "ti,palmas-gpio"; | |
544 | gpio-controller; | |
545 | #gpio-cells = <2>; | |
546 | }; | |
84ad1bab RQ |
547 | |
548 | extcon_usb2: tps659038_usb { | |
549 | compatible = "ti,palmas-usb-vid"; | |
550 | ti,enable-vbus-detection; | |
0331966d | 551 | vbus-gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>; |
84ad1bab RQ |
552 | }; |
553 | ||
5a0f93c6 NM |
554 | }; |
555 | ||
556 | tmp102: tmp102@48 { | |
557 | compatible = "ti,tmp102"; | |
558 | reg = <0x48>; | |
559 | pinctrl-names = "default"; | |
560 | pinctrl-0 = <&tmp102_pins_default>; | |
561 | interrupt-parent = <&gpio7>; | |
562 | interrupts = <16 IRQ_TYPE_LEVEL_LOW>; | |
d723cfea | 563 | #thermal-sensor-cells = <1>; |
5a0f93c6 | 564 | }; |
a00e368c PU |
565 | |
566 | tlv320aic3104: tlv320aic3104@18 { | |
567 | #sound-dai-cells = <0>; | |
568 | compatible = "ti,tlv320aic3104"; | |
569 | reg = <0x18>; | |
570 | pinctrl-names = "default", "sleep"; | |
571 | pinctrl-0 = <&clkout2_pins_default>; | |
572 | pinctrl-1 = <&clkout2_pins_sleep>; | |
e80ab5c9 PU |
573 | assigned-clocks = <&clkoutmux2_clk_mux>; |
574 | assigned-clock-parents = <&sys_clk2_dclk_div>; | |
575 | ||
a00e368c PU |
576 | status = "okay"; |
577 | adc-settle-ms = <40>; | |
578 | ||
579 | AVDD-supply = <&vdd_3v3>; | |
580 | IOVDD-supply = <&vdd_3v3>; | |
581 | DRVDD-supply = <&vdd_3v3>; | |
582 | DVDD-supply = <&aic_dvdd>; | |
583 | }; | |
b9d3ec1d NM |
584 | |
585 | eeprom: eeprom@50 { | |
586 | compatible = "at,24c32"; | |
587 | reg = <0x50>; | |
588 | }; | |
5a0f93c6 NM |
589 | }; |
590 | ||
591 | &i2c3 { | |
592 | status = "okay"; | |
593 | pinctrl-names = "default"; | |
594 | pinctrl-0 = <&i2c3_pins_default>; | |
595 | clock-frequency = <400000>; | |
596 | ||
597 | mcp_rtc: rtc@6f { | |
598 | compatible = "microchip,mcp7941x"; | |
599 | reg = <0x6f>; | |
c22c7f3e NM |
600 | interrupts-extended = <&crossbar_mpu GIC_SPI 2 IRQ_TYPE_EDGE_RISING>, |
601 | <&dra7_pmx_core 0x424>; | |
51c4cfef | 602 | interrupt-names = "irq", "wakeup"; |
5a0f93c6 NM |
603 | |
604 | pinctrl-names = "default"; | |
605 | pinctrl-0 = <&mcp79410_pins_default>; | |
606 | ||
607 | vcc-supply = <&vdd_3v3>; | |
608 | wakeup-source; | |
609 | }; | |
610 | }; | |
611 | ||
612 | &gpio7 { | |
613 | ti,no-reset-on-init; | |
614 | ti,no-idle-on-init; | |
615 | }; | |
616 | ||
617 | &cpu0 { | |
618 | cpu0-supply = <&smps12_reg>; | |
619 | voltage-tolerance = <1>; | |
620 | }; | |
621 | ||
622 | &uart3 { | |
623 | status = "okay"; | |
783d3186 | 624 | interrupts-extended = <&crossbar_mpu GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, |
5eb67198 | 625 | <&dra7_pmx_core 0x3f8>; |
5a0f93c6 NM |
626 | |
627 | pinctrl-names = "default"; | |
628 | pinctrl-0 = <&uart3_pins_default>; | |
629 | }; | |
630 | ||
a75dacf8 FB |
631 | &mac { |
632 | status = "okay"; | |
633 | pinctrl-names = "default", "sleep"; | |
634 | pinctrl-0 = <&cpsw_pins_default>; | |
635 | pinctrl-1 = <&cpsw_pins_sleep>; | |
636 | dual_emac; | |
637 | }; | |
638 | ||
639 | &cpsw_emac0 { | |
640 | phy_id = <&davinci_mdio>, <1>; | |
641 | phy-mode = "rgmii"; | |
642 | dual_emac_res_vlan = <1>; | |
643 | }; | |
644 | ||
645 | &cpsw_emac1 { | |
646 | phy_id = <&davinci_mdio>, <2>; | |
647 | phy-mode = "rgmii"; | |
648 | dual_emac_res_vlan = <2>; | |
649 | }; | |
650 | ||
651 | &davinci_mdio { | |
652 | pinctrl-names = "default", "sleep"; | |
653 | pinctrl-0 = <&davinci_mdio_pins_default>; | |
654 | pinctrl-1 = <&davinci_mdio_pins_sleep>; | |
655 | }; | |
656 | ||
5a0f93c6 NM |
657 | &mmc1 { |
658 | status = "okay"; | |
659 | ||
660 | pinctrl-names = "default"; | |
661 | pinctrl-0 = <&mmc1_pins_default>; | |
662 | ||
663 | vmmc-supply = <&ldo1_reg>; | |
5a0f93c6 | 664 | bus-width = <4>; |
267068d8 | 665 | cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>; /* gpio 219 */ |
5a0f93c6 NM |
666 | }; |
667 | ||
668 | &mmc2 { | |
669 | status = "okay"; | |
670 | ||
671 | pinctrl-names = "default"; | |
672 | pinctrl-0 = <&mmc2_pins_default>; | |
673 | ||
674 | vmmc-supply = <&vdd_3v3>; | |
675 | bus-width = <8>; | |
676 | ti,non-removable; | |
677 | cap-mmc-dual-data-rate; | |
678 | }; | |
679 | ||
680 | &sata { | |
681 | status = "okay"; | |
682 | }; | |
683 | ||
684 | &usb2_phy1 { | |
685 | phy-supply = <&ldousb_reg>; | |
686 | }; | |
687 | ||
9ab402ae RQ |
688 | &usb2_phy2 { |
689 | phy-supply = <&ldousb_reg>; | |
690 | }; | |
691 | ||
5a0f93c6 NM |
692 | &usb1 { |
693 | dr_mode = "host"; | |
694 | pinctrl-names = "default"; | |
695 | pinctrl-0 = <&usb1_pins>; | |
696 | }; | |
f60db98e | 697 | |
a7b0aa19 RQ |
698 | &omap_dwc3_2 { |
699 | extcon = <&extcon_usb2>; | |
700 | }; | |
701 | ||
726806ad | 702 | &usb2 { |
84ad1bab RQ |
703 | /* |
704 | * Stand alone usage is peripheral only. | |
705 | * However, with some resistor modifications | |
706 | * this port can be used via expansion connectors | |
707 | * as "host" or "dual-role". If so, provide | |
708 | * the necessary dr_mode override in the expansion | |
709 | * board's DT. | |
710 | */ | |
726806ad RQ |
711 | dr_mode = "peripheral"; |
712 | }; | |
d723cfea NM |
713 | |
714 | &cpu_trips { | |
715 | cpu_alert1: cpu_alert1 { | |
716 | temperature = <50000>; /* millicelsius */ | |
717 | hysteresis = <2000>; /* millicelsius */ | |
718 | type = "active"; | |
719 | }; | |
720 | }; | |
721 | ||
722 | &cpu_cooling_maps { | |
723 | map1 { | |
724 | trip = <&cpu_alert1>; | |
725 | cooling-device = <&gpio_fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; | |
726 | }; | |
727 | }; | |
728 | ||
729 | &thermal_zones { | |
730 | board_thermal: board_thermal { | |
731 | polling-delay-passive = <1250>; /* milliseconds */ | |
732 | polling-delay = <1500>; /* milliseconds */ | |
733 | ||
734 | /* sensor ID */ | |
735 | thermal-sensors = <&tmp102 0>; | |
736 | ||
737 | board_trips: trips { | |
738 | board_alert0: board_alert { | |
739 | temperature = <40000>; /* millicelsius */ | |
740 | hysteresis = <2000>; /* millicelsius */ | |
741 | type = "active"; | |
742 | }; | |
743 | ||
744 | board_crit: board_crit { | |
745 | temperature = <105000>; /* millicelsius */ | |
746 | hysteresis = <0>; /* millicelsius */ | |
747 | type = "critical"; | |
748 | }; | |
749 | }; | |
750 | ||
751 | board_cooling_maps: cooling-maps { | |
752 | map0 { | |
753 | trip = <&board_alert0>; | |
754 | cooling-device = | |
755 | <&gpio_fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; | |
756 | }; | |
757 | }; | |
758 | }; | |
759 | }; | |
0c534938 TV |
760 | |
761 | &dss { | |
762 | status = "ok"; | |
763 | ||
764 | vdda_video-supply = <&ldoln_reg>; | |
765 | }; | |
766 | ||
767 | &hdmi { | |
768 | status = "ok"; | |
5005296e | 769 | vdda-supply = <&ldo4_reg>; |
0c534938 TV |
770 | |
771 | pinctrl-names = "default"; | |
772 | pinctrl-0 = <&hdmi_pins>; | |
773 | ||
774 | port { | |
775 | hdmi_out: endpoint { | |
776 | remote-endpoint = <&tpd12s015_in>; | |
777 | }; | |
778 | }; | |
779 | }; | |
73c8f0cb KVA |
780 | |
781 | &pcie1 { | |
782 | gpios = <&gpio2 8 GPIO_ACTIVE_LOW>; | |
783 | }; | |
a00e368c PU |
784 | |
785 | &mcasp3 { | |
786 | #sound-dai-cells = <0>; | |
787 | pinctrl-names = "default", "sleep"; | |
788 | pinctrl-0 = <&mcasp3_pins_default>; | |
789 | pinctrl-1 = <&mcasp3_pins_sleep>; | |
bf26927b PU |
790 | assigned-clocks = <&mcasp3_ahclkx_mux>; |
791 | assigned-clock-parents = <&sys_clkin2>; | |
a00e368c PU |
792 | status = "okay"; |
793 | ||
794 | op-mode = <0>; /* MCASP_IIS_MODE */ | |
795 | tdm-slots = <2>; | |
796 | /* 4 serializers */ | |
797 | serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ | |
798 | 1 2 0 0 | |
799 | >; | |
42b2274d PU |
800 | tx-num-evt = <32>; |
801 | rx-num-evt = <32>; | |
a00e368c | 802 | }; |
ebbf93f0 SA |
803 | |
804 | &mailbox5 { | |
805 | status = "okay"; | |
806 | mbox_ipu1_ipc3x: mbox_ipu1_ipc3x { | |
807 | status = "okay"; | |
808 | }; | |
809 | mbox_dsp1_ipc3x: mbox_dsp1_ipc3x { | |
810 | status = "okay"; | |
811 | }; | |
812 | }; | |
813 | ||
814 | &mailbox6 { | |
815 | status = "okay"; | |
816 | mbox_ipu2_ipc3x: mbox_ipu2_ipc3x { | |
817 | status = "okay"; | |
818 | }; | |
819 | mbox_dsp2_ipc3x: mbox_dsp2_ipc3x { | |
820 | status = "okay"; | |
821 | }; | |
822 | }; |