pwm: Update DT bindings to reference pwm.txt for cells documentation
[deliverable/linux.git] / arch / arm / boot / dts / armada-370-db.dts
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1/*
2 * Device Tree file for Marvell Armada 370 evaluation board
3 * (DB-88F6710-BP-DDR3)
4 *
5 * Copyright (C) 2012 Marvell
6 *
7 * Lior Amsalem <alior@marvell.com>
8 * Gregory CLEMENT <gregory.clement@free-electrons.com>
9 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
10 *
11 * This file is licensed under the terms of the GNU General Public
12 * License version 2. This program is licensed "as is" without any
13 * warranty of any kind, whether express or implied.
14 */
15
16/dts-v1/;
17/include/ "armada-370.dtsi"
18
19/ {
20 model = "Marvell Armada 370 Evaluation Board";
21 compatible = "marvell,a370-db", "marvell,armada370", "marvell,armada-370-xp";
22
23 chosen {
24 bootargs = "console=ttyS0,115200 earlyprintk";
25 };
26
27 memory {
28 device_type = "memory";
11d5993d 29 reg = <0x00000000 0x40000000>; /* 1 GB */
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30 };
31
32 soc {
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33 internal-regs {
34 serial@12000 {
35 clock-frequency = <200000000>;
36 status = "okay";
f01959a9 37 };
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38 sata@a0000 {
39 nr-ports = <2>;
40 status = "okay";
f01959a9 41 };
f01959a9 42
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43 mdio {
44 phy0: ethernet-phy@0 {
45 reg = <0>;
46 };
b6150c71 47
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48 phy1: ethernet-phy@1 {
49 reg = <1>;
50 };
51 };
200506b1 52
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53 ethernet@70000 {
54 status = "okay";
55 phy = <&phy0>;
56 phy-mode = "rgmii-id";
57 };
58 ethernet@74000 {
59 status = "okay";
60 phy = <&phy1>;
61 phy-mode = "rgmii-id";
62 };
200506b1 63
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64 mvsdio@d4000 {
65 pinctrl-0 = <&sdio_pins1>;
66 pinctrl-names = "default";
67 /*
68 * This device is disabled by default, because
69 * using the SD card connector requires
70 * changing the default CON40 connector
71 * "DB-88F6710_MPP_2xRGMII_DEVICE_Jumper" to a
72 * different connector
73 * "DB-88F6710_MPP_RGMII_SD_Jumper".
74 */
75 status = "disabled";
76 /* No CD or WP GPIOs */
d87b5fbb 77 broken-cd;
467f54b2 78 };
04e09b72 79
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80 usb@50000 {
81 status = "okay";
82 };
04e09b72 83
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84 usb@51000 {
85 status = "okay";
04e09b72 86 };
3b723ae8 87
467f54b2 88 spi0: spi@10600 {
3b723ae8 89 status = "okay";
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90
91 spi-flash@0 {
92 #address-cells = <1>;
93 #size-cells = <1>;
94 compatible = "mx25l25635e";
95 reg = <0>; /* Chip select 0 */
96 spi-max-frequency = <50000000>;
97 };
3b723ae8 98 };
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99
100 pcie-controller {
3b723ae8 101 status = "okay";
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102 /*
103 * The two PCIe units are accessible through
104 * both standard PCIe slots and mini-PCIe
105 * slots on the board.
106 */
107 pcie@1,0 {
108 /* Port 0, Lane 0 */
109 status = "okay";
110 };
111 pcie@2,0 {
112 /* Port 1, Lane 0 */
113 status = "okay";
114 };
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115 };
116 };
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117 };
118};
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