Merge tag 'regmap-v3.11' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie...
[deliverable/linux.git] / arch / arm / boot / dts / armada-370-rd.dts
CommitLineData
49122145
FF
1/*
2 * Device Tree file for Marvell Armada 370 Reference Design board
3 * (RD-88F6710-A1)
4 *
5 * Copied from arch/arm/boot/dts/armada-370-db.dts
6 *
7 * Copyright (C) 2013 Florian Fainelli <florian@openwrt.org>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14/dts-v1/;
15/include/ "armada-370.dtsi"
16
17/ {
18 model = "Marvell Armada 370 Reference Design";
19 compatible = "marvell,a370-rd", "marvell,armada370", "marvell,armada-370-xp";
20
21 chosen {
22 bootargs = "console=ttyS0,115200 earlyprintk";
23 };
24
25 memory {
26 device_type = "memory";
27 reg = <0x00000000 0x20000000>; /* 512 MB */
28 };
29
30 soc {
467f54b2
GC
31 internal-regs {
32 serial@12000 {
33 clock-frequency = <200000000>;
34 status = "okay";
49122145 35 };
467f54b2
GC
36 sata@a0000 {
37 nr-ports = <2>;
38 status = "okay";
39 };
40
41 mdio {
42 phy0: ethernet-phy@0 {
43 reg = <0>;
44 };
49122145 45
467f54b2
GC
46 phy1: ethernet-phy@1 {
47 reg = <1>;
48 };
49122145 49 };
49122145 50
467f54b2
GC
51 ethernet@70000 {
52 status = "okay";
53 phy = <&phy0>;
54 phy-mode = "sgmii";
55 };
56 ethernet@74000 {
57 status = "okay";
58 phy = <&phy1>;
59 phy-mode = "rgmii-id";
60 };
56499120 61
467f54b2
GC
62 mvsdio@d4000 {
63 pinctrl-0 = <&sdio_pins1>;
64 pinctrl-names = "default";
65 status = "okay";
66 /* No CD or WP GPIOs */
d87b5fbb 67 broken-cd;
467f54b2 68 };
e822f75d 69
467f54b2
GC
70 usb@50000 {
71 status = "okay";
72 };
e822f75d 73
467f54b2
GC
74 usb@51000 {
75 status = "okay";
76 };
8c75e7b3 77
467f54b2
GC
78 gpio-keys {
79 compatible = "gpio-keys";
80 #address-cells = <1>;
81 #size-cells = <0>;
82 button@1 {
83 label = "Software Button";
84 linux,code = <116>;
85 gpios = <&gpio0 6 1>;
86 };
87 };
b848f622
TP
88
89 pcie-controller {
90 status = "okay";
91
92 /* Internal mini-PCIe connector */
93 pcie@1,0 {
94 /* Port 0, Lane 0 */
95 status = "okay";
96 };
97
98 /* Internal mini-PCIe connector */
99 pcie@2,0 {
100 /* Port 1, Lane 0 */
101 status = "okay";
102 };
103 };
8c75e7b3
EG
104 };
105 };
467f54b2 106 };
This page took 0.041284 seconds and 5 git commands to generate.