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49122145 FF |
1 | /* |
2 | * Device Tree file for Marvell Armada 370 Reference Design board | |
3 | * (RD-88F6710-A1) | |
4 | * | |
5 | * Copied from arch/arm/boot/dts/armada-370-db.dts | |
6 | * | |
7 | * Copyright (C) 2013 Florian Fainelli <florian@openwrt.org> | |
8 | * | |
7f2965ae GC |
9 | * This file is dual-licensed: you can use it either under the terms |
10 | * of the GPL or the X11 license, at your option. Note that this dual | |
11 | * licensing only applies to this file, and not this project as a | |
12 | * whole. | |
13 | * | |
14 | * a) This file is free software; you can redistribute it and/or | |
15 | * modify it under the terms of the GNU General Public License as | |
16 | * published by the Free Software Foundation; either version 2 of the | |
17 | * License, or (at your option) any later version. | |
18 | * | |
19 | * This file is distributed in the hope that it will be useful | |
20 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
21 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
22 | * GNU General Public License for more details. | |
23 | * | |
24 | * Or, alternatively | |
25 | * | |
26 | * b) Permission is hereby granted, free of charge, to any person | |
27 | * obtaining a copy of this software and associated documentation | |
28 | * files (the "Software"), to deal in the Software without | |
29 | * restriction, including without limitation the rights to use | |
30 | * copy, modify, merge, publish, distribute, sublicense, and/or | |
31 | * sell copies of the Software, and to permit persons to whom the | |
32 | * Software is furnished to do so, subject to the following | |
33 | * conditions: | |
34 | * | |
35 | * The above copyright notice and this permission notice shall be | |
36 | * included in all copies or substantial portions of the Software. | |
37 | * | |
38 | * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND | |
39 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES | |
40 | * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
41 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT | |
42 | * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY | |
43 | * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
44 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
45 | * OTHER DEALINGS IN THE SOFTWARE. | |
32c741d0 TP |
46 | * |
47 | * Note: this Device Tree assumes that the bootloader has remapped the | |
48 | * internal registers to 0xf1000000 (instead of the default | |
49 | * 0xd0000000). The 0xf1000000 is the default used by the recent, | |
50 | * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier | |
51 | * boards were delivered with an older version of the bootloader that | |
52 | * left internal registers mapped at 0xd0000000. If you are in this | |
53 | * situation, you should either update your bootloader (preferred | |
54 | * solution) or the below Device Tree should be adjusted. | |
49122145 FF |
55 | */ |
56 | ||
57 | /dts-v1/; | |
5c0169d1 | 58 | #include <dt-bindings/input/input.h> |
29e74f8b | 59 | #include <dt-bindings/gpio/gpio.h> |
38149887 | 60 | #include "armada-370.dtsi" |
49122145 FF |
61 | |
62 | / { | |
63 | model = "Marvell Armada 370 Reference Design"; | |
64 | compatible = "marvell,a370-rd", "marvell,armada370", "marvell,armada-370-xp"; | |
65 | ||
66 | chosen { | |
9552203c | 67 | stdout-path = "serial0:115200n8"; |
49122145 FF |
68 | }; |
69 | ||
70 | memory { | |
71 | device_type = "memory"; | |
72 | reg = <0x00000000 0x20000000>; /* 512 MB */ | |
73 | }; | |
74 | ||
75 | soc { | |
32c741d0 | 76 | ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000 |
b416f192 BB |
77 | MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000 |
78 | MBUS_ID(0x09, 0x01) 0 0xf1100000 0x10000>; | |
5e12a613 | 79 | |
0af83305 EG |
80 | pcie-controller { |
81 | status = "okay"; | |
82 | ||
83 | /* Internal mini-PCIe connector */ | |
84 | pcie@1,0 { | |
85 | /* Port 0, Lane 0 */ | |
86 | status = "okay"; | |
87 | }; | |
88 | ||
89 | /* Internal mini-PCIe connector */ | |
90 | pcie@2,0 { | |
91 | /* Port 1, Lane 0 */ | |
92 | status = "okay"; | |
93 | }; | |
94 | }; | |
95 | ||
467f54b2 GC |
96 | internal-regs { |
97 | serial@12000 { | |
467f54b2 | 98 | status = "okay"; |
49122145 | 99 | }; |
467f54b2 GC |
100 | sata@a0000 { |
101 | nr-ports = <2>; | |
102 | status = "okay"; | |
103 | }; | |
104 | ||
105 | mdio { | |
9dfb5c41 EG |
106 | pinctrl-0 = <&mdio_pins>; |
107 | pinctrl-names = "default"; | |
467f54b2 GC |
108 | phy0: ethernet-phy@0 { |
109 | reg = <0>; | |
110 | }; | |
49122145 | 111 | }; |
49122145 | 112 | |
467f54b2 GC |
113 | ethernet@70000 { |
114 | status = "okay"; | |
115 | phy = <&phy0>; | |
116 | phy-mode = "sgmii"; | |
117 | }; | |
118 | ethernet@74000 { | |
9dfb5c41 EG |
119 | pinctrl-0 = <&ge1_rgmii_pins>; |
120 | pinctrl-names = "default"; | |
467f54b2 | 121 | status = "okay"; |
467f54b2 | 122 | phy-mode = "rgmii-id"; |
9ef90cbb AL |
123 | fixed-link { |
124 | speed = <1000>; | |
125 | full-duplex; | |
126 | }; | |
467f54b2 | 127 | }; |
56499120 | 128 | |
467f54b2 GC |
129 | mvsdio@d4000 { |
130 | pinctrl-0 = <&sdio_pins1>; | |
131 | pinctrl-names = "default"; | |
132 | status = "okay"; | |
133 | /* No CD or WP GPIOs */ | |
d87b5fbb | 134 | broken-cd; |
467f54b2 | 135 | }; |
e822f75d | 136 | |
467f54b2 GC |
137 | usb@50000 { |
138 | status = "okay"; | |
139 | }; | |
e822f75d | 140 | |
467f54b2 GC |
141 | usb@51000 { |
142 | status = "okay"; | |
143 | }; | |
8c75e7b3 | 144 | |
467f54b2 GC |
145 | gpio-keys { |
146 | compatible = "gpio-keys"; | |
147 | #address-cells = <1>; | |
148 | #size-cells = <0>; | |
149 | button@1 { | |
150 | label = "Software Button"; | |
5c0169d1 | 151 | linux,code = <KEY_POWER>; |
29e74f8b | 152 | gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; |
467f54b2 GC |
153 | }; |
154 | }; | |
69e18e26 | 155 | |
e8db78dd TP |
156 | gpio-fan { |
157 | compatible = "gpio-fan"; | |
158 | gpios = <&gpio0 8 GPIO_ACTIVE_HIGH>; | |
159 | gpio-fan,speed-map = <0 0 3000 1>; | |
160 | pinctrl-0 = <&fan_pins>; | |
161 | pinctrl-names = "default"; | |
162 | }; | |
163 | ||
5b1e9e80 TP |
164 | gpio_leds { |
165 | compatible = "gpio-leds"; | |
166 | pinctrl-names = "default"; | |
167 | pinctrl-0 = <&led_pins>; | |
168 | ||
169 | sw_led { | |
170 | label = "370rd:green:sw"; | |
171 | gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; | |
172 | default-state = "keep"; | |
173 | }; | |
174 | }; | |
175 | ||
69e18e26 EG |
176 | nand@d0000 { |
177 | status = "okay"; | |
178 | num-cs = <1>; | |
179 | marvell,nand-keep-config; | |
180 | marvell,nand-enable-arbiter; | |
181 | nand-on-flash-bbt; | |
182 | ||
183 | partition@0 { | |
184 | label = "U-Boot"; | |
185 | reg = <0 0x800000>; | |
186 | }; | |
187 | partition@800000 { | |
188 | label = "Linux"; | |
189 | reg = <0x800000 0x800000>; | |
190 | }; | |
191 | partition@1000000 { | |
192 | label = "Filesystem"; | |
193 | reg = <0x1000000 0x3f000000>; | |
194 | }; | |
195 | }; | |
8c75e7b3 EG |
196 | }; |
197 | }; | |
9ef90cbb AL |
198 | |
199 | dsa@0 { | |
200 | compatible = "marvell,dsa"; | |
201 | #address-cells = <2>; | |
202 | #size-cells = <0>; | |
203 | ||
204 | dsa,ethernet = <ð1>; | |
205 | dsa,mii-bus = <&mdio>; | |
206 | ||
207 | switch@0 { | |
208 | #address-cells = <1>; | |
209 | #size-cells = <0>; | |
210 | reg = <0x10 0>; /* MDIO address 16, switch 0 in tree */ | |
211 | ||
212 | port@0 { | |
213 | reg = <0>; | |
214 | label = "lan0"; | |
215 | }; | |
216 | ||
217 | port@1 { | |
218 | reg = <1>; | |
219 | label = "lan1"; | |
220 | }; | |
221 | ||
222 | port@2 { | |
223 | reg = <2>; | |
224 | label = "lan2"; | |
225 | }; | |
226 | ||
227 | port@3 { | |
228 | reg = <3>; | |
229 | label = "lan3"; | |
230 | }; | |
231 | ||
232 | port@5 { | |
233 | reg = <5>; | |
234 | label = "cpu"; | |
235 | }; | |
236 | }; | |
237 | }; | |
467f54b2 | 238 | }; |
4904a82a AE |
239 | |
240 | &pinctrl { | |
241 | fan_pins: fan-pins { | |
242 | marvell,pins = "mpp8"; | |
243 | marvell,function = "gpio"; | |
244 | }; | |
245 | ||
246 | led_pins: led-pins { | |
247 | marvell,pins = "mpp32"; | |
248 | marvell,function = "gpio"; | |
249 | }; | |
250 | }; |