ARM: mvebu: Fix AXP-WiFi-AP DT for MBUS DT binding
[deliverable/linux.git] / arch / arm / boot / dts / armada-370-rd.dts
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1/*
2 * Device Tree file for Marvell Armada 370 Reference Design board
3 * (RD-88F6710-A1)
4 *
5 * Copied from arch/arm/boot/dts/armada-370-db.dts
6 *
7 * Copyright (C) 2013 Florian Fainelli <florian@openwrt.org>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14/dts-v1/;
38149887 15#include "armada-370.dtsi"
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16
17/ {
18 model = "Marvell Armada 370 Reference Design";
19 compatible = "marvell,a370-rd", "marvell,armada370", "marvell,armada-370-xp";
20
21 chosen {
22 bootargs = "console=ttyS0,115200 earlyprintk";
23 };
24
25 memory {
26 device_type = "memory";
27 reg = <0x00000000 0x20000000>; /* 512 MB */
28 };
29
30 soc {
0cd3754a
EG
31 ranges = <MBUS_ID(0xf0, 0x01) 0 0xd0000000 0x100000
32 MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000>;
5e12a613 33
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34 internal-regs {
35 serial@12000 {
36 clock-frequency = <200000000>;
37 status = "okay";
49122145 38 };
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39 sata@a0000 {
40 nr-ports = <2>;
41 status = "okay";
42 };
43
44 mdio {
45 phy0: ethernet-phy@0 {
46 reg = <0>;
47 };
49122145 48
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49 phy1: ethernet-phy@1 {
50 reg = <1>;
51 };
49122145 52 };
49122145 53
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54 ethernet@70000 {
55 status = "okay";
56 phy = <&phy0>;
57 phy-mode = "sgmii";
58 };
59 ethernet@74000 {
60 status = "okay";
61 phy = <&phy1>;
62 phy-mode = "rgmii-id";
63 };
56499120 64
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65 mvsdio@d4000 {
66 pinctrl-0 = <&sdio_pins1>;
67 pinctrl-names = "default";
68 status = "okay";
69 /* No CD or WP GPIOs */
d87b5fbb 70 broken-cd;
467f54b2 71 };
e822f75d 72
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73 usb@50000 {
74 status = "okay";
75 };
e822f75d 76
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77 usb@51000 {
78 status = "okay";
79 };
8c75e7b3 80
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81 gpio-keys {
82 compatible = "gpio-keys";
83 #address-cells = <1>;
84 #size-cells = <0>;
85 button@1 {
86 label = "Software Button";
87 linux,code = <116>;
88 gpios = <&gpio0 6 1>;
89 };
90 };
b848f622
TP
91
92 pcie-controller {
93 status = "okay";
94
95 /* Internal mini-PCIe connector */
96 pcie@1,0 {
97 /* Port 0, Lane 0 */
98 status = "okay";
99 };
100
101 /* Internal mini-PCIe connector */
102 pcie@2,0 {
103 /* Port 1, Lane 0 */
104 status = "okay";
105 };
106 };
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107 };
108 };
467f54b2 109 };
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