[deliverable/linux.git] / arch / arm / boot / dts / armada-370-xp.dtsi

/*
 * Device Tree Include file for Marvell Armada 370 and Armada XP SoC
 *
 * Copyright (C) 2012 Marvell
 *
 * Lior Amsalem <alior@marvell.com>
 * Gregory CLEMENT <gregory.clement@free-electrons.com>
 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
 * Ben Dooks <ben.dooks@codethink.co.uk>
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2.  This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 *
 * This file contains the definitions that are common to the Armada
 * 370 and Armada XP SoC.
 */

/include/ "skeleton64.dtsi"

/ {
	model = "Marvell Armada 370 and XP SoC";
	compatible = "marvell,armada-370-xp";

	aliases {
		eth0 = &eth0;
		eth1 = &eth1;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		cpu@0 {
			compatible = "marvell,sheeva-v7";
			device_type = "cpu";
			reg = <0>;
		};
	};

	soc {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "simple-bus";
		interrupt-parent = <&mpic>;
		ranges = <0          0 0xd0000000 0x0100000 /* internal registers */
			  0xe0000000 0 0xe0000000 0x8100000 /* PCIe */>;

		internal-regs {
			compatible = "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

			mpic: interrupt-controller@20000 {
				compatible = "marvell,mpic";
				#interrupt-cells = <1>;
				#size-cells = <1>;
				interrupt-controller;
			};

			coherency-fabric@20200 {
				compatible = "marvell,coherency-fabric";
				reg = <0x20200 0xb0>, <0x21810 0x1c>;
			};

			serial@12000 {
				compatible = "snps,dw-apb-uart";
				reg = <0x12000 0x100>;
				reg-shift = <2>;
				interrupts = <41>;
				reg-io-width = <1>;
				status = "disabled";
			};
			serial@12100 {
				compatible = "snps,dw-apb-uart";
				reg = <0x12100 0x100>;
				reg-shift = <2>;
				interrupts = <42>;
				reg-io-width = <1>;
				status = "disabled";
			};

			timer@20300 {
				compatible = "marvell,armada-370-xp-timer";
				reg = <0x20300 0x30>, <0x21040 0x30>;
				interrupts = <37>, <38>, <39>, <40>, <5>, <6>;
				clocks = <&coreclk 2>;
			};

			sata@a0000 {
				compatible = "marvell,orion-sata";
				reg = <0xa0000 0x5000>;
				interrupts = <55>;
				clocks = <&gateclk 15>, <&gateclk 30>;
				clock-names = "0", "1";
				status = "disabled";
			};

			mdio {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "marvell,orion-mdio";
				reg = <0x72004 0x4>;
			};

			eth0: ethernet@70000 {
				compatible = "marvell,armada-370-neta";
				reg = <0x70000 0x4000>;
				interrupts = <8>;
				clocks = <&gateclk 4>;
				status = "disabled";
			};

			eth1: ethernet@74000 {
				compatible = "marvell,armada-370-neta";
				reg = <0x74000 0x4000>;
				interrupts = <10>;
				clocks = <&gateclk 3>;
				status = "disabled";
			};

			i2c0: i2c@11000 {
				compatible = "marvell,mv64xxx-i2c";
				reg = <0x11000 0x20>;
				#address-cells = <1>;
				#size-cells = <0>;
				interrupts = <31>;
				timeout-ms = <1000>;
				clocks = <&coreclk 0>;
				status = "disabled";
			};

			i2c1: i2c@11100 {
				compatible = "marvell,mv64xxx-i2c";
				reg = <0x11100 0x20>;
				#address-cells = <1>;
				#size-cells = <0>;
				interrupts = <32>;
				timeout-ms = <1000>;
				clocks = <&coreclk 0>;
				status = "disabled";
			};

			rtc@10300 {
				compatible = "marvell,orion-rtc";
				reg = <0x10300 0x20>;
				interrupts = <50>;
			};

			mvsdio@d4000 {
				compatible = "marvell,orion-sdio";
				reg = <0xd4000 0x200>;
				interrupts = <54>;
				clocks = <&gateclk 17>;
				bus-width = <4>;
				cap-sdio-irq;
				cap-sd-highspeed;
				cap-mmc-highspeed;
				status = "disabled";
			};

			usb@50000 {
				compatible = "marvell,orion-ehci";
				reg = <0x50000 0x500>;
				interrupts = <45>;
				status = "disabled";
			};

			usb@51000 {
				compatible = "marvell,orion-ehci";
				reg = <0x51000 0x500>;
				interrupts = <46>;
				status = "disabled";
			};

			spi0: spi@10600 {
				compatible = "marvell,orion-spi";
				reg = <0x10600 0x28>;
				#address-cells = <1>;
				#size-cells = <0>;
				cell-index = <0>;
				interrupts = <30>;
				clocks = <&coreclk 0>;
				status = "disabled";
			};

			spi1: spi@10680 {
				compatible = "marvell,orion-spi";
				reg = <0x10680 0x28>;
				#address-cells = <1>;
				#size-cells = <0>;
				cell-index = <1>;
				interrupts = <92>;
				clocks = <&coreclk 0>;
				status = "disabled";
			};

			devbus-bootcs@10400 {
				compatible = "marvell,mvebu-devbus";
				reg = <0x10400 0x8>;
				#address-cells = <1>;
				#size-cells = <1>;
				clocks = <&coreclk 0>;
				status = "disabled";
			};

			devbus-cs0@10408 {
				compatible = "marvell,mvebu-devbus";
				reg = <0x10408 0x8>;
				#address-cells = <1>;
				#size-cells = <1>;
				clocks = <&coreclk 0>;
				status = "disabled";
			};

			devbus-cs1@10410 {
				compatible = "marvell,mvebu-devbus";
				reg = <0x10410 0x8>;
				#address-cells = <1>;
				#size-cells = <1>;
				clocks = <&coreclk 0>;
				status = "disabled";
			};

			devbus-cs2@10418 {
				compatible = "marvell,mvebu-devbus";
				reg = <0x10418 0x8>;
				#address-cells = <1>;
				#size-cells = <1>;
				clocks = <&coreclk 0>;
				status = "disabled";
			};

			devbus-cs3@10420 {
				compatible = "marvell,mvebu-devbus";
				reg = <0x10420 0x8>;
				#address-cells = <1>;
				#size-cells = <1>;
				clocks = <&coreclk 0>;
				status = "disabled";
			};
		};
	};
 };
Commit	Line	Data
9ae6f740 TP	1	/*
	2	* Device Tree Include file for Marvell Armada 370 and Armada XP SoC
	3	*
	4	* Copyright (C) 2012 Marvell
	5	*
	6	* Lior Amsalem <alior@marvell.com>
	7	* Gregory CLEMENT <gregory.clement@free-electrons.com>
	8	* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
	9	* Ben Dooks <ben.dooks@codethink.co.uk>
	10	*
	11	* This file is licensed under the terms of the GNU General Public
	12	* License version 2. This program is licensed "as is" without any
	13	* warranty of any kind, whether express or implied.
	14	*
	15	* This file contains the definitions that are common to the Armada
	16	* 370 and Armada XP SoC.
	17	*/
	18
74898364	19	/include/ "skeleton64.dtsi"
9ae6f740 TP	20
	21	/ {
	22	model = "Marvell Armada 370 and XP SoC";
92ece1cd	23	compatible = "marvell,armada-370-xp";
9ae6f740	24
be5a9389 WT	25	aliases {
	26	eth0 = &eth0;
	27	eth1 = &eth1;
	28	};
	29
9ae6f740	30	cpus {
7a7ed290 LP	31	#address-cells = <1>;
7a7ed290 LP	32	#size-cells = <0>;
9ae6f740 TP	33	cpu@0 {
9ae6f740 TP	34	compatible = "marvell,sheeva-v7";
7a7ed290 LP	35	device_type = "cpu";
7a7ed290 LP	36	reg = <0>;
9ae6f740 TP	37	};
	38	};
	39
9ae6f740 TP	40	soc {
	41	#address-cells = <1>;
	42	#size-cells = <1>;
	43	compatible = "simple-bus";
	44	interrupt-parent = <&mpic>;
8eed481e TP	45	ranges = <0 0 0xd0000000 0x0100000 /* internal registers */
8eed481e TP	46	0xe0000000 0 0xe0000000 0x8100000 /* PCIe */>;
9ae6f740	47
467f54b2 GC	48	internal-regs {
	49	compatible = "simple-bus";
	50	#address-cells = <1>;
	51	#size-cells = <1>;
	52	ranges;
	53
	54	mpic: interrupt-controller@20000 {
82a68267 GC	55	compatible = "marvell,mpic";
	56	#interrupt-cells = <1>;
	57	#size-cells = <1>;
	58	interrupt-controller;
467f54b2	59	};
b18ea4dc	60
467f54b2	61	coherency-fabric@20200 {
82a68267	62	compatible = "marvell,coherency-fabric";
467f54b2 GC	63	reg = <0x20200 0xb0>, <0x21810 0x1c>;
467f54b2 GC	64	};
b18ea4dc	65
467f54b2	66	serial@12000 {
b24212fb	67	compatible = "snps,dw-apb-uart";
82a68267	68	reg = <0x12000 0x100>;
9ae6f740 TP	69	reg-shift = <2>;
9ae6f740 TP	70	interrupts = <41>;
e366154f	71	reg-io-width = <1>;
9ae6f740	72	status = "disabled";
467f54b2 GC	73	};
467f54b2 GC	74	serial@12100 {
b24212fb	75	compatible = "snps,dw-apb-uart";
82a68267	76	reg = <0x12100 0x100>;
9ae6f740 TP	77	reg-shift = <2>;
9ae6f740 TP	78	interrupts = <42>;
e366154f	79	reg-io-width = <1>;
9ae6f740	80	status = "disabled";
467f54b2 GC	81	};
	82
	83	timer@20300 {
	84	compatible = "marvell,armada-370-xp-timer";
	85	reg = <0x20300 0x30>, <0x21040 0x30>;
	86	interrupts = <37>, <38>, <39>, <40>, <5>, <6>;
	87	clocks = <&coreclk 2>;
	88	};
	89
	90	sata@a0000 {
	91	compatible = "marvell,orion-sata";
911492de	92	reg = <0xa0000 0x5000>;
467f54b2 GC	93	interrupts = <55>;
	94	clocks = <&gateclk 15>, <&gateclk 30>;
	95	clock-names = "0", "1";
	96	status = "disabled";
	97	};
a6a6de1a	98
467f54b2 GC	99	mdio {
	100	#address-cells = <1>;
	101	#size-cells = <0>;
	102	compatible = "marvell,orion-mdio";
	103	reg = <0x72004 0x4>;
	104	};
323c1010	105
be5a9389	106	eth0: ethernet@70000 {
323c1010	107	compatible = "marvell,armada-370-neta";
cf8088c5	108	reg = <0x70000 0x4000>;
323c1010	109	interrupts = <8>;
4aa935a2	110	clocks = <&gateclk 4>;
323c1010	111	status = "disabled";
467f54b2	112	};
323c1010	113
be5a9389	114	eth1: ethernet@74000 {
323c1010	115	compatible = "marvell,armada-370-neta";
cf8088c5	116	reg = <0x74000 0x4000>;
323c1010	117	interrupts = <10>;
4aa935a2	118	clocks = <&gateclk 3>;
323c1010	119	status = "disabled";
467f54b2 GC	120	};
	121
	122	i2c0: i2c@11000 {
	123	compatible = "marvell,mv64xxx-i2c";
	124	reg = <0x11000 0x20>;
	125	#address-cells = <1>;
	126	#size-cells = <0>;
	127	interrupts = <31>;
	128	timeout-ms = <1000>;
	129	clocks = <&coreclk 0>;
	130	status = "disabled";
	131	};
	132
	133	i2c1: i2c@11100 {
	134	compatible = "marvell,mv64xxx-i2c";
	135	reg = <0x11100 0x20>;
	136	#address-cells = <1>;
	137	#size-cells = <0>;
	138	interrupts = <32>;
	139	timeout-ms = <1000>;
	140	clocks = <&coreclk 0>;
	141	status = "disabled";
	142	};
	143
	144	rtc@10300 {
	145	compatible = "marvell,orion-rtc";
	146	reg = <0x10300 0x20>;
	147	interrupts = <50>;
	148	};
	149
	150	mvsdio@d4000 {
	151	compatible = "marvell,orion-sdio";
	152	reg = <0xd4000 0x200>;
	153	interrupts = <54>;
	154	clocks = <&gateclk 17>;
d87b5fbb SB	155	bus-width = <4>;
	156	cap-sdio-irq;
	157	cap-sd-highspeed;
	158	cap-mmc-highspeed;
467f54b2 GC	159	status = "disabled";
467f54b2 GC	160	};
b2bb806f	161
467f54b2 GC	162	usb@50000 {
	163	compatible = "marvell,orion-ehci";
	164	reg = <0x50000 0x500>;
	165	interrupts = <45>;
	166	status = "disabled";
	167	};
d5dc035e	168
467f54b2 GC	169	usb@51000 {
	170	compatible = "marvell,orion-ehci";
	171	reg = <0x51000 0x500>;
	172	interrupts = <46>;
	173	status = "disabled";
	174	};
	175
	176	spi0: spi@10600 {
	177	compatible = "marvell,orion-spi";
	178	reg = <0x10600 0x28>;
	179	#address-cells = <1>;
	180	#size-cells = <0>;
	181	cell-index = <0>;
	182	interrupts = <30>;
	183	clocks = <&coreclk 0>;
	184	status = "disabled";
	185	};
	186
	187	spi1: spi@10680 {
	188	compatible = "marvell,orion-spi";
	189	reg = <0x10680 0x28>;
	190	#address-cells = <1>;
	191	#size-cells = <0>;
	192	cell-index = <1>;
	193	interrupts = <92>;
	194	clocks = <&coreclk 0>;
	195	status = "disabled";
	196	};
3d76e1f3	197
467f54b2 GC	198	devbus-bootcs@10400 {
	199	compatible = "marvell,mvebu-devbus";
	200	reg = <0x10400 0x8>;
	201	#address-cells = <1>;
	202	#size-cells = <1>;
	203	clocks = <&coreclk 0>;
	204	status = "disabled";
	205	};
3d76e1f3	206
467f54b2 GC	207	devbus-cs0@10408 {
	208	compatible = "marvell,mvebu-devbus";
	209	reg = <0x10408 0x8>;
	210	#address-cells = <1>;
	211	#size-cells = <1>;
	212	clocks = <&coreclk 0>;
	213	status = "disabled";
	214	};
3d76e1f3	215
467f54b2 GC	216	devbus-cs1@10410 {
	217	compatible = "marvell,mvebu-devbus";
	218	reg = <0x10410 0x8>;
	219	#address-cells = <1>;
	220	#size-cells = <1>;
	221	clocks = <&coreclk 0>;
	222	status = "disabled";
	223	};
3d76e1f3	224
467f54b2 GC	225	devbus-cs2@10418 {
	226	compatible = "marvell,mvebu-devbus";
	227	reg = <0x10418 0x8>;
	228	#address-cells = <1>;
	229	#size-cells = <1>;
	230	clocks = <&coreclk 0>;
	231	status = "disabled";
	232	};
3d76e1f3	233
467f54b2 GC	234	devbus-cs3@10420 {
	235	compatible = "marvell,mvebu-devbus";
	236	reg = <0x10420 0x8>;
	237	#address-cells = <1>;
	238	#size-cells = <1>;
	239	clocks = <&coreclk 0>;
	240	status = "disabled";
	241	};
3d76e1f3	242	};
9ae6f740	243	};
467f54b2	244	};