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9ae6f740 TP |
1 | /* |
2 | * Device Tree Include file for Marvell Armada 370 and Armada XP SoC | |
3 | * | |
4 | * Copyright (C) 2012 Marvell | |
5 | * | |
6 | * Lior Amsalem <alior@marvell.com> | |
7 | * Gregory CLEMENT <gregory.clement@free-electrons.com> | |
8 | * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> | |
9 | * Ben Dooks <ben.dooks@codethink.co.uk> | |
10 | * | |
11 | * This file is licensed under the terms of the GNU General Public | |
12 | * License version 2. This program is licensed "as is" without any | |
13 | * warranty of any kind, whether express or implied. | |
14 | * | |
15 | * This file contains the definitions that are common to the Armada | |
16 | * 370 and Armada XP SoC. | |
17 | */ | |
18 | ||
19 | /include/ "skeleton.dtsi" | |
20 | ||
21 | / { | |
22 | model = "Marvell Armada 370 and XP SoC"; | |
23 | compatible = "marvell,armada_370_xp"; | |
24 | ||
25 | cpus { | |
26 | cpu@0 { | |
27 | compatible = "marvell,sheeva-v7"; | |
28 | }; | |
29 | }; | |
30 | ||
31 | mpic: interrupt-controller@d0020000 { | |
32 | compatible = "marvell,mpic"; | |
33 | #interrupt-cells = <1>; | |
34 | #address-cells = <1>; | |
35 | #size-cells = <1>; | |
36 | interrupt-controller; | |
37 | }; | |
38 | ||
009f1315 GC |
39 | coherency-fabric@d0020200 { |
40 | compatible = "marvell,coherency-fabric"; | |
41 | reg = <0xd0020200 0xb0>; | |
42 | }; | |
43 | ||
9ae6f740 TP |
44 | soc { |
45 | #address-cells = <1>; | |
46 | #size-cells = <1>; | |
47 | compatible = "simple-bus"; | |
48 | interrupt-parent = <&mpic>; | |
49 | ranges; | |
50 | ||
51 | serial@d0012000 { | |
52 | compatible = "ns16550"; | |
53 | reg = <0xd0012000 0x100>; | |
54 | reg-shift = <2>; | |
55 | interrupts = <41>; | |
56 | status = "disabled"; | |
57 | }; | |
58 | serial@d0012100 { | |
59 | compatible = "ns16550"; | |
60 | reg = <0xd0012100 0x100>; | |
61 | reg-shift = <2>; | |
62 | interrupts = <42>; | |
63 | status = "disabled"; | |
64 | }; | |
65 | ||
66 | timer@d0020300 { | |
67 | compatible = "marvell,armada-370-xp-timer"; | |
68 | reg = <0xd0020300 0x30>; | |
69 | interrupts = <37>, <38>, <39>, <40>; | |
307c2bf4 | 70 | clocks = <&coreclk 2>; |
9ae6f740 | 71 | }; |
5b40baee TP |
72 | |
73 | addr-decoding@d0020000 { | |
74 | compatible = "marvell,armada-addr-decoding-controller"; | |
75 | reg = <0xd0020000 0x258>; | |
76 | }; | |
9ae6f740 TP |
77 | }; |
78 | }; | |
79 |