Commit | Line | Data |
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9ae6f740 TP |
1 | /* |
2 | * Device Tree Include file for Marvell Armada 370 family SoC | |
3 | * | |
4 | * Copyright (C) 2012 Marvell | |
5 | * | |
6 | * Lior Amsalem <alior@marvell.com> | |
7 | * Gregory CLEMENT <gregory.clement@free-electrons.com> | |
8 | * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> | |
9 | * | |
10 | * This file is licensed under the terms of the GNU General Public | |
11 | * License version 2. This program is licensed "as is" without any | |
12 | * warranty of any kind, whether express or implied. | |
13 | * | |
14 | * Contains definitions specific to the Armada 370 SoC that are not | |
15 | * common to all Armada SoCs. | |
16 | */ | |
17 | ||
38149887 | 18 | #include "armada-370-xp.dtsi" |
74898364 | 19 | /include/ "skeleton.dtsi" |
9ae6f740 TP |
20 | |
21 | / { | |
22 | model = "Marvell Armada 370 family SoC"; | |
23 | compatible = "marvell,armada370", "marvell,armada-370-xp"; | |
24 | ||
397d59f3 TP |
25 | aliases { |
26 | gpio0 = &gpio0; | |
27 | gpio1 = &gpio1; | |
28 | gpio2 = &gpio2; | |
29 | }; | |
30 | ||
9ae6f740 | 31 | soc { |
5e12a613 EG |
32 | compatible = "marvell,armada370-mbus", "simple-bus"; |
33 | ||
0cd3754a EG |
34 | bootrom { |
35 | compatible = "marvell,bootrom"; | |
36 | reg = <MBUS_ID(0x01, 0xe0) 0 0x100000>; | |
37 | }; | |
38 | ||
14fd8ed0 EG |
39 | pcie-controller { |
40 | compatible = "marvell,armada-370-pcie"; | |
41 | status = "disabled"; | |
42 | device_type = "pci"; | |
43 | ||
44 | #address-cells = <3>; | |
45 | #size-cells = <2>; | |
46 | ||
d4fa9941 | 47 | msi-parent = <&mpic>; |
14fd8ed0 EG |
48 | bus-range = <0x00 0xff>; |
49 | ||
50 | ranges = | |
51 | <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 | |
52 | 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 | |
53 | 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */ | |
54 | 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */ | |
55 | 0x82000000 0x2 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */ | |
56 | 0x81000000 0x2 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */>; | |
57 | ||
58 | pcie@1,0 { | |
59 | device_type = "pci"; | |
60 | assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; | |
61 | reg = <0x0800 0 0 0 0>; | |
62 | #address-cells = <3>; | |
63 | #size-cells = <2>; | |
64 | #interrupt-cells = <1>; | |
65 | ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 | |
66 | 0x81000000 0 0 0x81000000 0x1 0 1 0>; | |
67 | interrupt-map-mask = <0 0 0 0>; | |
68 | interrupt-map = <0 0 0 0 &mpic 58>; | |
69 | marvell,pcie-port = <0>; | |
70 | marvell,pcie-lane = <0>; | |
71 | clocks = <&gateclk 5>; | |
72 | status = "disabled"; | |
73 | }; | |
74 | ||
75 | pcie@2,0 { | |
76 | device_type = "pci"; | |
77 | assigned-addresses = <0x82002800 0 0x80000 0 0x2000>; | |
78 | reg = <0x1000 0 0 0 0>; | |
79 | #address-cells = <3>; | |
80 | #size-cells = <2>; | |
81 | #interrupt-cells = <1>; | |
82 | ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 | |
83 | 0x81000000 0 0 0x81000000 0x2 0 1 0>; | |
84 | interrupt-map-mask = <0 0 0 0>; | |
85 | interrupt-map = <0 0 0 0 &mpic 62>; | |
86 | marvell,pcie-port = <1>; | |
87 | marvell,pcie-lane = <0>; | |
88 | clocks = <&gateclk 9>; | |
89 | status = "disabled"; | |
90 | }; | |
91 | }; | |
92 | ||
467f54b2 | 93 | internal-regs { |
467f54b2 GC |
94 | L2: l2-cache { |
95 | compatible = "marvell,aurora-outer-cache"; | |
489e138e | 96 | reg = <0x08000 0x1000>; |
467f54b2 GC |
97 | cache-id-part = <0x100>; |
98 | wt-override; | |
fa1b21d1 | 99 | }; |
879d68a4 | 100 | |
a095b1c7 JC |
101 | i2c0: i2c@11000 { |
102 | reg = <0x11000 0x20>; | |
103 | }; | |
104 | ||
105 | i2c1: i2c@11100 { | |
106 | reg = <0x11100 0x20>; | |
107 | }; | |
108 | ||
109 | system-controller@18200 { | |
110 | compatible = "marvell,armada-370-xp-system-controller"; | |
111 | reg = <0x18200 0x100>; | |
879d68a4 | 112 | }; |
397d59f3 | 113 | |
467f54b2 GC |
114 | pinctrl { |
115 | compatible = "marvell,mv88f6710-pinctrl"; | |
116 | reg = <0x18000 0x38>; | |
117 | ||
118 | sdio_pins1: sdio-pins1 { | |
119 | marvell,pins = "mpp9", "mpp11", "mpp12", | |
120 | "mpp13", "mpp14", "mpp15"; | |
121 | marvell,function = "sd0"; | |
122 | }; | |
123 | ||
124 | sdio_pins2: sdio-pins2 { | |
125 | marvell,pins = "mpp47", "mpp48", "mpp49", | |
126 | "mpp50", "mpp51", "mpp52"; | |
127 | marvell,function = "sd0"; | |
128 | }; | |
129 | ||
130 | sdio_pins3: sdio-pins3 { | |
131 | marvell,pins = "mpp48", "mpp49", "mpp50", | |
132 | "mpp51", "mpp52", "mpp53"; | |
133 | marvell,function = "sd0"; | |
134 | }; | |
0122eee8 | 135 | }; |
0122eee8 | 136 | |
467f54b2 GC |
137 | gpio0: gpio@18100 { |
138 | compatible = "marvell,orion-gpio"; | |
139 | reg = <0x18100 0x40>; | |
140 | ngpios = <32>; | |
141 | gpio-controller; | |
142 | #gpio-cells = <2>; | |
143 | interrupt-controller; | |
ca60985c | 144 | #interrupt-cells = <2>; |
467f54b2 | 145 | interrupts = <82>, <83>, <84>, <85>; |
0122eee8 | 146 | }; |
b2bb806f | 147 | |
467f54b2 GC |
148 | gpio1: gpio@18140 { |
149 | compatible = "marvell,orion-gpio"; | |
150 | reg = <0x18140 0x40>; | |
151 | ngpios = <32>; | |
152 | gpio-controller; | |
153 | #gpio-cells = <2>; | |
154 | interrupt-controller; | |
ca60985c | 155 | #interrupt-cells = <2>; |
467f54b2 GC |
156 | interrupts = <87>, <88>, <89>, <90>; |
157 | }; | |
b2bb806f | 158 | |
467f54b2 GC |
159 | gpio2: gpio@18180 { |
160 | compatible = "marvell,orion-gpio"; | |
161 | reg = <0x18180 0x40>; | |
162 | ngpios = <2>; | |
163 | gpio-controller; | |
164 | #gpio-cells = <2>; | |
165 | interrupt-controller; | |
ca60985c | 166 | #interrupt-cells = <2>; |
467f54b2 GC |
167 | interrupts = <91>; |
168 | }; | |
a09a0b7c | 169 | |
a095b1c7 JC |
170 | gateclk: clock-gating-control@18220 { |
171 | compatible = "marvell,armada-370-gating-clock"; | |
172 | reg = <0x18220 0x4>; | |
173 | clocks = <&coreclk 0>; | |
174 | #clock-cells = <1>; | |
5d3b8830 EG |
175 | }; |
176 | ||
467f54b2 GC |
177 | coreclk: mvebu-sar@18230 { |
178 | compatible = "marvell,armada-370-core-clock"; | |
179 | reg = <0x18230 0x08>; | |
180 | #clock-cells = <1>; | |
181 | }; | |
a09a0b7c | 182 | |
a095b1c7 JC |
183 | thermal@18300 { |
184 | compatible = "marvell,armada370-thermal"; | |
185 | reg = <0x18300 0x4 | |
186 | 0x18304 0x4>; | |
187 | status = "okay"; | |
188 | }; | |
189 | ||
190 | interrupt-controller@20000 { | |
191 | reg = <0x20a00 0x1d0>, <0x21870 0x58>; | |
192 | }; | |
193 | ||
194 | timer@20300 { | |
195 | compatible = "marvell,armada-370-timer"; | |
196 | clocks = <&coreclk 2>; | |
197 | }; | |
198 | ||
199 | usb@50000 { | |
200 | clocks = <&coreclk 0>; | |
201 | }; | |
202 | ||
203 | usb@51000 { | |
467f54b2 | 204 | clocks = <&coreclk 0>; |
467f54b2 | 205 | }; |
a09a0b7c | 206 | |
467f54b2 GC |
207 | xor@60800 { |
208 | compatible = "marvell,orion-xor"; | |
209 | reg = <0x60800 0x100 | |
210 | 0x60A00 0x100>; | |
211 | status = "okay"; | |
212 | ||
213 | xor00 { | |
214 | interrupts = <51>; | |
215 | dmacap,memcpy; | |
216 | dmacap,xor; | |
217 | }; | |
218 | xor01 { | |
219 | interrupts = <52>; | |
220 | dmacap,memcpy; | |
221 | dmacap,xor; | |
222 | dmacap,memset; | |
223 | }; | |
224 | }; | |
a09a0b7c | 225 | |
467f54b2 GC |
226 | xor@60900 { |
227 | compatible = "marvell,orion-xor"; | |
228 | reg = <0x60900 0x100 | |
229 | 0x60b00 0x100>; | |
230 | status = "okay"; | |
231 | ||
232 | xor10 { | |
233 | interrupts = <94>; | |
234 | dmacap,memcpy; | |
235 | dmacap,xor; | |
236 | }; | |
237 | xor11 { | |
238 | interrupts = <95>; | |
239 | dmacap,memcpy; | |
240 | dmacap,xor; | |
241 | dmacap,memset; | |
242 | }; | |
243 | }; | |
a09a0b7c | 244 | }; |
9ae6f740 TP |
245 | }; |
246 | }; |