Commit | Line | Data |
---|---|---|
9ae6f740 TP |
1 | /* |
2 | * Device Tree Include file for Marvell Armada 370 family SoC | |
3 | * | |
4 | * Copyright (C) 2012 Marvell | |
5 | * | |
6 | * Lior Amsalem <alior@marvell.com> | |
7 | * Gregory CLEMENT <gregory.clement@free-electrons.com> | |
8 | * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> | |
9 | * | |
e7ad1fdf GC |
10 | * This file is dual-licensed: you can use it either under the terms |
11 | * of the GPL or the X11 license, at your option. Note that this dual | |
12 | * licensing only applies to this file, and not this project as a | |
13 | * whole. | |
14 | * | |
15 | * a) This file is free software; you can redistribute it and/or | |
16 | * modify it under the terms of the GNU General Public License as | |
17 | * published by the Free Software Foundation; either version 2 of the | |
18 | * License, or (at your option) any later version. | |
19 | * | |
20 | * This file is distributed in the hope that it will be useful | |
21 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
22 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
23 | * GNU General Public License for more details. | |
24 | * | |
25 | * Or, alternatively | |
26 | * | |
27 | * b) Permission is hereby granted, free of charge, to any person | |
28 | * obtaining a copy of this software and associated documentation | |
29 | * files (the "Software"), to deal in the Software without | |
30 | * restriction, including without limitation the rights to use | |
31 | * copy, modify, merge, publish, distribute, sublicense, and/or | |
32 | * sell copies of the Software, and to permit persons to whom the | |
33 | * Software is furnished to do so, subject to the following | |
34 | * conditions: | |
35 | * | |
36 | * The above copyright notice and this permission notice shall be | |
37 | * included in all copies or substantial portions of the Software. | |
38 | * | |
39 | * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND | |
40 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES | |
41 | * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
42 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT | |
43 | * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY | |
44 | * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
45 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
46 | * OTHER DEALINGS IN THE SOFTWARE. | |
9ae6f740 TP |
47 | * |
48 | * Contains definitions specific to the Armada 370 SoC that are not | |
49 | * common to all Armada SoCs. | |
50 | */ | |
51 | ||
38149887 | 52 | #include "armada-370-xp.dtsi" |
74898364 | 53 | /include/ "skeleton.dtsi" |
9ae6f740 TP |
54 | |
55 | / { | |
56 | model = "Marvell Armada 370 family SoC"; | |
57 | compatible = "marvell,armada370", "marvell,armada-370-xp"; | |
58 | ||
397d59f3 TP |
59 | aliases { |
60 | gpio0 = &gpio0; | |
61 | gpio1 = &gpio1; | |
62 | gpio2 = &gpio2; | |
63 | }; | |
64 | ||
9ae6f740 | 65 | soc { |
5e12a613 EG |
66 | compatible = "marvell,armada370-mbus", "simple-bus"; |
67 | ||
0cd3754a EG |
68 | bootrom { |
69 | compatible = "marvell,bootrom"; | |
70 | reg = <MBUS_ID(0x01, 0xe0) 0 0x100000>; | |
71 | }; | |
72 | ||
14fd8ed0 EG |
73 | pcie-controller { |
74 | compatible = "marvell,armada-370-pcie"; | |
75 | status = "disabled"; | |
76 | device_type = "pci"; | |
77 | ||
78 | #address-cells = <3>; | |
79 | #size-cells = <2>; | |
80 | ||
d4fa9941 | 81 | msi-parent = <&mpic>; |
14fd8ed0 EG |
82 | bus-range = <0x00 0xff>; |
83 | ||
84 | ranges = | |
85 | <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 | |
86 | 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 | |
87 | 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */ | |
88 | 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */ | |
89 | 0x82000000 0x2 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */ | |
90 | 0x81000000 0x2 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */>; | |
91 | ||
92 | pcie@1,0 { | |
93 | device_type = "pci"; | |
94 | assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; | |
95 | reg = <0x0800 0 0 0 0>; | |
96 | #address-cells = <3>; | |
97 | #size-cells = <2>; | |
98 | #interrupt-cells = <1>; | |
99 | ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 | |
100 | 0x81000000 0 0 0x81000000 0x1 0 1 0>; | |
101 | interrupt-map-mask = <0 0 0 0>; | |
102 | interrupt-map = <0 0 0 0 &mpic 58>; | |
103 | marvell,pcie-port = <0>; | |
104 | marvell,pcie-lane = <0>; | |
105 | clocks = <&gateclk 5>; | |
106 | status = "disabled"; | |
107 | }; | |
108 | ||
109 | pcie@2,0 { | |
110 | device_type = "pci"; | |
111 | assigned-addresses = <0x82002800 0 0x80000 0 0x2000>; | |
112 | reg = <0x1000 0 0 0 0>; | |
113 | #address-cells = <3>; | |
114 | #size-cells = <2>; | |
115 | #interrupt-cells = <1>; | |
116 | ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 | |
117 | 0x81000000 0 0 0x81000000 0x2 0 1 0>; | |
118 | interrupt-map-mask = <0 0 0 0>; | |
119 | interrupt-map = <0 0 0 0 &mpic 62>; | |
120 | marvell,pcie-port = <1>; | |
121 | marvell,pcie-lane = <0>; | |
122 | clocks = <&gateclk 9>; | |
123 | status = "disabled"; | |
124 | }; | |
125 | }; | |
126 | ||
467f54b2 | 127 | internal-regs { |
467f54b2 GC |
128 | L2: l2-cache { |
129 | compatible = "marvell,aurora-outer-cache"; | |
489e138e | 130 | reg = <0x08000 0x1000>; |
467f54b2 | 131 | cache-id-part = <0x100>; |
292a3546 | 132 | cache-level = <2>; |
a9ce1afb | 133 | cache-unified; |
467f54b2 | 134 | wt-override; |
fa1b21d1 | 135 | }; |
879d68a4 | 136 | |
a6fa8475 AE |
137 | /* |
138 | * Default SPI pinctrl setting, can be overwritten on | |
139 | * board level if a different configuration is used. | |
140 | */ | |
141 | spi0: spi@10600 { | |
2d295928 GC |
142 | compatible = "marvell,armada-370-spi", |
143 | "marvell,orion-spi"; | |
a6fa8475 AE |
144 | pinctrl-0 = <&spi0_pins1>; |
145 | pinctrl-names = "default"; | |
146 | }; | |
147 | ||
148 | spi1: spi@10680 { | |
2d295928 GC |
149 | compatible = "marvell,armada-370-spi", |
150 | "marvell,orion-spi"; | |
a6fa8475 AE |
151 | pinctrl-0 = <&spi1_pins>; |
152 | pinctrl-names = "default"; | |
153 | }; | |
154 | ||
a095b1c7 JC |
155 | i2c0: i2c@11000 { |
156 | reg = <0x11000 0x20>; | |
157 | }; | |
158 | ||
159 | i2c1: i2c@11100 { | |
160 | reg = <0x11100 0x20>; | |
161 | }; | |
162 | ||
467f54b2 GC |
163 | gpio0: gpio@18100 { |
164 | compatible = "marvell,orion-gpio"; | |
165 | reg = <0x18100 0x40>; | |
166 | ngpios = <32>; | |
167 | gpio-controller; | |
168 | #gpio-cells = <2>; | |
169 | interrupt-controller; | |
ca60985c | 170 | #interrupt-cells = <2>; |
467f54b2 | 171 | interrupts = <82>, <83>, <84>, <85>; |
0122eee8 | 172 | }; |
b2bb806f | 173 | |
467f54b2 GC |
174 | gpio1: gpio@18140 { |
175 | compatible = "marvell,orion-gpio"; | |
176 | reg = <0x18140 0x40>; | |
177 | ngpios = <32>; | |
178 | gpio-controller; | |
179 | #gpio-cells = <2>; | |
180 | interrupt-controller; | |
ca60985c | 181 | #interrupt-cells = <2>; |
467f54b2 GC |
182 | interrupts = <87>, <88>, <89>, <90>; |
183 | }; | |
b2bb806f | 184 | |
467f54b2 GC |
185 | gpio2: gpio@18180 { |
186 | compatible = "marvell,orion-gpio"; | |
187 | reg = <0x18180 0x40>; | |
188 | ngpios = <2>; | |
189 | gpio-controller; | |
190 | #gpio-cells = <2>; | |
191 | interrupt-controller; | |
ca60985c | 192 | #interrupt-cells = <2>; |
467f54b2 GC |
193 | interrupts = <91>; |
194 | }; | |
a09a0b7c | 195 | |
f8afeaea AE |
196 | /* |
197 | * Default UART pinctrl setting without RTS/CTS, can | |
198 | * be overwritten on board level if a different | |
199 | * configuration is used. | |
200 | */ | |
201 | uart0: serial@12000 { | |
202 | pinctrl-0 = <&uart0_pins>; | |
203 | pinctrl-names = "default"; | |
204 | }; | |
205 | ||
206 | uart1: serial@12100 { | |
207 | pinctrl-0 = <&uart1_pins>; | |
208 | pinctrl-names = "default"; | |
209 | }; | |
210 | ||
ab1e8537 UKK |
211 | system-controller@18200 { |
212 | compatible = "marvell,armada-370-xp-system-controller"; | |
213 | reg = <0x18200 0x100>; | |
214 | }; | |
215 | ||
a095b1c7 JC |
216 | gateclk: clock-gating-control@18220 { |
217 | compatible = "marvell,armada-370-gating-clock"; | |
218 | reg = <0x18220 0x4>; | |
219 | clocks = <&coreclk 0>; | |
220 | #clock-cells = <1>; | |
5d3b8830 EG |
221 | }; |
222 | ||
467f54b2 GC |
223 | coreclk: mvebu-sar@18230 { |
224 | compatible = "marvell,armada-370-core-clock"; | |
225 | reg = <0x18230 0x08>; | |
226 | #clock-cells = <1>; | |
227 | }; | |
a09a0b7c | 228 | |
a095b1c7 JC |
229 | thermal@18300 { |
230 | compatible = "marvell,armada370-thermal"; | |
231 | reg = <0x18300 0x4 | |
232 | 0x18304 0x4>; | |
233 | status = "okay"; | |
234 | }; | |
235 | ||
e86ed56a GC |
236 | sscg@18330 { |
237 | reg = <0x18330 0x4>; | |
238 | }; | |
239 | ||
24c2573b | 240 | interrupt-controller@20a00 { |
a095b1c7 JC |
241 | reg = <0x20a00 0x1d0>, <0x21870 0x58>; |
242 | }; | |
243 | ||
244 | timer@20300 { | |
245 | compatible = "marvell,armada-370-timer"; | |
246 | clocks = <&coreclk 2>; | |
247 | }; | |
248 | ||
05afeeb9 EG |
249 | watchdog@20300 { |
250 | compatible = "marvell,armada-370-wdt"; | |
251 | clocks = <&coreclk 2>; | |
252 | }; | |
253 | ||
b6249d4b GC |
254 | cpurst@20800 { |
255 | compatible = "marvell,armada-370-cpu-reset"; | |
256 | reg = <0x20800 0x8>; | |
257 | }; | |
258 | ||
97dd823e TP |
259 | cpu-config@21000 { |
260 | compatible = "marvell,armada-370-cpu-config"; | |
261 | reg = <0x21000 0x8>; | |
262 | }; | |
263 | ||
74839835 | 264 | audio_controller: audio-controller@30000 { |
a6b33451 | 265 | #sound-dai-cells = <1>; |
74839835 TP |
266 | compatible = "marvell,armada370-audio"; |
267 | reg = <0x30000 0x4000>; | |
268 | interrupts = <93>; | |
269 | clocks = <&gateclk 0>; | |
270 | clock-names = "internal"; | |
271 | status = "disabled"; | |
272 | }; | |
273 | ||
a095b1c7 JC |
274 | usb@50000 { |
275 | clocks = <&coreclk 0>; | |
276 | }; | |
277 | ||
278 | usb@51000 { | |
467f54b2 | 279 | clocks = <&coreclk 0>; |
467f54b2 | 280 | }; |
a09a0b7c | 281 | |
467f54b2 GC |
282 | xor@60800 { |
283 | compatible = "marvell,orion-xor"; | |
284 | reg = <0x60800 0x100 | |
285 | 0x60A00 0x100>; | |
286 | status = "okay"; | |
287 | ||
288 | xor00 { | |
289 | interrupts = <51>; | |
290 | dmacap,memcpy; | |
291 | dmacap,xor; | |
292 | }; | |
293 | xor01 { | |
294 | interrupts = <52>; | |
295 | dmacap,memcpy; | |
296 | dmacap,xor; | |
297 | dmacap,memset; | |
298 | }; | |
299 | }; | |
a09a0b7c | 300 | |
467f54b2 GC |
301 | xor@60900 { |
302 | compatible = "marvell,orion-xor"; | |
303 | reg = <0x60900 0x100 | |
304 | 0x60b00 0x100>; | |
305 | status = "okay"; | |
306 | ||
307 | xor10 { | |
308 | interrupts = <94>; | |
309 | dmacap,memcpy; | |
310 | dmacap,xor; | |
311 | }; | |
312 | xor11 { | |
313 | interrupts = <95>; | |
314 | dmacap,memcpy; | |
315 | dmacap,xor; | |
316 | dmacap,memset; | |
317 | }; | |
318 | }; | |
ea3b55fe SG |
319 | |
320 | ethernet@70000 { | |
321 | compatible = "marvell,armada-370-neta"; | |
322 | }; | |
323 | ||
324 | ethernet@74000 { | |
325 | compatible = "marvell,armada-370-neta"; | |
326 | }; | |
2dbcdb11 AE |
327 | |
328 | crypto@90000 { | |
329 | compatible = "marvell,armada-370-crypto"; | |
330 | reg = <0x90000 0x10000>; | |
331 | reg-names = "regs"; | |
332 | interrupts = <48>; | |
333 | clocks = <&gateclk 23>; | |
334 | clock-names = "cesa0"; | |
335 | marvell,crypto-srams = <&crypto_sram>; | |
336 | marvell,crypto-sram-size = <0x7e0>; | |
337 | }; | |
338 | }; | |
339 | ||
340 | crypto_sram: sa-sram { | |
341 | compatible = "mmio-sram"; | |
342 | reg = <MBUS_ID(0x09, 0x01) 0 0x800>; | |
343 | reg-names = "sram"; | |
344 | clocks = <&gateclk 23>; | |
345 | #address-cells = <1>; | |
346 | #size-cells = <1>; | |
347 | ranges = <0 MBUS_ID(0x09, 0x01) 0 0x800>; | |
348 | ||
349 | /* | |
350 | * The Armada 370 has an erratum preventing the use of | |
351 | * the standard workflow for CPU idle support (relying | |
352 | * on the BootROM code to enter/exit idle state). | |
353 | * Reserve some amount of the crypto SRAM to put the | |
354 | * cpuidle workaround. | |
355 | */ | |
356 | idle-sram@0 { | |
357 | reg = <0x0 0x20>; | |
358 | }; | |
a09a0b7c | 359 | }; |
9ae6f740 TP |
360 | }; |
361 | }; | |
4904a82a AE |
362 | |
363 | &pinctrl { | |
364 | compatible = "marvell,mv88f6710-pinctrl"; | |
365 | ||
a6fa8475 AE |
366 | spi0_pins1: spi0-pins1 { |
367 | marvell,pins = "mpp33", "mpp34", | |
368 | "mpp35", "mpp36"; | |
369 | marvell,function = "spi0"; | |
370 | }; | |
371 | ||
372 | spi0_pins2: spi0_pins2 { | |
373 | marvell,pins = "mpp32", "mpp63", | |
374 | "mpp64", "mpp65"; | |
375 | marvell,function = "spi0"; | |
376 | }; | |
377 | ||
378 | spi1_pins: spi1-pins { | |
379 | marvell,pins = "mpp49", "mpp50", | |
380 | "mpp51", "mpp52"; | |
381 | marvell,function = "spi1"; | |
382 | }; | |
383 | ||
f8afeaea AE |
384 | uart0_pins: uart0-pins { |
385 | marvell,pins = "mpp0", "mpp1"; | |
386 | marvell,function = "uart0"; | |
387 | }; | |
388 | ||
389 | uart1_pins: uart1-pins { | |
390 | marvell,pins = "mpp41", "mpp42"; | |
391 | marvell,function = "uart1"; | |
392 | }; | |
393 | ||
4904a82a AE |
394 | sdio_pins1: sdio-pins1 { |
395 | marvell,pins = "mpp9", "mpp11", "mpp12", | |
396 | "mpp13", "mpp14", "mpp15"; | |
397 | marvell,function = "sd0"; | |
398 | }; | |
399 | ||
400 | sdio_pins2: sdio-pins2 { | |
401 | marvell,pins = "mpp47", "mpp48", "mpp49", | |
402 | "mpp50", "mpp51", "mpp52"; | |
403 | marvell,function = "sd0"; | |
404 | }; | |
405 | ||
406 | sdio_pins3: sdio-pins3 { | |
407 | marvell,pins = "mpp48", "mpp49", "mpp50", | |
408 | "mpp51", "mpp52", "mpp53"; | |
409 | marvell,function = "sd0"; | |
410 | }; | |
411 | ||
412 | i2c0_pins: i2c0-pins { | |
413 | marvell,pins = "mpp2", "mpp3"; | |
414 | marvell,function = "i2c0"; | |
415 | }; | |
416 | ||
417 | i2s_pins1: i2s-pins1 { | |
418 | marvell,pins = "mpp5", "mpp6", "mpp7", | |
419 | "mpp8", "mpp9", "mpp10", | |
420 | "mpp12", "mpp13"; | |
421 | marvell,function = "audio"; | |
422 | }; | |
423 | ||
424 | i2s_pins2: i2s-pins2 { | |
425 | marvell,pins = "mpp49", "mpp47", "mpp50", | |
426 | "mpp59", "mpp57", "mpp61", | |
427 | "mpp62", "mpp60", "mpp58"; | |
428 | marvell,function = "audio"; | |
429 | }; | |
430 | ||
431 | mdio_pins: mdio-pins { | |
432 | marvell,pins = "mpp17", "mpp18"; | |
433 | marvell,function = "ge"; | |
434 | }; | |
435 | ||
436 | ge0_rgmii_pins: ge0-rgmii-pins { | |
437 | marvell,pins = "mpp5", "mpp6", "mpp7", "mpp8", | |
438 | "mpp9", "mpp10", "mpp11", "mpp12", | |
439 | "mpp13", "mpp14", "mpp15", "mpp16"; | |
440 | marvell,function = "ge0"; | |
441 | }; | |
442 | ||
443 | ge1_rgmii_pins: ge1-rgmii-pins { | |
444 | marvell,pins = "mpp19", "mpp20", "mpp21", "mpp22", | |
445 | "mpp23", "mpp24", "mpp25", "mpp26", | |
446 | "mpp27", "mpp28", "mpp29", "mpp30"; | |
447 | marvell,function = "ge1"; | |
448 | }; | |
449 | }; |