projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 9ae6f740 TP |
1 | /* |
| 2 | * Device Tree Include file for Marvell Armada 370 family SoC | |
| 3 | * | |
| 4 | * Copyright (C) 2012 Marvell | |
| 5 | * | |
| 6 | * Lior Amsalem <alior@marvell.com> | |
| 7 | * Gregory CLEMENT <gregory.clement@free-electrons.com> | |
| 8 | * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> | |
| 9 | * | |
| 10 | * This file is licensed under the terms of the GNU General Public | |
| 11 | * License version 2. This program is licensed "as is" without any | |
| 12 | * warranty of any kind, whether express or implied. | |
| 13 | * | |
| 14 | * Contains definitions specific to the Armada 370 SoC that are not | |
| 15 | * common to all Armada SoCs. | |
| 16 | */ | |
| 17 | ||
| 18 | /include/ "armada-370-xp.dtsi" | |
| 19 | ||
| 20 | / { | |
| 21 | model = "Marvell Armada 370 family SoC"; | |
| 22 | compatible = "marvell,armada370", "marvell,armada-370-xp"; | |
| 2f96fbb7 GC |
23 | L2: l2-cache { |
| 24 | compatible = "marvell,aurora-outer-cache"; | |
| 25 | reg = <0xd0008000 0x1000>; | |
| 26 | cache-id-part = <0x100>; | |
| 27 | wt-override; | |
| 28 | }; | |
| 9ae6f740 | 29 | |
| 397d59f3 TP |
30 | aliases { |
| 31 | gpio0 = &gpio0; | |
| 32 | gpio1 = &gpio1; | |
| 33 | gpio2 = &gpio2; | |
| 34 | }; | |
| 35 | ||
| 9ae6f740 TP |
36 | mpic: interrupt-controller@d0020000 { |
| 37 | reg = <0xd0020a00 0x1d0>, | |
| 38 | <0xd0021870 0x58>; | |
| 39 | }; | |
| 40 | ||
| 41 | soc { | |
| 42 | system-controller@d0018200 { | |
| 43 | compatible = "marvell,armada-370-xp-system-controller"; | |
| 44 | reg = <0xd0018200 0x100>; | |
| 45 | }; | |
| d81b8baf TP |
46 | |
| 47 | pinctrl { | |
| 48 | compatible = "marvell,mv88f6710-pinctrl"; | |
| 49 | reg = <0xd0018000 0x38>; | |
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50 | |
| 51 | sdio_pins1: sdio-pins1 { | |
| 52 | marvell,pins = "mpp9", "mpp11", "mpp12", | |
| 53 | "mpp13", "mpp14", "mpp15"; | |
| 54 | marvell,function = "sd0"; | |
| 55 | }; | |
| 56 | ||
| 57 | sdio_pins2: sdio-pins2 { | |
| 58 | marvell,pins = "mpp47", "mpp48", "mpp49", | |
| 59 | "mpp50", "mpp51", "mpp52"; | |
| 60 | marvell,function = "sd0"; | |
| 61 | }; | |
| 397d59f3 TP |
62 | }; |
| 63 | ||
| 64 | gpio0: gpio@d0018100 { | |
| 65 | compatible = "marvell,orion-gpio"; | |
| 66 | reg = <0xd0018100 0x40>; | |
| 67 | ngpios = <32>; | |
| 68 | gpio-controller; | |
| 69 | #gpio-cells = <2>; | |
| 70 | interrupt-controller; | |
| 71 | #interrupts-cells = <2>; | |
| 72 | interrupts = <82>, <83>, <84>, <85>; | |
| 73 | }; | |
| 74 | ||
| 75 | gpio1: gpio@d0018140 { | |
| 76 | compatible = "marvell,orion-gpio"; | |
| 77 | reg = <0xd0018140 0x40>; | |
| 78 | ngpios = <32>; | |
| 79 | gpio-controller; | |
| 80 | #gpio-cells = <2>; | |
| 81 | interrupt-controller; | |
| 82 | #interrupts-cells = <2>; | |
| 83 | interrupts = <87>, <88>, <89>, <90>; | |
| 84 | }; | |
| 85 | ||
| 86 | gpio2: gpio@d0018180 { | |
| 87 | compatible = "marvell,orion-gpio"; | |
| 88 | reg = <0xd0018180 0x40>; | |
| 89 | ngpios = <2>; | |
| 90 | gpio-controller; | |
| 91 | #gpio-cells = <2>; | |
| 92 | interrupt-controller; | |
| 93 | #interrupts-cells = <2>; | |
| 94 | interrupts = <91>; | |
| d81b8baf | 95 | }; |
| 9d202783 GC |
96 | |
| 97 | coreclk: mvebu-sar@d0018230 { | |
| 98 | compatible = "marvell,armada-370-core-clock"; | |
| 99 | reg = <0xd0018230 0x08>; | |
| 100 | #clock-cells = <1>; | |
| 101 | }; | |
| 102 | ||
| 103 | gateclk: clock-gating-control@d0018220 { | |
| 104 | compatible = "marvell,armada-370-gating-clock"; | |
| 105 | reg = <0xd0018220 0x4>; | |
| 106 | clocks = <&coreclk 0>; | |
| 107 | #clock-cells = <1>; | |
| 108 | }; | |
| 109 | ||
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110 | xor@d0060800 { |
| 111 | compatible = "marvell,orion-xor"; | |
| 112 | reg = <0xd0060800 0x100 | |
| 113 | 0xd0060A00 0x100>; | |
| 114 | status = "okay"; | |
| 9d202783 | 115 | |
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116 | xor00 { |
| 117 | interrupts = <51>; | |
| 118 | dmacap,memcpy; | |
| 119 | dmacap,xor; | |
| 120 | }; | |
| 121 | xor01 { | |
| 122 | interrupts = <52>; | |
| 123 | dmacap,memcpy; | |
| 124 | dmacap,xor; | |
| 125 | dmacap,memset; | |
| 126 | }; | |
| 127 | }; | |
| 128 | ||
| 129 | xor@d0060900 { | |
| 130 | compatible = "marvell,orion-xor"; | |
| 131 | reg = <0xd0060900 0x100 | |
| 132 | 0xd0060b00 0x100>; | |
| 133 | status = "okay"; | |
| 134 | ||
| 135 | xor10 { | |
| 136 | interrupts = <94>; | |
| 137 | dmacap,memcpy; | |
| 138 | dmacap,xor; | |
| 139 | }; | |
| 140 | xor11 { | |
| 141 | interrupts = <95>; | |
| 142 | dmacap,memcpy; | |
| 143 | dmacap,xor; | |
| 144 | dmacap,memset; | |
| 145 | }; | |
| 146 | }; | |
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147 | |
| 148 | usb@d0050000 { | |
| 149 | clocks = <&coreclk 0>; | |
| 150 | }; | |
| 151 | ||
| 152 | usb@d0051000 { | |
| 153 | clocks = <&coreclk 0>; | |
| 154 | }; | |
| 155 | ||
| a10837ba EG |
156 | thermal@d0018300 { |
| 157 | compatible = "marvell,armada370-thermal"; | |
| 158 | reg = <0xd0018300 0x4 | |
| 159 | 0xd0018304 0x4>; | |
| 160 | status = "okay"; | |
| 161 | }; | |
| 9ae6f740 TP |
162 | }; |
| 163 | }; |