projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 9ae6f740 TP |
1 | /* |
| 2 | * Device Tree Include file for Marvell Armada 370 family SoC | |
| 3 | * | |
| 4 | * Copyright (C) 2012 Marvell | |
| 5 | * | |
| 6 | * Lior Amsalem <alior@marvell.com> | |
| 7 | * Gregory CLEMENT <gregory.clement@free-electrons.com> | |
| 8 | * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> | |
| 9 | * | |
| 10 | * This file is licensed under the terms of the GNU General Public | |
| 11 | * License version 2. This program is licensed "as is" without any | |
| 12 | * warranty of any kind, whether express or implied. | |
| 13 | * | |
| 14 | * Contains definitions specific to the Armada 370 SoC that are not | |
| 15 | * common to all Armada SoCs. | |
| 16 | */ | |
| 17 | ||
| 38149887 | 18 | #include "armada-370-xp.dtsi" |
| 74898364 | 19 | /include/ "skeleton.dtsi" |
| 9ae6f740 TP |
20 | |
| 21 | / { | |
| 22 | model = "Marvell Armada 370 family SoC"; | |
| 23 | compatible = "marvell,armada370", "marvell,armada-370-xp"; | |
| 24 | ||
| 397d59f3 TP |
25 | aliases { |
| 26 | gpio0 = &gpio0; | |
| 27 | gpio1 = &gpio1; | |
| 28 | gpio2 = &gpio2; | |
| 29 | }; | |
| 30 | ||
| 9ae6f740 | 31 | soc { |
| 5e12a613 EG |
32 | compatible = "marvell,armada370-mbus", "simple-bus"; |
| 33 | ||
| 0cd3754a EG |
34 | bootrom { |
| 35 | compatible = "marvell,bootrom"; | |
| 36 | reg = <MBUS_ID(0x01, 0xe0) 0 0x100000>; | |
| 37 | }; | |
| 38 | ||
| 14fd8ed0 EG |
39 | pcie-controller { |
| 40 | compatible = "marvell,armada-370-pcie"; | |
| 41 | status = "disabled"; | |
| 42 | device_type = "pci"; | |
| 43 | ||
| 44 | #address-cells = <3>; | |
| 45 | #size-cells = <2>; | |
| 46 | ||
| d4fa9941 | 47 | msi-parent = <&mpic>; |
| 14fd8ed0 EG |
48 | bus-range = <0x00 0xff>; |
| 49 | ||
| 50 | ranges = | |
| 51 | <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 | |
| 52 | 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 | |
| 53 | 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */ | |
| 54 | 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */ | |
| 55 | 0x82000000 0x2 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */ | |
| 56 | 0x81000000 0x2 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */>; | |
| 57 | ||
| 58 | pcie@1,0 { | |
| 59 | device_type = "pci"; | |
| 60 | assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; | |
| 61 | reg = <0x0800 0 0 0 0>; | |
| 62 | #address-cells = <3>; | |
| 63 | #size-cells = <2>; | |
| 64 | #interrupt-cells = <1>; | |
| 65 | ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 | |
| 66 | 0x81000000 0 0 0x81000000 0x1 0 1 0>; | |
| 67 | interrupt-map-mask = <0 0 0 0>; | |
| 68 | interrupt-map = <0 0 0 0 &mpic 58>; | |
| 69 | marvell,pcie-port = <0>; | |
| 70 | marvell,pcie-lane = <0>; | |
| 71 | clocks = <&gateclk 5>; | |
| 72 | status = "disabled"; | |
| 73 | }; | |
| 74 | ||
| 75 | pcie@2,0 { | |
| 76 | device_type = "pci"; | |
| 77 | assigned-addresses = <0x82002800 0 0x80000 0 0x2000>; | |
| 78 | reg = <0x1000 0 0 0 0>; | |
| 79 | #address-cells = <3>; | |
| 80 | #size-cells = <2>; | |
| 81 | #interrupt-cells = <1>; | |
| 82 | ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 | |
| 83 | 0x81000000 0 0 0x81000000 0x2 0 1 0>; | |
| 84 | interrupt-map-mask = <0 0 0 0>; | |
| 85 | interrupt-map = <0 0 0 0 &mpic 62>; | |
| 86 | marvell,pcie-port = <1>; | |
| 87 | marvell,pcie-lane = <0>; | |
| 88 | clocks = <&gateclk 9>; | |
| 89 | status = "disabled"; | |
| 90 | }; | |
| 91 | }; | |
| 92 | ||
| 467f54b2 | 93 | internal-regs { |
| 467f54b2 GC |
94 | L2: l2-cache { |
| 95 | compatible = "marvell,aurora-outer-cache"; | |
| 489e138e | 96 | reg = <0x08000 0x1000>; |
| 467f54b2 | 97 | cache-id-part = <0x100>; |
| a9ce1afb | 98 | cache-unified; |
| 467f54b2 | 99 | wt-override; |
| fa1b21d1 | 100 | }; |
| 879d68a4 | 101 | |
| a6fa8475 AE |
102 | /* |
| 103 | * Default SPI pinctrl setting, can be overwritten on | |
| 104 | * board level if a different configuration is used. | |
| 105 | */ | |
| 106 | spi0: spi@10600 { | |
| 107 | pinctrl-0 = <&spi0_pins1>; | |
| 108 | pinctrl-names = "default"; | |
| 109 | }; | |
| 110 | ||
| 111 | spi1: spi@10680 { | |
| 112 | pinctrl-0 = <&spi1_pins>; | |
| 113 | pinctrl-names = "default"; | |
| 114 | }; | |
| 115 | ||
| a095b1c7 JC |
116 | i2c0: i2c@11000 { |
| 117 | reg = <0x11000 0x20>; | |
| 118 | }; | |
| 119 | ||
| 120 | i2c1: i2c@11100 { | |
| 121 | reg = <0x11100 0x20>; | |
| 122 | }; | |
| 123 | ||
| 467f54b2 GC |
124 | gpio0: gpio@18100 { |
| 125 | compatible = "marvell,orion-gpio"; | |
| 126 | reg = <0x18100 0x40>; | |
| 127 | ngpios = <32>; | |
| 128 | gpio-controller; | |
| 129 | #gpio-cells = <2>; | |
| 130 | interrupt-controller; | |
| ca60985c | 131 | #interrupt-cells = <2>; |
| 467f54b2 | 132 | interrupts = <82>, <83>, <84>, <85>; |
| 0122eee8 | 133 | }; |
| b2bb806f | 134 | |
| 467f54b2 GC |
135 | gpio1: gpio@18140 { |
| 136 | compatible = "marvell,orion-gpio"; | |
| 137 | reg = <0x18140 0x40>; | |
| 138 | ngpios = <32>; | |
| 139 | gpio-controller; | |
| 140 | #gpio-cells = <2>; | |
| 141 | interrupt-controller; | |
| ca60985c | 142 | #interrupt-cells = <2>; |
| 467f54b2 GC |
143 | interrupts = <87>, <88>, <89>, <90>; |
| 144 | }; | |
| b2bb806f | 145 | |
| 467f54b2 GC |
146 | gpio2: gpio@18180 { |
| 147 | compatible = "marvell,orion-gpio"; | |
| 148 | reg = <0x18180 0x40>; | |
| 149 | ngpios = <2>; | |
| 150 | gpio-controller; | |
| 151 | #gpio-cells = <2>; | |
| 152 | interrupt-controller; | |
| ca60985c | 153 | #interrupt-cells = <2>; |
| 467f54b2 GC |
154 | interrupts = <91>; |
| 155 | }; | |
| a09a0b7c | 156 | |
| ab1e8537 UKK |
157 | system-controller@18200 { |
| 158 | compatible = "marvell,armada-370-xp-system-controller"; | |
| 159 | reg = <0x18200 0x100>; | |
| 160 | }; | |
| 161 | ||
| a095b1c7 JC |
162 | gateclk: clock-gating-control@18220 { |
| 163 | compatible = "marvell,armada-370-gating-clock"; | |
| 164 | reg = <0x18220 0x4>; | |
| 165 | clocks = <&coreclk 0>; | |
| 166 | #clock-cells = <1>; | |
| 5d3b8830 EG |
167 | }; |
| 168 | ||
| 467f54b2 GC |
169 | coreclk: mvebu-sar@18230 { |
| 170 | compatible = "marvell,armada-370-core-clock"; | |
| 171 | reg = <0x18230 0x08>; | |
| 172 | #clock-cells = <1>; | |
| 173 | }; | |
| a09a0b7c | 174 | |
| a095b1c7 JC |
175 | thermal@18300 { |
| 176 | compatible = "marvell,armada370-thermal"; | |
| 177 | reg = <0x18300 0x4 | |
| 178 | 0x18304 0x4>; | |
| 179 | status = "okay"; | |
| 180 | }; | |
| 181 | ||
| e86ed56a GC |
182 | sscg@18330 { |
| 183 | reg = <0x18330 0x4>; | |
| 184 | }; | |
| 185 | ||
| a095b1c7 JC |
186 | interrupt-controller@20000 { |
| 187 | reg = <0x20a00 0x1d0>, <0x21870 0x58>; | |
| 188 | }; | |
| 189 | ||
| 190 | timer@20300 { | |
| 191 | compatible = "marvell,armada-370-timer"; | |
| 192 | clocks = <&coreclk 2>; | |
| 193 | }; | |
| 194 | ||
| 05afeeb9 EG |
195 | watchdog@20300 { |
| 196 | compatible = "marvell,armada-370-wdt"; | |
| 197 | clocks = <&coreclk 2>; | |
| 198 | }; | |
| 199 | ||
| b6249d4b GC |
200 | cpurst@20800 { |
| 201 | compatible = "marvell,armada-370-cpu-reset"; | |
| 202 | reg = <0x20800 0x8>; | |
| 203 | }; | |
| 204 | ||
| 74839835 | 205 | audio_controller: audio-controller@30000 { |
| a6b33451 | 206 | #sound-dai-cells = <1>; |
| 74839835 TP |
207 | compatible = "marvell,armada370-audio"; |
| 208 | reg = <0x30000 0x4000>; | |
| 209 | interrupts = <93>; | |
| 210 | clocks = <&gateclk 0>; | |
| 211 | clock-names = "internal"; | |
| 212 | status = "disabled"; | |
| 213 | }; | |
| 214 | ||
| a095b1c7 JC |
215 | usb@50000 { |
| 216 | clocks = <&coreclk 0>; | |
| 217 | }; | |
| 218 | ||
| 219 | usb@51000 { | |
| 467f54b2 | 220 | clocks = <&coreclk 0>; |
| 467f54b2 | 221 | }; |
| a09a0b7c | 222 | |
| 467f54b2 GC |
223 | xor@60800 { |
| 224 | compatible = "marvell,orion-xor"; | |
| 225 | reg = <0x60800 0x100 | |
| 226 | 0x60A00 0x100>; | |
| 227 | status = "okay"; | |
| 228 | ||
| 229 | xor00 { | |
| 230 | interrupts = <51>; | |
| 231 | dmacap,memcpy; | |
| 232 | dmacap,xor; | |
| 233 | }; | |
| 234 | xor01 { | |
| 235 | interrupts = <52>; | |
| 236 | dmacap,memcpy; | |
| 237 | dmacap,xor; | |
| 238 | dmacap,memset; | |
| 239 | }; | |
| 240 | }; | |
| a09a0b7c | 241 | |
| 467f54b2 GC |
242 | xor@60900 { |
| 243 | compatible = "marvell,orion-xor"; | |
| 244 | reg = <0x60900 0x100 | |
| 245 | 0x60b00 0x100>; | |
| 246 | status = "okay"; | |
| 247 | ||
| 248 | xor10 { | |
| 249 | interrupts = <94>; | |
| 250 | dmacap,memcpy; | |
| 251 | dmacap,xor; | |
| 252 | }; | |
| 253 | xor11 { | |
| 254 | interrupts = <95>; | |
| 255 | dmacap,memcpy; | |
| 256 | dmacap,xor; | |
| 257 | dmacap,memset; | |
| 258 | }; | |
| 259 | }; | |
| a09a0b7c | 260 | }; |
| 9ae6f740 TP |
261 | }; |
| 262 | }; | |
| 4904a82a AE |
263 | |
| 264 | &pinctrl { | |
| 265 | compatible = "marvell,mv88f6710-pinctrl"; | |
| 266 | ||
| a6fa8475 AE |
267 | spi0_pins1: spi0-pins1 { |
| 268 | marvell,pins = "mpp33", "mpp34", | |
| 269 | "mpp35", "mpp36"; | |
| 270 | marvell,function = "spi0"; | |
| 271 | }; | |
| 272 | ||
| 273 | spi0_pins2: spi0_pins2 { | |
| 274 | marvell,pins = "mpp32", "mpp63", | |
| 275 | "mpp64", "mpp65"; | |
| 276 | marvell,function = "spi0"; | |
| 277 | }; | |
| 278 | ||
| 279 | spi1_pins: spi1-pins { | |
| 280 | marvell,pins = "mpp49", "mpp50", | |
| 281 | "mpp51", "mpp52"; | |
| 282 | marvell,function = "spi1"; | |
| 283 | }; | |
| 284 | ||
| 4904a82a AE |
285 | sdio_pins1: sdio-pins1 { |
| 286 | marvell,pins = "mpp9", "mpp11", "mpp12", | |
| 287 | "mpp13", "mpp14", "mpp15"; | |
| 288 | marvell,function = "sd0"; | |
| 289 | }; | |
| 290 | ||
| 291 | sdio_pins2: sdio-pins2 { | |
| 292 | marvell,pins = "mpp47", "mpp48", "mpp49", | |
| 293 | "mpp50", "mpp51", "mpp52"; | |
| 294 | marvell,function = "sd0"; | |
| 295 | }; | |
| 296 | ||
| 297 | sdio_pins3: sdio-pins3 { | |
| 298 | marvell,pins = "mpp48", "mpp49", "mpp50", | |
| 299 | "mpp51", "mpp52", "mpp53"; | |
| 300 | marvell,function = "sd0"; | |
| 301 | }; | |
| 302 | ||
| 303 | i2c0_pins: i2c0-pins { | |
| 304 | marvell,pins = "mpp2", "mpp3"; | |
| 305 | marvell,function = "i2c0"; | |
| 306 | }; | |
| 307 | ||
| 308 | i2s_pins1: i2s-pins1 { | |
| 309 | marvell,pins = "mpp5", "mpp6", "mpp7", | |
| 310 | "mpp8", "mpp9", "mpp10", | |
| 311 | "mpp12", "mpp13"; | |
| 312 | marvell,function = "audio"; | |
| 313 | }; | |
| 314 | ||
| 315 | i2s_pins2: i2s-pins2 { | |
| 316 | marvell,pins = "mpp49", "mpp47", "mpp50", | |
| 317 | "mpp59", "mpp57", "mpp61", | |
| 318 | "mpp62", "mpp60", "mpp58"; | |
| 319 | marvell,function = "audio"; | |
| 320 | }; | |
| 321 | ||
| 322 | mdio_pins: mdio-pins { | |
| 323 | marvell,pins = "mpp17", "mpp18"; | |
| 324 | marvell,function = "ge"; | |
| 325 | }; | |
| 326 | ||
| 327 | ge0_rgmii_pins: ge0-rgmii-pins { | |
| 328 | marvell,pins = "mpp5", "mpp6", "mpp7", "mpp8", | |
| 329 | "mpp9", "mpp10", "mpp11", "mpp12", | |
| 330 | "mpp13", "mpp14", "mpp15", "mpp16"; | |
| 331 | marvell,function = "ge0"; | |
| 332 | }; | |
| 333 | ||
| 334 | ge1_rgmii_pins: ge1-rgmii-pins { | |
| 335 | marvell,pins = "mpp19", "mpp20", "mpp21", "mpp22", | |
| 336 | "mpp23", "mpp24", "mpp25", "mpp26", | |
| 337 | "mpp27", "mpp28", "mpp29", "mpp30"; | |
| 338 | marvell,function = "ge1"; | |
| 339 | }; | |
| 340 | }; |