[deliverable/linux.git] / arch / arm / boot / dts / armada-370.dtsi

/*
 * Device Tree Include file for Marvell Armada 370 family SoC
 *
 * Copyright (C) 2012 Marvell
 *
 * Lior Amsalem <alior@marvell.com>
 * Gregory CLEMENT <gregory.clement@free-electrons.com>
 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2.  This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 *
 * Contains definitions specific to the Armada 370 SoC that are not
 * common to all Armada SoCs.
 */

#include "armada-370-xp.dtsi"
/include/ "skeleton.dtsi"

/ {
	model = "Marvell Armada 370 family SoC";
	compatible = "marvell,armada370", "marvell,armada-370-xp";

	aliases {
		gpio0 = &gpio0;
		gpio1 = &gpio1;
		gpio2 = &gpio2;
	};

	soc {
		compatible = "marvell,armada370-mbus", "simple-bus";

		bootrom {
			compatible = "marvell,bootrom";
			reg = <MBUS_ID(0x01, 0xe0) 0 0x100000>;
		};

		pcie-controller {
			compatible = "marvell,armada-370-pcie";
			status = "disabled";
			device_type = "pci";

			#address-cells = <3>;
			#size-cells = <2>;

			msi-parent = <&mpic>;
			bus-range = <0x00 0xff>;

			ranges =
			       <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
				0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000
				0x82000000 0x1 0     MBUS_ID(0x04, 0xe8) 0       1 0 /* Port 0.0 MEM */
				0x81000000 0x1 0     MBUS_ID(0x04, 0xe0) 0       1 0 /* Port 0.0 IO  */
				0x82000000 0x2 0     MBUS_ID(0x08, 0xe8) 0       1 0 /* Port 1.0 MEM */
				0x81000000 0x2 0     MBUS_ID(0x08, 0xe0) 0       1 0 /* Port 1.0 IO  */>;

			pcie@1,0 {
				device_type = "pci";
				assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
				reg = <0x0800 0 0 0 0>;
				#address-cells = <3>;
				#size-cells = <2>;
				#interrupt-cells = <1>;
                                ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
                                          0x81000000 0 0 0x81000000 0x1 0 1 0>;
				interrupt-map-mask = <0 0 0 0>;
				interrupt-map = <0 0 0 0 &mpic 58>;
				marvell,pcie-port = <0>;
				marvell,pcie-lane = <0>;
				clocks = <&gateclk 5>;
				status = "disabled";
			};

			pcie@2,0 {
				device_type = "pci";
				assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
				reg = <0x1000 0 0 0 0>;
				#address-cells = <3>;
				#size-cells = <2>;
				#interrupt-cells = <1>;
                                ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
                                          0x81000000 0 0 0x81000000 0x2 0 1 0>;
				interrupt-map-mask = <0 0 0 0>;
				interrupt-map = <0 0 0 0 &mpic 62>;
				marvell,pcie-port = <1>;
				marvell,pcie-lane = <0>;
				clocks = <&gateclk 9>;
				status = "disabled";
			};
		};

		internal-regs {
			L2: l2-cache {
				compatible = "marvell,aurora-outer-cache";
				reg = <0x08000 0x1000>;
				cache-id-part = <0x100>;
				cache-unified;
				wt-override;
			};

			i2c0: i2c@11000 {
				reg = <0x11000 0x20>;
			};

			i2c1: i2c@11100 {
				reg = <0x11100 0x20>;
			};

			pinctrl {
				compatible = "marvell,mv88f6710-pinctrl";
				reg = <0x18000 0x38>;

				sdio_pins1: sdio-pins1 {
					marvell,pins = "mpp9",  "mpp11", "mpp12",
							"mpp13", "mpp14", "mpp15";
					marvell,function = "sd0";
				};

				sdio_pins2: sdio-pins2 {
					marvell,pins = "mpp47", "mpp48", "mpp49",
							"mpp50", "mpp51", "mpp52";
					marvell,function = "sd0";
				};

				sdio_pins3: sdio-pins3 {
					marvell,pins = "mpp48", "mpp49", "mpp50",
							"mpp51", "mpp52", "mpp53";
					marvell,function = "sd0";
				};

				i2c0_pins: i2c0-pins {
					marvell,pins = "mpp2", "mpp3";
					marvell,function = "i2c0";
				};

				i2s_pins1: i2s-pins1 {
					marvell,pins = "mpp5", "mpp6", "mpp7",
						       "mpp8", "mpp9", "mpp10",
						       "mpp12", "mpp13";
					marvell,function = "audio";
				};

				i2s_pins2: i2s-pins2 {
					marvell,pins = "mpp49", "mpp47", "mpp50",
						       "mpp59", "mpp57", "mpp61",
						       "mpp62", "mpp60", "mpp58";
					marvell,function = "audio";
				};

				mdio_pins: mdio-pins {
					marvell,pins = "mpp17", "mpp18";
					marvell,function = "ge";
				};

				ge0_rgmii_pins: ge0-rgmii-pins {
					marvell,pins = "mpp5", "mpp6", "mpp7", "mpp8",
						       "mpp9", "mpp10", "mpp11", "mpp12",
						       "mpp13", "mpp14", "mpp15", "mpp16";
					marvell,function = "ge0";
				};

				ge1_rgmii_pins: ge1-rgmii-pins {
					marvell,pins = "mpp19", "mpp20", "mpp21", "mpp22",
						       "mpp23", "mpp24", "mpp25", "mpp26",
						       "mpp27", "mpp28", "mpp29", "mpp30";
					marvell,function = "ge1";
				};
			};

			gpio0: gpio@18100 {
				compatible = "marvell,orion-gpio";
				reg = <0x18100 0x40>;
				ngpios = <32>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				interrupts = <82>, <83>, <84>, <85>;
			};

			gpio1: gpio@18140 {
				compatible = "marvell,orion-gpio";
				reg = <0x18140 0x40>;
				ngpios = <32>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				interrupts = <87>, <88>, <89>, <90>;
			};

			gpio2: gpio@18180 {
				compatible = "marvell,orion-gpio";
				reg = <0x18180 0x40>;
				ngpios = <2>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				interrupts = <91>;
			};

			system-controller@18200 {
				compatible = "marvell,armada-370-xp-system-controller";
				reg = <0x18200 0x100>;
			};

			gateclk: clock-gating-control@18220 {
				compatible = "marvell,armada-370-gating-clock";
				reg = <0x18220 0x4>;
				clocks = <&coreclk 0>;
				#clock-cells = <1>;
			};

			coreclk: mvebu-sar@18230 {
				compatible = "marvell,armada-370-core-clock";
				reg = <0x18230 0x08>;
				#clock-cells = <1>;
			};

			thermal@18300 {
				compatible = "marvell,armada370-thermal";
				reg = <0x18300 0x4
					0x18304 0x4>;
				status = "okay";
			};

			sscg@18330 {
				reg = <0x18330 0x4>;
			};

			interrupt-controller@20000 {
				reg = <0x20a00 0x1d0>, <0x21870 0x58>;
			};

			timer@20300 {
				compatible = "marvell,armada-370-timer";
				clocks = <&coreclk 2>;
			};

			watchdog@20300 {
				compatible = "marvell,armada-370-wdt";
				clocks = <&coreclk 2>;
			};

			cpurst@20800 {
				compatible = "marvell,armada-370-cpu-reset";
				reg = <0x20800 0x8>;
			};

			audio_controller: audio-controller@30000 {
				#sound-dai-cells = <1>;
				compatible = "marvell,armada370-audio";
				reg = <0x30000 0x4000>;
				interrupts = <93>;
				clocks = <&gateclk 0>;
				clock-names = "internal";
				status = "disabled";
			};

			usb@50000 {
				clocks = <&coreclk 0>;
			};

			usb@51000 {
				clocks = <&coreclk 0>;
			};

			xor@60800 {
				compatible = "marvell,orion-xor";
				reg = <0x60800 0x100
				       0x60A00 0x100>;
				status = "okay";

				xor00 {
					interrupts = <51>;
					dmacap,memcpy;
					dmacap,xor;
				};
				xor01 {
					interrupts = <52>;
					dmacap,memcpy;
					dmacap,xor;
					dmacap,memset;
				};
			};

			xor@60900 {
				compatible = "marvell,orion-xor";
				reg = <0x60900 0x100
				       0x60b00 0x100>;
				status = "okay";

				xor10 {
					interrupts = <94>;
					dmacap,memcpy;
					dmacap,xor;
				};
				xor11 {
					interrupts = <95>;
					dmacap,memcpy;
					dmacap,xor;
					dmacap,memset;
				};
			};
		};
	};
};
Commit	Line	Data
9ae6f740 TP	1	/*
	2	* Device Tree Include file for Marvell Armada 370 family SoC
	3	*
	4	* Copyright (C) 2012 Marvell
	5	*
	6	* Lior Amsalem <alior@marvell.com>
	7	* Gregory CLEMENT <gregory.clement@free-electrons.com>
	8	* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
	9	*
	10	* This file is licensed under the terms of the GNU General Public
	11	* License version 2. This program is licensed "as is" without any
	12	* warranty of any kind, whether express or implied.
	13	*
	14	* Contains definitions specific to the Armada 370 SoC that are not
	15	* common to all Armada SoCs.
	16	*/
	17
38149887	18	#include "armada-370-xp.dtsi"
74898364	19	/include/ "skeleton.dtsi"
9ae6f740 TP	20
	21	/ {
	22	model = "Marvell Armada 370 family SoC";
	23	compatible = "marvell,armada370", "marvell,armada-370-xp";
	24
397d59f3 TP	25	aliases {
	26	gpio0 = &gpio0;
	27	gpio1 = &gpio1;
	28	gpio2 = &gpio2;
	29	};
	30
9ae6f740	31	soc {
5e12a613 EG	32	compatible = "marvell,armada370-mbus", "simple-bus";
5e12a613 EG	33
0cd3754a EG	34	bootrom {
	35	compatible = "marvell,bootrom";
	36	reg = <MBUS_ID(0x01, 0xe0) 0 0x100000>;
	37	};
	38
14fd8ed0 EG	39	pcie-controller {
	40	compatible = "marvell,armada-370-pcie";
	41	status = "disabled";
	42	device_type = "pci";
	43
	44	#address-cells = <3>;
	45	#size-cells = <2>;
	46
d4fa9941	47	msi-parent = <&mpic>;
14fd8ed0 EG	48	bus-range = <0x00 0xff>;
	49
	50	ranges =
	51	<0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
	52	0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000
	53	0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
	54	0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
	55	0x82000000 0x2 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
	56	0x81000000 0x2 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */>;
	57
	58	pcie@1,0 {
	59	device_type = "pci";
	60	assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
	61	reg = <0x0800 0 0 0 0>;
	62	#address-cells = <3>;
	63	#size-cells = <2>;
	64	#interrupt-cells = <1>;
	65	ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
	66	0x81000000 0 0 0x81000000 0x1 0 1 0>;
	67	interrupt-map-mask = <0 0 0 0>;
	68	interrupt-map = <0 0 0 0 &mpic 58>;
	69	marvell,pcie-port = <0>;
	70	marvell,pcie-lane = <0>;
	71	clocks = <&gateclk 5>;
	72	status = "disabled";
	73	};
	74
	75	pcie@2,0 {
	76	device_type = "pci";
	77	assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
	78	reg = <0x1000 0 0 0 0>;
	79	#address-cells = <3>;
	80	#size-cells = <2>;
	81	#interrupt-cells = <1>;
	82	ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
	83	0x81000000 0 0 0x81000000 0x2 0 1 0>;
	84	interrupt-map-mask = <0 0 0 0>;
	85	interrupt-map = <0 0 0 0 &mpic 62>;
	86	marvell,pcie-port = <1>;
	87	marvell,pcie-lane = <0>;
	88	clocks = <&gateclk 9>;
	89	status = "disabled";
	90	};
	91	};
	92
467f54b2	93	internal-regs {
467f54b2 GC	94	L2: l2-cache {
467f54b2 GC	95	compatible = "marvell,aurora-outer-cache";
489e138e	96	reg = <0x08000 0x1000>;
467f54b2	97	cache-id-part = <0x100>;
a9ce1afb	98	cache-unified;
467f54b2	99	wt-override;
fa1b21d1	100	};
879d68a4	101
a095b1c7 JC	102	i2c0: i2c@11000 {
	103	reg = <0x11000 0x20>;
	104	};
	105
	106	i2c1: i2c@11100 {
	107	reg = <0x11100 0x20>;
	108	};
	109
467f54b2 GC	110	pinctrl {
	111	compatible = "marvell,mv88f6710-pinctrl";
	112	reg = <0x18000 0x38>;
	113
	114	sdio_pins1: sdio-pins1 {
	115	marvell,pins = "mpp9", "mpp11", "mpp12",
	116	"mpp13", "mpp14", "mpp15";
	117	marvell,function = "sd0";
	118	};
	119
	120	sdio_pins2: sdio-pins2 {
	121	marvell,pins = "mpp47", "mpp48", "mpp49",
	122	"mpp50", "mpp51", "mpp52";
	123	marvell,function = "sd0";
	124	};
	125
	126	sdio_pins3: sdio-pins3 {
	127	marvell,pins = "mpp48", "mpp49", "mpp50",
	128	"mpp51", "mpp52", "mpp53";
	129	marvell,function = "sd0";
	130	};
74839835	131
8d001f0b TP	132	i2c0_pins: i2c0-pins {
	133	marvell,pins = "mpp2", "mpp3";
	134	marvell,function = "i2c0";
	135	};
	136
74839835 TP	137	i2s_pins1: i2s-pins1 {
	138	marvell,pins = "mpp5", "mpp6", "mpp7",
	139	"mpp8", "mpp9", "mpp10",
	140	"mpp12", "mpp13";
	141	marvell,function = "audio";
	142	};
	143
	144	i2s_pins2: i2s-pins2 {
	145	marvell,pins = "mpp49", "mpp47", "mpp50",
	146	"mpp59", "mpp57", "mpp61",
	147	"mpp62", "mpp60", "mpp58";
	148	marvell,function = "audio";
	149	};
a43f99d2 EG	150
	151	mdio_pins: mdio-pins {
	152	marvell,pins = "mpp17", "mpp18";
	153	marvell,function = "ge";
	154	};
	155
	156	ge0_rgmii_pins: ge0-rgmii-pins {
	157	marvell,pins = "mpp5", "mpp6", "mpp7", "mpp8",
	158	"mpp9", "mpp10", "mpp11", "mpp12",
	159	"mpp13", "mpp14", "mpp15", "mpp16";
	160	marvell,function = "ge0";
	161	};
	162
	163	ge1_rgmii_pins: ge1-rgmii-pins {
	164	marvell,pins = "mpp19", "mpp20", "mpp21", "mpp22",
	165	"mpp23", "mpp24", "mpp25", "mpp26",
	166	"mpp27", "mpp28", "mpp29", "mpp30";
	167	marvell,function = "ge1";
	168	};
0122eee8	169	};
0122eee8	170
467f54b2 GC	171	gpio0: gpio@18100 {
	172	compatible = "marvell,orion-gpio";
	173	reg = <0x18100 0x40>;
	174	ngpios = <32>;
	175	gpio-controller;
	176	#gpio-cells = <2>;
	177	interrupt-controller;
ca60985c	178	#interrupt-cells = <2>;
467f54b2	179	interrupts = <82>, <83>, <84>, <85>;
0122eee8	180	};
b2bb806f	181
467f54b2 GC	182	gpio1: gpio@18140 {
	183	compatible = "marvell,orion-gpio";
	184	reg = <0x18140 0x40>;
	185	ngpios = <32>;
	186	gpio-controller;
	187	#gpio-cells = <2>;
	188	interrupt-controller;
ca60985c	189	#interrupt-cells = <2>;
467f54b2 GC	190	interrupts = <87>, <88>, <89>, <90>;
467f54b2 GC	191	};
b2bb806f	192
467f54b2 GC	193	gpio2: gpio@18180 {
	194	compatible = "marvell,orion-gpio";
	195	reg = <0x18180 0x40>;
	196	ngpios = <2>;
	197	gpio-controller;
	198	#gpio-cells = <2>;
	199	interrupt-controller;
ca60985c	200	#interrupt-cells = <2>;
467f54b2 GC	201	interrupts = <91>;
467f54b2 GC	202	};
a09a0b7c	203
ab1e8537 UKK	204	system-controller@18200 {
	205	compatible = "marvell,armada-370-xp-system-controller";
	206	reg = <0x18200 0x100>;
	207	};
	208
a095b1c7 JC	209	gateclk: clock-gating-control@18220 {
	210	compatible = "marvell,armada-370-gating-clock";
	211	reg = <0x18220 0x4>;
	212	clocks = <&coreclk 0>;
	213	#clock-cells = <1>;
5d3b8830 EG	214	};
5d3b8830 EG	215
467f54b2 GC	216	coreclk: mvebu-sar@18230 {
	217	compatible = "marvell,armada-370-core-clock";
	218	reg = <0x18230 0x08>;
	219	#clock-cells = <1>;
	220	};
a09a0b7c	221
a095b1c7 JC	222	thermal@18300 {
	223	compatible = "marvell,armada370-thermal";
	224	reg = <0x18300 0x4
	225	0x18304 0x4>;
	226	status = "okay";
	227	};
	228
e86ed56a GC	229	sscg@18330 {
	230	reg = <0x18330 0x4>;
	231	};
	232
a095b1c7 JC	233	interrupt-controller@20000 {
	234	reg = <0x20a00 0x1d0>, <0x21870 0x58>;
	235	};
	236
	237	timer@20300 {
	238	compatible = "marvell,armada-370-timer";
	239	clocks = <&coreclk 2>;
	240	};
	241
05afeeb9 EG	242	watchdog@20300 {
	243	compatible = "marvell,armada-370-wdt";
	244	clocks = <&coreclk 2>;
	245	};
	246
b6249d4b GC	247	cpurst@20800 {
	248	compatible = "marvell,armada-370-cpu-reset";
	249	reg = <0x20800 0x8>;
	250	};
	251
74839835	252	audio_controller: audio-controller@30000 {
a6b33451	253	#sound-dai-cells = <1>;
74839835 TP	254	compatible = "marvell,armada370-audio";
	255	reg = <0x30000 0x4000>;
	256	interrupts = <93>;
	257	clocks = <&gateclk 0>;
	258	clock-names = "internal";
	259	status = "disabled";
	260	};
	261
a095b1c7 JC	262	usb@50000 {
	263	clocks = <&coreclk 0>;
	264	};
	265
	266	usb@51000 {
467f54b2	267	clocks = <&coreclk 0>;
467f54b2	268	};
a09a0b7c	269
467f54b2 GC	270	xor@60800 {
	271	compatible = "marvell,orion-xor";
	272	reg = <0x60800 0x100
	273	0x60A00 0x100>;
	274	status = "okay";
	275
	276	xor00 {
	277	interrupts = <51>;
	278	dmacap,memcpy;
	279	dmacap,xor;
	280	};
	281	xor01 {
	282	interrupts = <52>;
	283	dmacap,memcpy;
	284	dmacap,xor;
	285	dmacap,memset;
	286	};
	287	};
a09a0b7c	288
467f54b2 GC	289	xor@60900 {
	290	compatible = "marvell,orion-xor";
	291	reg = <0x60900 0x100
	292	0x60b00 0x100>;
	293	status = "okay";
	294
	295	xor10 {
	296	interrupts = <94>;
	297	dmacap,memcpy;
	298	dmacap,xor;
	299	};
	300	xor11 {
	301	interrupts = <95>;
	302	dmacap,memcpy;
	303	dmacap,xor;
	304	dmacap,memset;
	305	};
	306	};
a09a0b7c	307	};
9ae6f740 TP	308	};
9ae6f740 TP	309	};