[deliverable/linux.git] / arch / arm / boot / dts / armada-375.dtsi

/*
 * Device Tree Include file for Marvell Armada 375 family SoC
 *
 * Copyright (C) 2014 Marvell
 *
 * Gregory CLEMENT <gregory.clement@free-electrons.com>
 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2.  This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */

#include "skeleton.dtsi"
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>

#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))

/ {
	model = "Marvell Armada 375 family SoC";
	compatible = "marvell,armada375";

	aliases {
		gpio0 = &gpio0;
		gpio1 = &gpio1;
		gpio2 = &gpio2;
		ethernet0 = &eth0;
		ethernet1 = &eth1;
	};

	clocks {
		/* 2 GHz fixed main PLL */
		mainpll: mainpll {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <2000000000>;
		};
		/* 25 MHz reference crystal */
		refclk: oscillator {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <25000000>;
		};
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		enable-method = "marvell,armada-375-smp";

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <0>;
		};
		cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <1>;
		};
	};

	soc {
		compatible = "marvell,armada375-mbus", "marvell,armada370-mbus", "simple-bus";
		#address-cells = <2>;
		#size-cells = <1>;
		controller = <&mbusc>;
		interrupt-parent = <&gic>;
		pcie-mem-aperture = <0xe0000000 0x8000000>;
		pcie-io-aperture  = <0xe8000000 0x100000>;

		bootrom {
			compatible = "marvell,bootrom";
			reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
		};

		devbus-bootcs {
			compatible = "marvell,mvebu-devbus";
			reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
			ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
			#address-cells = <1>;
			#size-cells = <1>;
			clocks = <&coreclk 0>;
			status = "disabled";
		};

		devbus-cs0 {
			compatible = "marvell,mvebu-devbus";
			reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
			ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
			#address-cells = <1>;
			#size-cells = <1>;
			clocks = <&coreclk 0>;
			status = "disabled";
		};

		devbus-cs1 {
			compatible = "marvell,mvebu-devbus";
			reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
			ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>;
			#address-cells = <1>;
			#size-cells = <1>;
			clocks = <&coreclk 0>;
			status = "disabled";
		};

		devbus-cs2 {
			compatible = "marvell,mvebu-devbus";
			reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>;
			ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>;
			#address-cells = <1>;
			#size-cells = <1>;
			clocks = <&coreclk 0>;
			status = "disabled";
		};

		devbus-cs3 {
			compatible = "marvell,mvebu-devbus";
			reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>;
			ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>;
			#address-cells = <1>;
			#size-cells = <1>;
			clocks = <&coreclk 0>;
			status = "disabled";
		};

		internal-regs {
			compatible = "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;

			L2: cache-controller@8000 {
				compatible = "arm,pl310-cache";
				reg = <0x8000 0x1000>;
				cache-unified;
				cache-level = <2>;
			};

			scu@c000 {
				compatible = "arm,cortex-a9-scu";
				reg = <0xc000 0x58>;
			};

			timer@c600 {
				compatible = "arm,cortex-a9-twd-timer";
				reg = <0xc600 0x20>;
				interrupts = <GIC_PPI 13 (IRQ_TYPE_EDGE_RISING | GIC_CPU_MASK_SIMPLE(2))>;
				clocks = <&coreclk 2>;
			};

			gic: interrupt-controller@d000 {
				compatible = "arm,cortex-a9-gic";
				#interrupt-cells = <3>;
				#size-cells = <0>;
				interrupt-controller;
				reg = <0xd000 0x1000>,
				      <0xc100 0x100>;
			};

			mdio {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "marvell,orion-mdio";
				reg = <0xc0054 0x4>;
				clocks = <&gateclk 19>;
			};

			/* Network controller */
			ethernet@f0000 {
				compatible = "marvell,armada-375-pp2";
				reg = <0xf0000 0xa000>, /* Packet Processor regs */
				      <0xc0000 0x3060>, /* LMS regs */
				      <0xc4000 0x100>,  /* eth0 regs */
				      <0xc5000 0x100>;  /* eth1 regs */
				clocks = <&gateclk 3>, <&gateclk 19>;
				clock-names = "pp_clk", "gop_clk";
				status = "disabled";

				eth0: eth0@c4000 {
					interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
					port-id = <0>;
					status = "disabled";
				};

				eth1: eth1@c5000 {
					interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
					port-id = <1>;
					status = "disabled";
				};
			};

			rtc@10300 {
				compatible = "marvell,orion-rtc";
				reg = <0x10300 0x20>;
				interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
			};

			spi0: spi@10600 {
				compatible = "marvell,orion-spi";
				reg = <0x10600 0x50>;
				#address-cells = <1>;
				#size-cells = <0>;
				cell-index = <0>;
				interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&coreclk 0>;
				status = "disabled";
			};

			spi1: spi@10680 {
				compatible = "marvell,orion-spi";
				reg = <0x10680 0x50>;
				#address-cells = <1>;
				#size-cells = <0>;
				cell-index = <1>;
				interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&coreclk 0>;
				status = "disabled";
			};

			i2c0: i2c@11000 {
				compatible = "marvell,mv64xxx-i2c";
				reg = <0x11000 0x20>;
				#address-cells = <1>;
				#size-cells = <0>;
				interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
				timeout-ms = <1000>;
				clocks = <&coreclk 0>;
				status = "disabled";
			};

			i2c1: i2c@11100 {
				compatible = "marvell,mv64xxx-i2c";
				reg = <0x11100 0x20>;
				#address-cells = <1>;
				#size-cells = <0>;
				interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
				timeout-ms = <1000>;
				clocks = <&coreclk 0>;
				status = "disabled";
			};

			serial@12000 {
				compatible = "snps,dw-apb-uart";
				reg = <0x12000 0x100>;
				reg-shift = <2>;
				interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
				reg-io-width = <1>;
				clocks = <&coreclk 0>;
				status = "disabled";
			};

			serial@12100 {
				compatible = "snps,dw-apb-uart";
				reg = <0x12100 0x100>;
				reg-shift = <2>;
				interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
				reg-io-width = <1>;
				clocks = <&coreclk 0>;
				status = "disabled";
			};

			pinctrl {
				compatible = "marvell,mv88f6720-pinctrl";
				reg = <0x18000 0x24>;

				i2c0_pins: i2c0-pins {
					marvell,pins = "mpp14",  "mpp15";
					marvell,function = "i2c0";
				};

				i2c1_pins: i2c1-pins {
					marvell,pins = "mpp61",  "mpp62";
					marvell,function = "i2c1";
				};

				nand_pins: nand-pins {
					marvell,pins = "mpp0", "mpp1", "mpp2",
						"mpp3", "mpp4", "mpp5",
						"mpp6", "mpp7", "mpp8",
						"mpp9", "mpp10", "mpp11",
						"mpp12", "mpp13";
					marvell,function = "nand";
				};

				sdio_pins: sdio-pins {
					marvell,pins = "mpp24",  "mpp25", "mpp26",
						     "mpp27", "mpp28", "mpp29";
					marvell,function = "sd";
				};

				spi0_pins: spi0-pins {
					marvell,pins = "mpp0",  "mpp1", "mpp4",
						     "mpp5", "mpp8", "mpp9";
					marvell,function = "spi0";
				};
			};

			gpio0: gpio@18100 {
				compatible = "marvell,orion-gpio";
				reg = <0x18100 0x40>;
				ngpios = <32>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
			};

			gpio1: gpio@18140 {
				compatible = "marvell,orion-gpio";
				reg = <0x18140 0x40>;
				ngpios = <32>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
			};

			gpio2: gpio@18180 {
				compatible = "marvell,orion-gpio";
				reg = <0x18180 0x40>;
				ngpios = <3>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
			};

			system-controller@18200 {
				compatible = "marvell,armada-375-system-controller";
				reg = <0x18200 0x100>;
			};

			gateclk: clock-gating-control@18220 {
				compatible = "marvell,armada-375-gating-clock";
				reg = <0x18220 0x4>;
				clocks = <&coreclk 0>;
				#clock-cells = <1>;
			};

			mbusc: mbus-controller@20000 {
				compatible = "marvell,mbus-controller";
				reg = <0x20000 0x100>, <0x20180 0x20>;
			};

			mpic: interrupt-controller@20000 {
				compatible = "marvell,mpic";
				reg = <0x20a00 0x2d0>, <0x21070 0x58>;
				#interrupt-cells = <1>;
				#size-cells = <1>;
				interrupt-controller;
				msi-controller;
				interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
			};

			timer@20300 {
				compatible = "marvell,armada-375-timer", "marvell,armada-370-timer";
				reg = <0x20300 0x30>, <0x21040 0x30>;
				interrupts-extended = <&gic  GIC_SPI  8 IRQ_TYPE_LEVEL_HIGH>,
						      <&gic  GIC_SPI  9 IRQ_TYPE_LEVEL_HIGH>,
						      <&gic  GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
						      <&gic  GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
						      <&mpic 5>,
						      <&mpic 6>;
				clocks = <&coreclk 0>, <&refclk>;
				clock-names = "nbclk", "fixed";
			};

			watchdog@20300 {
				compatible = "marvell,armada-375-wdt";
				reg = <0x20300 0x34>, <0x20704 0x4>, <0x18254 0x4>;
				clocks = <&coreclk 0>, <&refclk>;
				clock-names = "nbclk", "fixed";
			};

			cpurst@20800 {
				compatible = "marvell,armada-370-cpu-reset";
				reg = <0x20800 0x10>;
			};

			coherency-fabric@21010 {
				compatible = "marvell,armada-375-coherency-fabric";
				reg = <0x21010 0x1c>;
			};

			usb@50000 {
				compatible = "marvell,orion-ehci";
				reg = <0x50000 0x500>;
				interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&gateclk 18>;
				status = "disabled";
			};

			usb@54000 {
				compatible = "marvell,orion-ehci";
				reg = <0x54000 0x500>;
				interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&gateclk 26>;
				status = "disabled";
			};

			usb3@58000 {
				compatible = "marvell,armada-375-xhci";
				reg = <0x58000 0x20000>,<0x5b880 0x80>;
				interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&gateclk 16>;
				status = "disabled";
			};

			xor@60800 {
				compatible = "marvell,orion-xor";
				reg = <0x60800 0x100
				       0x60A00 0x100>;
				clocks = <&gateclk 22>;
				status = "okay";

				xor00 {
					interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
					dmacap,memcpy;
					dmacap,xor;
				};
				xor01 {
					interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
					dmacap,memcpy;
					dmacap,xor;
					dmacap,memset;
				};
			};

			xor@60900 {
				compatible = "marvell,orion-xor";
				reg = <0x60900 0x100
				       0x60b00 0x100>;
				clocks = <&gateclk 23>;
				status = "okay";

				xor10 {
					interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
					dmacap,memcpy;
					dmacap,xor;
				};
				xor11 {
					interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
					dmacap,memcpy;
					dmacap,xor;
					dmacap,memset;
				};
			};

			sata@a0000 {
				compatible = "marvell,orion-sata";
				reg = <0xa0000 0x5000>;
				interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&gateclk 14>, <&gateclk 20>;
				clock-names = "0", "1";
				status = "disabled";
			};

			nand@d0000 {
				compatible = "marvell,armada370-nand";
				reg = <0xd0000 0x54>;
				#address-cells = <1>;
				#size-cells = <1>;
				interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&gateclk 11>;
				status = "disabled";
			};

			mvsdio@d4000 {
				compatible = "marvell,orion-sdio";
				reg = <0xd4000 0x200>;
				interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&gateclk 17>;
				bus-width = <4>;
				cap-sdio-irq;
				cap-sd-highspeed;
				cap-mmc-highspeed;
				status = "disabled";
			};

			thermal@e8078 {
				compatible = "marvell,armada375-thermal";
				reg = <0xe8078 0x4>, <0xe807c 0x8>;
				status = "okay";
			};

			coreclk: mvebu-sar@e8204 {
				compatible = "marvell,armada-375-core-clock";
				reg = <0xe8204 0x04>;
				#clock-cells = <1>;
			};

			coredivclk: corediv-clock@e8250 {
				compatible = "marvell,armada-375-corediv-clock";
				reg = <0xe8250 0xc>;
				#clock-cells = <1>;
				clocks = <&mainpll>;
				clock-output-names = "nand";
			};
		};

		pcie-controller {
			compatible = "marvell,armada-370-pcie";
			status = "disabled";
			device_type = "pci";

			#address-cells = <3>;
			#size-cells = <2>;

			msi-parent = <&mpic>;
			bus-range = <0x00 0xff>;

			ranges =
			       <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
				0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000
				0x82000000 0x1 0       MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0 MEM */
				0x81000000 0x1 0       MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0 IO  */
				0x82000000 0x2 0       MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 1 MEM */
				0x81000000 0x2 0       MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 1 IO  */>;

			pcie@1,0 {
				device_type = "pci";
				assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
				reg = <0x0800 0 0 0 0>;
				#address-cells = <3>;
				#size-cells = <2>;
				#interrupt-cells = <1>;
				ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
					  0x81000000 0 0 0x81000000 0x1 0 1 0>;
				interrupt-map-mask = <0 0 0 0>;
				interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
				marvell,pcie-port = <0>;
				marvell,pcie-lane = <0>;
				clocks = <&gateclk 5>;
				status = "disabled";
			};

			pcie@2,0 {
				device_type = "pci";
				assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
				reg = <0x1000 0 0 0 0>;
				#address-cells = <3>;
				#size-cells = <2>;
				#interrupt-cells = <1>;
				ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
					  0x81000000 0 0 0x81000000 0x2 0 1 0>;
				interrupt-map-mask = <0 0 0 0>;
				interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
				marvell,pcie-port = <0>;
				marvell,pcie-lane = <1>;
				clocks = <&gateclk 6>;
				status = "disabled";
			};

		};
	};
};
Commit	Line	Data
4de59085 GC	1	/*
	2	* Device Tree Include file for Marvell Armada 375 family SoC
	3	*
	4	* Copyright (C) 2014 Marvell
	5	*
	6	* Gregory CLEMENT <gregory.clement@free-electrons.com>
	7	* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
	8	*
	9	* This file is licensed under the terms of the GNU General Public
	10	* License version 2. This program is licensed "as is" without any
	11	* warranty of any kind, whether express or implied.
	12	*/
	13
a2be1561	14	#include "skeleton.dtsi"
f327d43d	15	#include <dt-bindings/interrupt-controller/arm-gic.h>
d11548e3	16	#include <dt-bindings/interrupt-controller/irq.h>
4de59085 GC	17
	18	#define MBUS_ID(target,attributes) (((target) << 24) \| ((attributes) << 16))
	19
	20	/ {
	21	model = "Marvell Armada 375 family SoC";
	22	compatible = "marvell,armada375";
	23
	24	aliases {
	25	gpio0 = &gpio0;
	26	gpio1 = &gpio1;
	27	gpio2 = &gpio2;
6c1062ba MW	28	ethernet0 = &eth0;
6c1062ba MW	29	ethernet1 = &eth1;
4de59085 GC	30	};
	31
	32	clocks {
	33	/* 2 GHz fixed main PLL */
	34	mainpll: mainpll {
	35	compatible = "fixed-clock";
	36	#clock-cells = <0>;
	37	clock-frequency = <2000000000>;
	38	};
9a27b449 EG	39	/* 25 MHz reference crystal */
	40	refclk: oscillator {
	41	compatible = "fixed-clock";
	42	#clock-cells = <0>;
	43	clock-frequency = <25000000>;
	44	};
4de59085 GC	45	};
	46
	47	cpus {
	48	#address-cells = <1>;
	49	#size-cells = <0>;
42eae5a4 GC	50	enable-method = "marvell,armada-375-smp";
42eae5a4 GC	51
4de59085 GC	52	cpu@0 {
	53	device_type = "cpu";
	54	compatible = "arm,cortex-a9";
	55	reg = <0>;
	56	};
	57	cpu@1 {
	58	device_type = "cpu";
	59	compatible = "arm,cortex-a9";
	60	reg = <1>;
	61	};
	62	};
	63
	64	soc {
	65	compatible = "marvell,armada375-mbus", "marvell,armada370-mbus", "simple-bus";
	66	#address-cells = <2>;
	67	#size-cells = <1>;
	68	controller = <&mbusc>;
	69	interrupt-parent = <&gic>;
	70	pcie-mem-aperture = <0xe0000000 0x8000000>;
	71	pcie-io-aperture = <0xe8000000 0x100000>;
	72
	73	bootrom {
	74	compatible = "marvell,bootrom";
	75	reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
	76	};
	77
	78	devbus-bootcs {
	79	compatible = "marvell,mvebu-devbus";
	80	reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
	81	ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
	82	#address-cells = <1>;
	83	#size-cells = <1>;
	84	clocks = <&coreclk 0>;
	85	status = "disabled";
	86	};
	87
	88	devbus-cs0 {
	89	compatible = "marvell,mvebu-devbus";
	90	reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
	91	ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
	92	#address-cells = <1>;
	93	#size-cells = <1>;
	94	clocks = <&coreclk 0>;
	95	status = "disabled";
	96	};
	97
	98	devbus-cs1 {
	99	compatible = "marvell,mvebu-devbus";
	100	reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
	101	ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>;
	102	#address-cells = <1>;
	103	#size-cells = <1>;
	104	clocks = <&coreclk 0>;
	105	status = "disabled";
	106	};
	107
	108	devbus-cs2 {
	109	compatible = "marvell,mvebu-devbus";
	110	reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>;
	111	ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>;
	112	#address-cells = <1>;
	113	#size-cells = <1>;
	114	clocks = <&coreclk 0>;
	115	status = "disabled";
116	};
117
118	devbus-cs3 {
119	compatible = "marvell,mvebu-devbus";
120	reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>;
121	ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>;
122	#address-cells = <1>;
123	#size-cells = <1>;
124	clocks = <&coreclk 0>;
125	status = "disabled";
126	};
127
128	internal-regs {
129	compatible = "simple-bus";
130	#address-cells = <1>;
131	#size-cells = <1>;
132	ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
133
134	L2: cache-controller@8000 {
135	compatible = "arm,pl310-cache";
136	reg = <0x8000 0x1000>;
137	cache-unified;
138	cache-level = <2>;
139	};
140
6a8a57f2 TP	141	scu@c000 {
	142	compatible = "arm,cortex-a9-scu";
	143	reg = <0xc000 0x58>;
	144	};
	145
4de59085 GC	146	timer@c600 {
	147	compatible = "arm,cortex-a9-twd-timer";
	148	reg = <0xc600 0x20>;
d11548e3	149	interrupts = <GIC_PPI 13 (IRQ_TYPE_EDGE_RISING \| GIC_CPU_MASK_SIMPLE(2))>;
4de59085 GC	150	clocks = <&coreclk 2>;
	151	};
	152
	153	gic: interrupt-controller@d000 {
	154	compatible = "arm,cortex-a9-gic";
	155	#interrupt-cells = <3>;
	156	#size-cells = <0>;
	157	interrupt-controller;
	158	reg = <0xd000 0x1000>,
	159	<0xc100 0x100>;
	160	};
	161
ff10e2cd EG	162	mdio {
	163	#address-cells = <1>;
	164	#size-cells = <0>;
	165	compatible = "marvell,orion-mdio";
	166	reg = <0xc0054 0x4>;
112dc53d	167	clocks = <&gateclk 19>;
ff10e2cd EG	168	};
	169
	170	/* Network controller */
	171	ethernet@f0000 {
	172	compatible = "marvell,armada-375-pp2";
	173	reg = <0xf0000 0xa000>, /* Packet Processor regs */
	174	<0xc0000 0x3060>, /* LMS regs */
	175	<0xc4000 0x100>, /* eth0 regs */
	176	<0xc5000 0x100>; /* eth1 regs */
	177	clocks = <&gateclk 3>, <&gateclk 19>;
	178	clock-names = "pp_clk", "gop_clk";
	179	status = "disabled";
	180
	181	eth0: eth0@c4000 {
	182	interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
	183	port-id = <0>;
	184	status = "disabled";
	185	};
	186
	187	eth1: eth1@c5000 {
	188	interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
	189	port-id = <1>;
	190	status = "disabled";
	191	};
	192	};
	193
dd2d62df GC	194	rtc@10300 {
	195	compatible = "marvell,orion-rtc";
	196	reg = <0x10300 0x20>;
	197	interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
	198	};
	199
4de59085 GC	200	spi0: spi@10600 {
	201	compatible = "marvell,orion-spi";
	202	reg = <0x10600 0x50>;
	203	#address-cells = <1>;
	204	#size-cells = <0>;
	205	cell-index = <0>;
d11548e3	206	interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
4de59085 GC	207	clocks = <&coreclk 0>;
	208	status = "disabled";
	209	};
	210
	211	spi1: spi@10680 {
	212	compatible = "marvell,orion-spi";
	213	reg = <0x10680 0x50>;
	214	#address-cells = <1>;
	215	#size-cells = <0>;
	216	cell-index = <1>;
d11548e3	217	interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
4de59085 GC	218	clocks = <&coreclk 0>;
	219	status = "disabled";
	220	};
	221
	222	i2c0: i2c@11000 {
	223	compatible = "marvell,mv64xxx-i2c";
	224	reg = <0x11000 0x20>;
	225	#address-cells = <1>;
	226	#size-cells = <0>;
d11548e3	227	interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
4de59085 GC	228	timeout-ms = <1000>;
	229	clocks = <&coreclk 0>;
	230	status = "disabled";
	231	};
	232
	233	i2c1: i2c@11100 {
	234	compatible = "marvell,mv64xxx-i2c";
	235	reg = <0x11100 0x20>;
	236	#address-cells = <1>;
	237	#size-cells = <0>;
d11548e3	238	interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
4de59085 GC	239	timeout-ms = <1000>;
	240	clocks = <&coreclk 0>;
	241	status = "disabled";
	242	};
	243
	244	serial@12000 {
	245	compatible = "snps,dw-apb-uart";
	246	reg = <0x12000 0x100>;
	247	reg-shift = <2>;
d11548e3	248	interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
4de59085	249	reg-io-width = <1>;
64939dc5	250	clocks = <&coreclk 0>;
4de59085 GC	251	status = "disabled";
	252	};
	253
	254	serial@12100 {
	255	compatible = "snps,dw-apb-uart";
	256	reg = <0x12100 0x100>;
	257	reg-shift = <2>;
d11548e3	258	interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
4de59085	259	reg-io-width = <1>;
64939dc5	260	clocks = <&coreclk 0>;
4de59085 GC	261	status = "disabled";
	262	};
	263
	264	pinctrl {
	265	compatible = "marvell,mv88f6720-pinctrl";
	266	reg = <0x18000 0x24>;
	267
	268	i2c0_pins: i2c0-pins {
	269	marvell,pins = "mpp14", "mpp15";
	270	marvell,function = "i2c0";
	271	};
	272
	273	i2c1_pins: i2c1-pins {
	274	marvell,pins = "mpp61", "mpp62";
	275	marvell,function = "i2c1";
	276	};
	277
	278	nand_pins: nand-pins {
	279	marvell,pins = "mpp0", "mpp1", "mpp2",
	280	"mpp3", "mpp4", "mpp5",
	281	"mpp6", "mpp7", "mpp8",
	282	"mpp9", "mpp10", "mpp11",
	283	"mpp12", "mpp13";
	284	marvell,function = "nand";
	285	};
	286
	287	sdio_pins: sdio-pins {
	288	marvell,pins = "mpp24", "mpp25", "mpp26",
	289	"mpp27", "mpp28", "mpp29";
	290	marvell,function = "sd";
	291	};
	292
	293	spi0_pins: spi0-pins {
	294	marvell,pins = "mpp0", "mpp1", "mpp4",
	295	"mpp5", "mpp8", "mpp9";
	296	marvell,function = "spi0";
	297	};
	298	};
	299
	300	gpio0: gpio@18100 {
	301	compatible = "marvell,orion-gpio";
	302	reg = <0x18100 0x40>;
	303	ngpios = <32>;
	304	gpio-controller;
	305	#gpio-cells = <2>;
	306	interrupt-controller;
	307	#interrupt-cells = <2>;
d11548e3 TP	308	interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
	309	<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
	310	<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
	311	<GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
4de59085 GC	312	};
	313
	314	gpio1: gpio@18140 {
	315	compatible = "marvell,orion-gpio";
	316	reg = <0x18140 0x40>;
	317	ngpios = <32>;
	318	gpio-controller;
	319	#gpio-cells = <2>;
	320	interrupt-controller;
	321	#interrupt-cells = <2>;
d11548e3 TP	322	interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
	323	<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
	324	<GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
	325	<GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
4de59085 GC	326	};
	327
	328	gpio2: gpio@18180 {
	329	compatible = "marvell,orion-gpio";
	330	reg = <0x18180 0x40>;
	331	ngpios = <3>;
	332	gpio-controller;
	333	#gpio-cells = <2>;
	334	interrupt-controller;
	335	#interrupt-cells = <2>;
d11548e3	336	interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
4de59085 GC	337	};
	338
	339	system-controller@18200 {
	340	compatible = "marvell,armada-375-system-controller";
	341	reg = <0x18200 0x100>;
	342	};
	343
	344	gateclk: clock-gating-control@18220 {
	345	compatible = "marvell,armada-375-gating-clock";
	346	reg = <0x18220 0x4>;
	347	clocks = <&coreclk 0>;
	348	#clock-cells = <1>;
	349	};
	350
	351	mbusc: mbus-controller@20000 {
	352	compatible = "marvell,mbus-controller";
	353	reg = <0x20000 0x100>, <0x20180 0x20>;
	354	};
	355
	356	mpic: interrupt-controller@20000 {
	357	compatible = "marvell,mpic";
	358	reg = <0x20a00 0x2d0>, <0x21070 0x58>;
	359	#interrupt-cells = <1>;
	360	#size-cells = <1>;
	361	interrupt-controller;
	362	msi-controller;
d11548e3	363	interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
4de59085 GC	364	};
	365
	366	timer@20300 {
	367	compatible = "marvell,armada-375-timer", "marvell,armada-370-timer";
	368	reg = <0x20300 0x30>, <0x21040 0x30>;
d11548e3 TP	369	interrupts-extended = <&gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
	370	<&gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
	371	<&gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
	372	<&gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
4de59085 GC	373	<&mpic 5>,
4de59085 GC	374	<&mpic 6>;
9a27b449 EG	375	clocks = <&coreclk 0>, <&refclk>;
9a27b449 EG	376	clock-names = "nbclk", "fixed";
4de59085 GC	377	};
4de59085 GC	378
13dacc56 EG	379	watchdog@20300 {
	380	compatible = "marvell,armada-375-wdt";
	381	reg = <0x20300 0x34>, <0x20704 0x4>, <0x18254 0x4>;
9a27b449 EG	382	clocks = <&coreclk 0>, <&refclk>;
9a27b449 EG	383	clock-names = "nbclk", "fixed";
13dacc56 EG	384	};
13dacc56 EG	385
42eae5a4 GC	386	cpurst@20800 {
	387	compatible = "marvell,armada-370-cpu-reset";
	388	reg = <0x20800 0x10>;
	389	};
	390
6a8a57f2 TP	391	coherency-fabric@21010 {
	392	compatible = "marvell,armada-375-coherency-fabric";
	393	reg = <0x21010 0x1c>;
	394	};
	395
57dc7971 GC	396	usb@50000 {
	397	compatible = "marvell,orion-ehci";
	398	reg = <0x50000 0x500>;
	399	interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
	400	clocks = <&gateclk 18>;
	401	status = "disabled";
	402	};
	403
	404	usb@54000 {
	405	compatible = "marvell,orion-ehci";
	406	reg = <0x54000 0x500>;
	407	interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
	408	clocks = <&gateclk 26>;
	409	status = "disabled";
	410	};
	411
e8f99c5b GC	412	usb3@58000 {
	413	compatible = "marvell,armada-375-xhci";
	414	reg = <0x58000 0x20000>,<0x5b880 0x80>;
	415	interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
	416	clocks = <&gateclk 16>;
	417	status = "disabled";
	418	};
	419
4de59085 GC	420	xor@60800 {
	421	compatible = "marvell,orion-xor";
	422	reg = <0x60800 0x100
	423	0x60A00 0x100>;
	424	clocks = <&gateclk 22>;
	425	status = "okay";
	426
	427	xor00 {
d11548e3	428	interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
4de59085 GC	429	dmacap,memcpy;
	430	dmacap,xor;
	431	};
	432	xor01 {
d11548e3	433	interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
4de59085 GC	434	dmacap,memcpy;
	435	dmacap,xor;
	436	dmacap,memset;
	437	};
	438	};
	439
	440	xor@60900 {
	441	compatible = "marvell,orion-xor";
	442	reg = <0x60900 0x100
	443	0x60b00 0x100>;
	444	clocks = <&gateclk 23>;
	445	status = "okay";
	446
	447	xor10 {
d11548e3	448	interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
4de59085 GC	449	dmacap,memcpy;
	450	dmacap,xor;
	451	};
	452	xor11 {
d11548e3	453	interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
4de59085 GC	454	dmacap,memcpy;
	455	dmacap,xor;
	456	dmacap,memset;
	457	};
	458	};
	459
	460	sata@a0000 {
	461	compatible = "marvell,orion-sata";
	462	reg = <0xa0000 0x5000>;
d11548e3	463	interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
4de59085 GC	464	clocks = <&gateclk 14>, <&gateclk 20>;
	465	clock-names = "0", "1";
	466	status = "disabled";
	467	};
	468
	469	nand@d0000 {
	470	compatible = "marvell,armada370-nand";
	471	reg = <0xd0000 0x54>;
	472	#address-cells = <1>;
	473	#size-cells = <1>;
d11548e3	474	interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
4de59085 GC	475	clocks = <&gateclk 11>;
	476	status = "disabled";
	477	};
	478
	479	mvsdio@d4000 {
	480	compatible = "marvell,orion-sdio";
	481	reg = <0xd4000 0x200>;
d11548e3	482	interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
4de59085 GC	483	clocks = <&gateclk 17>;
	484	bus-width = <4>;
	485	cap-sdio-irq;
	486	cap-sd-highspeed;
	487	cap-mmc-highspeed;
	488	status = "disabled";
f672e481 EG	489	};
	490
	491	thermal@e8078 {
	492	compatible = "marvell,armada375-thermal";
	493	reg = <0xe8078 0x4>, <0xe807c 0x8>;
	494	status = "okay";
4de59085 GC	495	};
	496
	497	coreclk: mvebu-sar@e8204 {
	498	compatible = "marvell,armada-375-core-clock";
	499	reg = <0xe8204 0x04>;
	500	#clock-cells = <1>;
	501	};
	502
	503	coredivclk: corediv-clock@e8250 {
	504	compatible = "marvell,armada-375-corediv-clock";
	505	reg = <0xe8250 0xc>;
	506	#clock-cells = <1>;
	507	clocks = <&mainpll>;
	508	clock-output-names = "nand";
	509	};
	510	};
	511
	512	pcie-controller {
	513	compatible = "marvell,armada-370-pcie";
	514	status = "disabled";
	515	device_type = "pci";
	516
	517	#address-cells = <3>;
	518	#size-cells = <2>;
	519
	520	msi-parent = <&mpic>;
	521	bus-range = <0x00 0xff>;
	522
	523	ranges =
	524	<0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
	525	0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000
	526	0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0 MEM */
	527	0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0 IO */
	528	0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 1 MEM */
	529	0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 1 IO */>;
	530
	531	pcie@1,0 {
	532	device_type = "pci";
	533	assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
	534	reg = <0x0800 0 0 0 0>;
	535	#address-cells = <3>;
	536	#size-cells = <2>;
	537	#interrupt-cells = <1>;
	538	ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
	539	0x81000000 0 0 0x81000000 0x1 0 1 0>;
	540	interrupt-map-mask = <0 0 0 0>;
d11548e3	541	interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
4de59085 GC	542	marvell,pcie-port = <0>;
	543	marvell,pcie-lane = <0>;
	544	clocks = <&gateclk 5>;
	545	status = "disabled";
	546	};
	547
	548	pcie@2,0 {
	549	device_type = "pci";
	550	assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
	551	reg = <0x1000 0 0 0 0>;
	552	#address-cells = <3>;
	553	#size-cells = <2>;
	554	#interrupt-cells = <1>;
	555	ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
	556	0x81000000 0 0 0x81000000 0x2 0 1 0>;
	557	interrupt-map-mask = <0 0 0 0>;
d11548e3	558	interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
4de59085 GC	559	marvell,pcie-port = <0>;
	560	marvell,pcie-lane = <1>;
	561	clocks = <&gateclk 6>;
	562	status = "disabled";
	563	};
	564
	565	};
	566	};
	567	};