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a47172ea | 1 | /* |
881a50e4 | 2 | * Device Tree file for Marvell Armada 388 evaluation board |
a47172ea TP |
3 | * (DB-88F6820) |
4 | * | |
5 | * Copyright (C) 2014 Marvell | |
6 | * | |
7 | * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> | |
8 | * | |
626a1020 GC |
9 | * This file is dual-licensed: you can use it either under the terms |
10 | * of the GPL or the X11 license, at your option. Note that this dual | |
11 | * licensing only applies to this file, and not this project as a | |
12 | * whole. | |
13 | * | |
14 | * a) This file is free software; you can redistribute it and/or | |
15 | * modify it under the terms of the GNU General Public License as | |
16 | * published by the Free Software Foundation; either version 2 of the | |
17 | * License, or (at your option) any later version. | |
18 | * | |
19 | * This file is distributed in the hope that it will be useful | |
20 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
21 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
22 | * GNU General Public License for more details. | |
23 | * | |
24 | * Or, alternatively | |
25 | * | |
26 | * b) Permission is hereby granted, free of charge, to any person | |
27 | * obtaining a copy of this software and associated documentation | |
28 | * files (the "Software"), to deal in the Software without | |
29 | * restriction, including without limitation the rights to use | |
30 | * copy, modify, merge, publish, distribute, sublicense, and/or | |
31 | * sell copies of the Software, and to permit persons to whom the | |
32 | * Software is furnished to do so, subject to the following | |
33 | * conditions: | |
34 | * | |
35 | * The above copyright notice and this permission notice shall be | |
36 | * included in all copies or substantial portions of the Software. | |
37 | * | |
38 | * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND | |
39 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES | |
40 | * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
41 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT | |
42 | * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY | |
43 | * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
44 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
45 | * OTHER DEALINGS IN THE SOFTWARE. | |
a47172ea TP |
46 | */ |
47 | ||
48 | /dts-v1/; | |
881a50e4 | 49 | #include "armada-388.dtsi" |
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50 | |
51 | / { | |
52 | model = "Marvell Armada 385 Development Board"; | |
881a50e4 GC |
53 | compatible = "marvell,a385-db", "marvell,armada388", |
54 | "marvell,armada385", "marvell,armada380"; | |
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55 | |
56 | chosen { | |
9552203c | 57 | stdout-path = "serial0:115200n8"; |
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58 | }; |
59 | ||
60 | memory { | |
61 | device_type = "memory"; | |
62 | reg = <0x00000000 0x10000000>; /* 256 MB */ | |
63 | }; | |
64 | ||
65 | soc { | |
66 | ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000 | |
d716f2e8 BB |
67 | MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000 |
68 | MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000 | |
c49e99c2 MW |
69 | MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000 |
70 | MBUS_ID(0x0c, 0x04) 0 0xf1200000 0x100000>; | |
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71 | |
72 | internal-regs { | |
73 | spi@10600 { | |
74 | status = "okay"; | |
75 | ||
76 | spi-flash@0 { | |
77 | #address-cells = <1>; | |
78 | #size-cells = <1>; | |
e9f3ed4a | 79 | compatible = "w25q32", "jedec,spi-nor"; |
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80 | reg = <0>; /* Chip select 0 */ |
81 | spi-max-frequency = <108000000>; | |
82 | }; | |
83 | }; | |
84 | ||
85 | i2c@11000 { | |
86 | status = "okay"; | |
87 | clock-frequency = <100000>; | |
88 | }; | |
89 | ||
90 | i2c@11100 { | |
91 | status = "okay"; | |
92 | clock-frequency = <100000>; | |
93 | }; | |
94 | ||
95 | serial@12000 { | |
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96 | status = "okay"; |
97 | }; | |
98 | ||
99 | ethernet@30000 { | |
100 | status = "okay"; | |
101 | phy = <&phy1>; | |
0d2e6378 | 102 | phy-mode = "rgmii-id"; |
c49e99c2 MW |
103 | buffer-manager = <&bm>; |
104 | bm,pool-long = <2>; | |
105 | bm,pool-short = <3>; | |
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106 | }; |
107 | ||
a165c3b6 | 108 | usb@58000 { |
9e81775a GC |
109 | status = "ok"; |
110 | }; | |
111 | ||
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112 | ethernet@70000 { |
113 | status = "okay"; | |
114 | phy = <&phy0>; | |
0d2e6378 | 115 | phy-mode = "rgmii-id"; |
c49e99c2 MW |
116 | buffer-manager = <&bm>; |
117 | bm,pool-long = <0>; | |
118 | bm,pool-short = <1>; | |
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119 | }; |
120 | ||
4a25432b | 121 | mdio@72004 { |
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122 | phy0: ethernet-phy@0 { |
123 | reg = <0>; | |
124 | }; | |
125 | ||
126 | phy1: ethernet-phy@1 { | |
127 | reg = <1>; | |
128 | }; | |
129 | }; | |
4de29e63 | 130 | |
d175b6e4 TP |
131 | sata@a8000 { |
132 | status = "okay"; | |
133 | }; | |
134 | ||
135 | sata@e0000 { | |
136 | status = "okay"; | |
137 | }; | |
138 | ||
c49e99c2 MW |
139 | bm@c8000 { |
140 | status = "okay"; | |
141 | }; | |
142 | ||
4de29e63 EG |
143 | flash@d0000 { |
144 | status = "okay"; | |
145 | num-cs = <1>; | |
146 | marvell,nand-keep-config; | |
147 | marvell,nand-enable-arbiter; | |
148 | nand-on-flash-bbt; | |
1ad58443 EG |
149 | nand-ecc-strength = <4>; |
150 | nand-ecc-step-size = <512>; | |
4de29e63 EG |
151 | |
152 | partition@0 { | |
153 | label = "U-Boot"; | |
154 | reg = <0 0x800000>; | |
155 | }; | |
156 | partition@800000 { | |
157 | label = "Linux"; | |
158 | reg = <0x800000 0x800000>; | |
159 | }; | |
160 | partition@1000000 { | |
161 | label = "Filesystem"; | |
162 | reg = <0x1000000 0x3f000000>; | |
163 | }; | |
164 | }; | |
6eccc52b TP |
165 | |
166 | sdhci@d8000 { | |
6eccc52b TP |
167 | broken-cd; |
168 | wp-inverted; | |
169 | bus-width = <8>; | |
170 | status = "okay"; | |
5e949f0c | 171 | no-1-8-v; |
6eccc52b | 172 | }; |
87e2fc37 GC |
173 | |
174 | usb3@f0000 { | |
175 | status = "okay"; | |
176 | }; | |
177 | ||
178 | usb3@f8000 { | |
179 | status = "okay"; | |
180 | }; | |
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181 | }; |
182 | ||
c49e99c2 MW |
183 | bm-bppi { |
184 | status = "okay"; | |
185 | }; | |
186 | ||
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187 | pcie-controller { |
188 | status = "okay"; | |
189 | /* | |
190 | * The two PCIe units are accessible through | |
191 | * standard PCIe slots on the board. | |
192 | */ | |
193 | pcie@1,0 { | |
194 | /* Port 0, Lane 0 */ | |
195 | status = "okay"; | |
196 | }; | |
197 | pcie@2,0 { | |
198 | /* Port 1, Lane 0 */ | |
199 | status = "okay"; | |
200 | }; | |
201 | }; | |
202 | }; | |
203 | }; |