[deliverable/linux.git] / arch / arm / boot / dts / armada-388-gp.dts

/*
 * Device Tree file for Marvell Armada 385 development board
 * (RD-88F6820-GP)
 *
 * Copyright (C) 2014 Marvell
 *
 * Gregory CLEMENT <gregory.clement@free-electrons.com>
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 *  a) This file is licensed under the terms of the GNU General Public
 *     License version 2.  This program is licensed "as is" without
 *     any warranty of any kind, whether express or implied.
 *
 * Or, alternatively,
 *
 *  b) Permission is hereby granted, free of charge, to any person
 *     obtaining a copy of this software and associated documentation
 *     files (the "Software"), to deal in the Software without
 *     restriction, including without limitation the rights to use,
 *     copy, modify, merge, publish, distribute, sublicense, and/or
 *     sell copies of the Software, and to permit persons to whom the
 *     Software is furnished to do so, subject to the following
 *     conditions:
 *
 *     The above copyright notice and this permission notice shall be
 *     included in all copies or substantial portions of the Software.
 *
 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 *     OTHER DEALINGS IN THE SOFTWARE.
 */

/dts-v1/;
#include "armada-388.dtsi"
#include <dt-bindings/gpio/gpio.h>

/ {
	model = "Marvell Armada 385 GP";
	compatible = "marvell,a385-gp", "marvell,armada388", "marvell,armada380";

	chosen {
		bootargs = "console=ttyS0,115200";
		stdout-path = &uart0;
	};

	memory {
		device_type = "memory";
		reg = <0x00000000 0x80000000>; /* 2 GB */
	};

	soc {
		ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
			  MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;

		internal-regs {
			spi@10600 {
				pinctrl-names = "default";
				pinctrl-0 = <&spi0_pins>;
				status = "okay";

				spi-flash@0 {
					#address-cells = <1>;
					#size-cells = <1>;
					compatible = "st,m25p128";
					reg = <0>; /* Chip select 0 */
					spi-max-frequency = <50000000>;
					m25p,fast-read;
				};
			};

			i2c@11000 {
				pinctrl-names = "default";
				pinctrl-0 = <&i2c0_pins>;
				status = "okay";
				clock-frequency = <100000>;
				/*
				 * The EEPROM located at adresse 54 is needed
				 * for the boot - DO NOT ERASE IT -
				 */

				expander0: pca9555@20 {
					compatible = "nxp,pca9555";
					pinctrl-names = "default";
					pinctrl-0 = <&pca0_pins>;
					interrupt-parent = <&gpio0>;
					interrupts = <18 IRQ_TYPE_EDGE_FALLING>;
					gpio-controller;
					#gpio-cells = <2>;
					interrupt-controller;
					#interrupt-cells = <2>;
					reg = <0x20>;
				};

				expander1: pca9555@21 {
					compatible = "nxp,pca9555";
					pinctrl-names = "default";
					interrupt-parent = <&gpio0>;
					interrupts = <18 IRQ_TYPE_EDGE_FALLING>;
					gpio-controller;
					#gpio-cells = <2>;
					interrupt-controller;
					#interrupt-cells = <2>;
					reg = <0x21>;
				};

			};

			serial@12000 {
				/*
				 * Exported on the micro USB connector CON16
				 * through an FTDI
				 */

				pinctrl-names = "default";
				pinctrl-0 = <&uart0_pins>;
				status = "okay";
			};

			/* GE1 CON15 */
			ethernet@30000 {
				pinctrl-names = "default";
				pinctrl-0 = <&ge1_rgmii_pins>;
				status = "okay";
				phy = <&phy1>;
				phy-mode = "rgmii-id";
			};

			/* CON4 */
			usb@50000 {
				vcc-supply = <&reg_usb2_0_vbus>;
				status = "okay";
			};

			/* GE0 CON1 */
			ethernet@70000 {
				pinctrl-names = "default";
				/*
				 * The Reference Clock 0 is used to provide a
				 * clock to the PHY
				 */
				pinctrl-0 = <&ge0_rgmii_pins>, <&ref_clk0_pins>;
				status = "okay";
				phy = <&phy0>;
				phy-mode = "rgmii-id";
			};


			mdio@72004 {
				pinctrl-names = "default";
				pinctrl-0 = <&mdio_pins>;

				phy0: ethernet-phy@1 {
					reg = <1>;
				};

				phy1: ethernet-phy@0 {
					reg = <0>;
				};
			};

			sata@a8000 {
				pinctrl-names = "default";
				pinctrl-0 = <&sata0_pins>, <&sata1_pins>;
				status = "okay";
				#address-cells = <1>;
				#size-cells = <0>;
			};

			sata@e0000 {
				pinctrl-names = "default";
				pinctrl-0 = <&sata2_pins>, <&sata3_pins>;
				status = "okay";
				#address-cells = <1>;
				#size-cells = <0>;
			};

			sdhci@d8000 {
				pinctrl-names = "default";
				pinctrl-0 = <&sdhci_pins>;
				cd-gpios = <&expander0 5 GPIO_ACTIVE_LOW>;
				no-1-8-v;
				wp-inverted;
				bus-width = <8>;
				status = "okay";
			};

			/* CON5 */
			usb3@f0000 {
				vcc-supply = <&reg_usb2_1_vbus>;
				status = "okay";
			};

			/* CON7 */
			usb3@f8000 {
				vcc-supply = <&reg_usb3_vbus>;
				status = "okay";
			};
		};

		pcie-controller {
			status = "okay";
			/*
			 * One PCIe units is accessible through
			 * standard PCIe slot on the board.
			 */
			pcie@1,0 {
				/* Port 0, Lane 0 */
				status = "okay";
			};

			/*
			 * The two other PCIe units are accessible
			 * through mini PCIe slot on the board.
			 */
			pcie@2,0 {
				/* Port 1, Lane 0 */
				status = "okay";
			};
			pcie@3,0 {
				/* Port 2, Lane 0 */
				status = "okay";
			};
		};

		gpio-fan {
			compatible = "gpio-fan";
			gpios = <&expander1 3 GPIO_ACTIVE_HIGH>;
			gpio-fan,speed-map = <	 0 0
					      3000 1>;
		};
	};

	reg_usb3_vbus: usb3-vbus {
		compatible = "regulator-fixed";
		regulator-name = "usb3-vbus";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		enable-active-high;
		regulator-always-on;
		gpio = <&expander1 15 GPIO_ACTIVE_HIGH>;
	};

	reg_usb2_0_vbus: v5-vbus0 {
		compatible = "regulator-fixed";
		regulator-name = "v5.0-vbus0";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		enable-active-high;
		regulator-always-on;
		gpio = <&expander1 14 GPIO_ACTIVE_HIGH>;
	};

	reg_usb2_1_vbus: v5-vbus1 {
		compatible = "regulator-fixed";
		regulator-name = "v5.0-vbus1";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		enable-active-high;
		regulator-always-on;
		gpio = <&expander0 4 GPIO_ACTIVE_HIGH>;
	};

	reg_usb2_1_vbus: v5-vbus1 {
		compatible = "regulator-fixed";
		regulator-name = "v5.0-vbus1";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		enable-active-high;
		regulator-always-on;
		gpio = <&expander0 4 GPIO_ACTIVE_HIGH>;
	};
};

&pinctrl {
	pca0_pins: pca0_pins {
		marvell,pins = "mpp18";
		marvell,function = "gpio";
	};
};
Commit	Line	Data
928413bd GC	1	/*
	2	* Device Tree file for Marvell Armada 385 development board
	3	* (RD-88F6820-GP)
	4	*
	5	* Copyright (C) 2014 Marvell
	6	*
	7	* Gregory CLEMENT <gregory.clement@free-electrons.com>
	8	*
	9	* This file is dual-licensed: you can use it either under the terms
	10	* of the GPL or the X11 license, at your option. Note that this dual
	11	* licensing only applies to this file, and not this project as a
	12	* whole.
	13	*
	14	* a) This file is licensed under the terms of the GNU General Public
	15	* License version 2. This program is licensed "as is" without
	16	* any warranty of any kind, whether express or implied.
	17	*
	18	* Or, alternatively,
	19	*
	20	* b) Permission is hereby granted, free of charge, to any person
	21	* obtaining a copy of this software and associated documentation
	22	* files (the "Software"), to deal in the Software without
	23	* restriction, including without limitation the rights to use,
	24	* copy, modify, merge, publish, distribute, sublicense, and/or
	25	* sell copies of the Software, and to permit persons to whom the
	26	* Software is furnished to do so, subject to the following
	27	* conditions:
	28	*
	29	* The above copyright notice and this permission notice shall be
	30	* included in all copies or substantial portions of the Software.
	31	*
	32	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	33	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
	34	* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	35	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
	36	* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
	37	* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	38	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	39	* OTHER DEALINGS IN THE SOFTWARE.
	40	*/
	41
	42	/dts-v1/;
	43	#include "armada-388.dtsi"
	44	#include <dt-bindings/gpio/gpio.h>
	45
	46	/ {
	47	model = "Marvell Armada 385 GP";
	48	compatible = "marvell,a385-gp", "marvell,armada388", "marvell,armada380";
	49
	50	chosen {
	51	bootargs = "console=ttyS0,115200";
	52	stdout-path = &uart0;
	53	};
	54
	55	memory {
	56	device_type = "memory";
	57	reg = <0x00000000 0x80000000>; /* 2 GB */
	58	};
	59
	60	soc {
	61	ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
	62	MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;
	63
	64	internal-regs {
65	spi@10600 {
66	pinctrl-names = "default";
67	pinctrl-0 = <&spi0_pins>;
68	status = "okay";
69
70	spi-flash@0 {
71	#address-cells = <1>;
72	#size-cells = <1>;
73	compatible = "st,m25p128";
74	reg = <0>; /* Chip select 0 */
75	spi-max-frequency = <50000000>;
76	m25p,fast-read;
77	};
78	};
79
80	i2c@11000 {
81	pinctrl-names = "default";
82	pinctrl-0 = <&i2c0_pins>;
83	status = "okay";
84	clock-frequency = <100000>;
85	/*
86	* The EEPROM located at adresse 54 is needed
87	* for the boot - DO NOT ERASE IT -
88	*/
89
90	expander0: pca9555@20 {
91	compatible = "nxp,pca9555";
92	pinctrl-names = "default";
93	pinctrl-0 = <&pca0_pins>;
94	interrupt-parent = <&gpio0>;
95	interrupts = <18 IRQ_TYPE_EDGE_FALLING>;
96	gpio-controller;
97	#gpio-cells = <2>;
98	interrupt-controller;
99	#interrupt-cells = <2>;
100	reg = <0x20>;
101	};
102
103	expander1: pca9555@21 {
104	compatible = "nxp,pca9555";
105	pinctrl-names = "default";
106	interrupt-parent = <&gpio0>;
107	interrupts = <18 IRQ_TYPE_EDGE_FALLING>;
108	gpio-controller;
109	#gpio-cells = <2>;
110	interrupt-controller;
111	#interrupt-cells = <2>;
112	reg = <0x21>;
113	};
114
115	};
116
117	serial@12000 {
118	/*
119	* Exported on the micro USB connector CON16
120	* through an FTDI
121	*/
122
123	pinctrl-names = "default";
124	pinctrl-0 = <&uart0_pins>;
125	status = "okay";
126	};
127
128	/* GE1 CON15 */
129	ethernet@30000 {
130	pinctrl-names = "default";
131	pinctrl-0 = <&ge1_rgmii_pins>;
132	status = "okay";
133	phy = <&phy1>;
134	phy-mode = "rgmii-id";
135	};
136
137	/* CON4 */
138	usb@50000 {
139	vcc-supply = <&reg_usb2_0_vbus>;
140	status = "okay";
141	};
142
143	/* GE0 CON1 */
144	ethernet@70000 {
145	pinctrl-names = "default";
146	/*
147	* The Reference Clock 0 is used to provide a
148	* clock to the PHY
149	*/
150	pinctrl-0 = <&ge0_rgmii_pins>, <&ref_clk0_pins>;
151	status = "okay";
152	phy = <&phy0>;
153	phy-mode = "rgmii-id";
154	};
155
156
157	mdio@72004 {
158	pinctrl-names = "default";
159	pinctrl-0 = <&mdio_pins>;
160
161	phy0: ethernet-phy@1 {
162	reg = <1>;
163	};
164
165	phy1: ethernet-phy@0 {
166	reg = <0>;
167	};
168	};
169
170	sata@a8000 {
171	pinctrl-names = "default";
172	pinctrl-0 = <&sata0_pins>, <&sata1_pins>;
173	status = "okay";
174	#address-cells = <1>;
175	#size-cells = <0>;
176	};
177
178	sata@e0000 {
179	pinctrl-names = "default";
180	pinctrl-0 = <&sata2_pins>, <&sata3_pins>;
181	status = "okay";
182	#address-cells = <1>;
183	#size-cells = <0>;
184	};
185
186	sdhci@d8000 {
187	pinctrl-names = "default";
188	pinctrl-0 = <&sdhci_pins>;
189	cd-gpios = <&expander0 5 GPIO_ACTIVE_LOW>;
190	no-1-8-v;
191	wp-inverted;
192	bus-width = <8>;
193	status = "okay";
194	};
195
196	/* CON5 */
197	usb3@f0000 {
198	vcc-supply = <&reg_usb2_1_vbus>;
199	status = "okay";
200	};
201
202	/* CON7 */
203	usb3@f8000 {
204	vcc-supply = <&reg_usb3_vbus>;
205	status = "okay";
206	};
207	};
208
209	pcie-controller {
210	status = "okay";
211	/*
212	* One PCIe units is accessible through
213	* standard PCIe slot on the board.
214	*/
215	pcie@1,0 {
216	/* Port 0, Lane 0 */
217	status = "okay";
218	};
219
220	/*
221	* The two other PCIe units are accessible
222	* through mini PCIe slot on the board.
223	*/
224	pcie@2,0 {
225	/* Port 1, Lane 0 */
226	status = "okay";
227	};
228	pcie@3,0 {
229	/* Port 2, Lane 0 */
230	status = "okay";
231	};
232	};
233
234	gpio-fan {
235	compatible = "gpio-fan";
236	gpios = <&expander1 3 GPIO_ACTIVE_HIGH>;
237	gpio-fan,speed-map = < 0 0
238	3000 1>;
239	};
240	};
241
242	reg_usb3_vbus: usb3-vbus {
243	compatible = "regulator-fixed";
244	regulator-name = "usb3-vbus";
245	regulator-min-microvolt = <5000000>;
246	regulator-max-microvolt = <5000000>;
247	enable-active-high;
248	regulator-always-on;
249	gpio = <&expander1 15 GPIO_ACTIVE_HIGH>;
250	};
251
252	reg_usb2_0_vbus: v5-vbus0 {
253	compatible = "regulator-fixed";
254	regulator-name = "v5.0-vbus0";
255	regulator-min-microvolt = <5000000>;
256	regulator-max-microvolt = <5000000>;
257	enable-active-high;
258	regulator-always-on;
259	gpio = <&expander1 14 GPIO_ACTIVE_HIGH>;
260	};
261
262	reg_usb2_1_vbus: v5-vbus1 {
263	compatible = "regulator-fixed";
264	regulator-name = "v5.0-vbus1";
265	regulator-min-microvolt = <5000000>;
266	regulator-max-microvolt = <5000000>;
267	enable-active-high;
268	regulator-always-on;
269	gpio = <&expander0 4 GPIO_ACTIVE_HIGH>;
270	};
271
272	reg_usb2_1_vbus: v5-vbus1 {
273	compatible = "regulator-fixed";
274	regulator-name = "v5.0-vbus1";
275	regulator-min-microvolt = <5000000>;
276	regulator-max-microvolt = <5000000>;
277	enable-active-high;
278	regulator-always-on;
279	gpio = <&expander0 4 GPIO_ACTIVE_HIGH>;
280	};
281	};
282
283	&pinctrl {
284	pca0_pins: pca0_pins {
285	marvell,pins = "mpp18";
286	marvell,function = "gpio";
287	};
288	};