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0d3d96ab TP |
1 | /* |
2 | * Device Tree Include file for Marvell Armada 38x family of SoCs. | |
3 | * | |
4 | * Copyright (C) 2014 Marvell | |
5 | * | |
6 | * Lior Amsalem <alior@marvell.com> | |
7 | * Gregory CLEMENT <gregory.clement@free-electrons.com> | |
8 | * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> | |
9 | * | |
7674432f GC |
10 | * This file is dual-licensed: you can use it either under the terms |
11 | * of the GPL or the X11 license, at your option. Note that this dual | |
12 | * licensing only applies to this file, and not this project as a | |
13 | * whole. | |
14 | * | |
15 | * a) This file is free software; you can redistribute it and/or | |
16 | * modify it under the terms of the GNU General Public License as | |
17 | * published by the Free Software Foundation; either version 2 of the | |
18 | * License, or (at your option) any later version. | |
19 | * | |
20 | * This file is distributed in the hope that it will be useful | |
21 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
22 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
23 | * GNU General Public License for more details. | |
24 | * | |
25 | * Or, alternatively | |
26 | * | |
27 | * b) Permission is hereby granted, free of charge, to any person | |
28 | * obtaining a copy of this software and associated documentation | |
29 | * files (the "Software"), to deal in the Software without | |
30 | * restriction, including without limitation the rights to use | |
31 | * copy, modify, merge, publish, distribute, sublicense, and/or | |
32 | * sell copies of the Software, and to permit persons to whom the | |
33 | * Software is furnished to do so, subject to the following | |
34 | * conditions: | |
35 | * | |
36 | * The above copyright notice and this permission notice shall be | |
37 | * included in all copies or substantial portions of the Software. | |
38 | * | |
39 | * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND | |
40 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES | |
41 | * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
42 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT | |
43 | * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY | |
44 | * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
45 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
46 | * OTHER DEALINGS IN THE SOFTWARE. | |
0d3d96ab TP |
47 | */ |
48 | ||
49 | #include "skeleton.dtsi" | |
f327d43d | 50 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
d11548e3 | 51 | #include <dt-bindings/interrupt-controller/irq.h> |
0d3d96ab TP |
52 | |
53 | #define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16)) | |
54 | ||
55 | / { | |
56 | model = "Marvell Armada 38x family SoC"; | |
8dbdb8e7 | 57 | compatible = "marvell,armada380"; |
0d3d96ab TP |
58 | |
59 | aliases { | |
60 | gpio0 = &gpio0; | |
61 | gpio1 = &gpio1; | |
bf6acf16 TP |
62 | serial0 = &uart0; |
63 | serial1 = &uart1; | |
0d3d96ab TP |
64 | }; |
65 | ||
754c4b1b EG |
66 | pmu { |
67 | compatible = "arm,cortex-a9-pmu"; | |
68 | interrupts-extended = <&mpic 3>; | |
69 | }; | |
70 | ||
0d3d96ab | 71 | soc { |
a9e274c4 | 72 | compatible = "marvell,armada380-mbus", "simple-bus"; |
0d3d96ab TP |
73 | #address-cells = <2>; |
74 | #size-cells = <1>; | |
75 | controller = <&mbusc>; | |
76 | interrupt-parent = <&gic>; | |
77 | pcie-mem-aperture = <0xe0000000 0x8000000>; | |
78 | pcie-io-aperture = <0xe8000000 0x100000>; | |
79 | ||
80 | bootrom { | |
81 | compatible = "marvell,bootrom"; | |
82 | reg = <MBUS_ID(0x01, 0x1d) 0 0x200000>; | |
83 | }; | |
84 | ||
85 | devbus-bootcs { | |
86 | compatible = "marvell,mvebu-devbus"; | |
87 | reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>; | |
88 | ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>; | |
89 | #address-cells = <1>; | |
90 | #size-cells = <1>; | |
91 | clocks = <&coreclk 0>; | |
92 | status = "disabled"; | |
93 | }; | |
94 | ||
95 | devbus-cs0 { | |
96 | compatible = "marvell,mvebu-devbus"; | |
97 | reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>; | |
98 | ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>; | |
99 | #address-cells = <1>; | |
100 | #size-cells = <1>; | |
101 | clocks = <&coreclk 0>; | |
102 | status = "disabled"; | |
103 | }; | |
104 | ||
105 | devbus-cs1 { | |
106 | compatible = "marvell,mvebu-devbus"; | |
107 | reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>; | |
108 | ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>; | |
109 | #address-cells = <1>; | |
110 | #size-cells = <1>; | |
111 | clocks = <&coreclk 0>; | |
112 | status = "disabled"; | |
113 | }; | |
114 | ||
115 | devbus-cs2 { | |
116 | compatible = "marvell,mvebu-devbus"; | |
117 | reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>; | |
118 | ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>; | |
119 | #address-cells = <1>; | |
120 | #size-cells = <1>; | |
121 | clocks = <&coreclk 0>; | |
122 | status = "disabled"; | |
123 | }; | |
124 | ||
125 | devbus-cs3 { | |
126 | compatible = "marvell,mvebu-devbus"; | |
127 | reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>; | |
128 | ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>; | |
129 | #address-cells = <1>; | |
130 | #size-cells = <1>; | |
131 | clocks = <&coreclk 0>; | |
132 | status = "disabled"; | |
133 | }; | |
134 | ||
135 | internal-regs { | |
136 | compatible = "simple-bus"; | |
137 | #address-cells = <1>; | |
138 | #size-cells = <1>; | |
139 | ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>; | |
140 | ||
141 | L2: cache-controller@8000 { | |
142 | compatible = "arm,pl310-cache"; | |
143 | reg = <0x8000 0x1000>; | |
144 | cache-unified; | |
145 | cache-level = <2>; | |
146 | }; | |
147 | ||
964a6156 TP |
148 | scu@c000 { |
149 | compatible = "arm,cortex-a9-scu"; | |
150 | reg = <0xc000 0x58>; | |
151 | }; | |
152 | ||
0d3d96ab TP |
153 | timer@c600 { |
154 | compatible = "arm,cortex-a9-twd-timer"; | |
155 | reg = <0xc600 0x20>; | |
d11548e3 | 156 | interrupts = <GIC_PPI 13 (IRQ_TYPE_EDGE_RISING | GIC_CPU_MASK_SIMPLE(2))>; |
0d3d96ab TP |
157 | clocks = <&coreclk 2>; |
158 | }; | |
159 | ||
160 | gic: interrupt-controller@d000 { | |
161 | compatible = "arm,cortex-a9-gic"; | |
162 | #interrupt-cells = <3>; | |
163 | #size-cells = <0>; | |
164 | interrupt-controller; | |
165 | reg = <0xd000 0x1000>, | |
166 | <0xc100 0x100>; | |
167 | }; | |
168 | ||
169 | spi0: spi@10600 { | |
170 | compatible = "marvell,orion-spi"; | |
171 | reg = <0x10600 0x50>; | |
172 | #address-cells = <1>; | |
173 | #size-cells = <0>; | |
174 | cell-index = <0>; | |
d11548e3 | 175 | interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; |
0d3d96ab TP |
176 | clocks = <&coreclk 0>; |
177 | status = "disabled"; | |
178 | }; | |
179 | ||
180 | spi1: spi@10680 { | |
181 | compatible = "marvell,orion-spi"; | |
182 | reg = <0x10680 0x50>; | |
183 | #address-cells = <1>; | |
184 | #size-cells = <0>; | |
185 | cell-index = <1>; | |
d11548e3 | 186 | interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; |
0d3d96ab TP |
187 | clocks = <&coreclk 0>; |
188 | status = "disabled"; | |
189 | }; | |
190 | ||
191 | i2c0: i2c@11000 { | |
192 | compatible = "marvell,mv64xxx-i2c"; | |
193 | reg = <0x11000 0x20>; | |
194 | #address-cells = <1>; | |
195 | #size-cells = <0>; | |
d11548e3 | 196 | interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; |
0d3d96ab TP |
197 | timeout-ms = <1000>; |
198 | clocks = <&coreclk 0>; | |
199 | status = "disabled"; | |
200 | }; | |
201 | ||
202 | i2c1: i2c@11100 { | |
203 | compatible = "marvell,mv64xxx-i2c"; | |
204 | reg = <0x11100 0x20>; | |
205 | #address-cells = <1>; | |
206 | #size-cells = <0>; | |
d11548e3 | 207 | interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; |
0d3d96ab TP |
208 | timeout-ms = <1000>; |
209 | clocks = <&coreclk 0>; | |
210 | status = "disabled"; | |
211 | }; | |
212 | ||
10c5c472 | 213 | uart0: serial@12000 { |
0d3d96ab TP |
214 | compatible = "snps,dw-apb-uart"; |
215 | reg = <0x12000 0x100>; | |
216 | reg-shift = <2>; | |
d11548e3 | 217 | interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; |
0d3d96ab | 218 | reg-io-width = <1>; |
64939dc5 | 219 | clocks = <&coreclk 0>; |
0d3d96ab TP |
220 | status = "disabled"; |
221 | }; | |
222 | ||
8a48dccb | 223 | uart1: serial@12100 { |
0d3d96ab TP |
224 | compatible = "snps,dw-apb-uart"; |
225 | reg = <0x12100 0x100>; | |
226 | reg-shift = <2>; | |
d11548e3 | 227 | interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; |
0d3d96ab | 228 | reg-io-width = <1>; |
64939dc5 | 229 | clocks = <&coreclk 0>; |
0d3d96ab TP |
230 | status = "disabled"; |
231 | }; | |
232 | ||
10c5c472 | 233 | pinctrl: pinctrl@18000 { |
0d3d96ab | 234 | reg = <0x18000 0x20>; |
91b4c91f MR |
235 | |
236 | ge0_rgmii_pins: ge-rgmii-pins-0 { | |
237 | marvell,pins = "mpp6", "mpp7", "mpp8", | |
238 | "mpp9", "mpp10", "mpp11", | |
239 | "mpp12", "mpp13", "mpp14", | |
240 | "mpp15", "mpp16", "mpp17"; | |
241 | marvell,function = "ge0"; | |
242 | }; | |
243 | ||
34598503 GC |
244 | ge1_rgmii_pins: ge-rgmii-pins-1 { |
245 | marvell,pins = "mpp21", "mpp27", "mpp28", | |
246 | "mpp29", "mpp30", "mpp31", | |
247 | "mpp32", "mpp37", "mpp38", | |
248 | "mpp39", "mpp40", "mpp41"; | |
249 | marvell,function = "ge1"; | |
250 | }; | |
251 | ||
91b4c91f MR |
252 | i2c0_pins: i2c-pins-0 { |
253 | marvell,pins = "mpp2", "mpp3"; | |
254 | marvell,function = "i2c0"; | |
255 | }; | |
256 | ||
257 | mdio_pins: mdio-pins { | |
258 | marvell,pins = "mpp4", "mpp5"; | |
259 | marvell,function = "ge"; | |
260 | }; | |
261 | ||
262 | ref_clk0_pins: ref-clk-pins-0 { | |
263 | marvell,pins = "mpp45"; | |
264 | marvell,function = "ref"; | |
265 | }; | |
266 | ||
34598503 GC |
267 | ref_clk1_pins: ref-clk-pins-1 { |
268 | marvell,pins = "mpp46"; | |
269 | marvell,function = "ref"; | |
270 | }; | |
271 | ||
272 | spi0_pins: spi-pins-0 { | |
273 | marvell,pins = "mpp22", "mpp23", "mpp24", | |
274 | "mpp25"; | |
275 | marvell,function = "spi0"; | |
276 | }; | |
277 | ||
91b4c91f MR |
278 | spi1_pins: spi-pins-1 { |
279 | marvell,pins = "mpp56", "mpp57", "mpp58", | |
280 | "mpp59"; | |
281 | marvell,function = "spi1"; | |
282 | }; | |
283 | ||
284 | uart0_pins: uart-pins-0 { | |
285 | marvell,pins = "mpp0", "mpp1"; | |
286 | marvell,function = "ua0"; | |
287 | }; | |
288 | ||
289 | uart1_pins: uart-pins-1 { | |
290 | marvell,pins = "mpp19", "mpp20"; | |
291 | marvell,function = "ua1"; | |
292 | }; | |
34598503 GC |
293 | |
294 | sdhci_pins: sdhci-pins { | |
295 | marvell,pins = "mpp48", "mpp49", "mpp50", | |
296 | "mpp52", "mpp53", "mpp54", | |
297 | "mpp55", "mpp57", "mpp58", | |
298 | "mpp59"; | |
299 | marvell,function = "sd0"; | |
300 | }; | |
301 | ||
302 | sata0_pins: sata-pins-0 { | |
303 | marvell,pins = "mpp20"; | |
304 | marvell,function = "sata0"; | |
305 | }; | |
306 | ||
307 | sata1_pins: sata-pins-1 { | |
308 | marvell,pins = "mpp19"; | |
309 | marvell,function = "sata1"; | |
310 | }; | |
311 | ||
312 | sata2_pins: sata-pins-2 { | |
313 | marvell,pins = "mpp47"; | |
314 | marvell,function = "sata2"; | |
315 | }; | |
316 | ||
317 | sata3_pins: sata-pins-3 { | |
318 | marvell,pins = "mpp44"; | |
319 | marvell,function = "sata3"; | |
320 | }; | |
0d3d96ab TP |
321 | }; |
322 | ||
323 | gpio0: gpio@18100 { | |
324 | compatible = "marvell,orion-gpio"; | |
325 | reg = <0x18100 0x40>; | |
326 | ngpios = <32>; | |
327 | gpio-controller; | |
328 | #gpio-cells = <2>; | |
329 | interrupt-controller; | |
330 | #interrupt-cells = <2>; | |
d11548e3 TP |
331 | interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, |
332 | <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, | |
333 | <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, | |
334 | <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; | |
0d3d96ab TP |
335 | }; |
336 | ||
337 | gpio1: gpio@18140 { | |
338 | compatible = "marvell,orion-gpio"; | |
339 | reg = <0x18140 0x40>; | |
340 | ngpios = <28>; | |
341 | gpio-controller; | |
342 | #gpio-cells = <2>; | |
343 | interrupt-controller; | |
344 | #interrupt-cells = <2>; | |
d11548e3 TP |
345 | interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, |
346 | <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, | |
347 | <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, | |
348 | <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; | |
0d3d96ab TP |
349 | }; |
350 | ||
351 | system-controller@18200 { | |
352 | compatible = "marvell,armada-380-system-controller", | |
353 | "marvell,armada-370-xp-system-controller"; | |
354 | reg = <0x18200 0x100>; | |
355 | }; | |
356 | ||
357 | gateclk: clock-gating-control@18220 { | |
358 | compatible = "marvell,armada-380-gating-clock"; | |
359 | reg = <0x18220 0x4>; | |
360 | clocks = <&coreclk 0>; | |
361 | #clock-cells = <1>; | |
362 | }; | |
363 | ||
364 | coreclk: mvebu-sar@18600 { | |
365 | compatible = "marvell,armada-380-core-clock"; | |
366 | reg = <0x18600 0x04>; | |
367 | #clock-cells = <1>; | |
368 | }; | |
369 | ||
370 | mbusc: mbus-controller@20000 { | |
371 | compatible = "marvell,mbus-controller"; | |
372 | reg = <0x20000 0x100>, <0x20180 0x20>; | |
373 | }; | |
374 | ||
1d7b0839 | 375 | mpic: interrupt-controller@20a00 { |
0d3d96ab TP |
376 | compatible = "marvell,mpic"; |
377 | reg = <0x20a00 0x2d0>, <0x21070 0x58>; | |
378 | #interrupt-cells = <1>; | |
379 | #size-cells = <1>; | |
380 | interrupt-controller; | |
381 | msi-controller; | |
d11548e3 | 382 | interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>; |
0d3d96ab TP |
383 | }; |
384 | ||
385 | timer@20300 { | |
386 | compatible = "marvell,armada-380-timer", | |
387 | "marvell,armada-xp-timer"; | |
388 | reg = <0x20300 0x30>, <0x21040 0x30>; | |
d11548e3 TP |
389 | interrupts-extended = <&gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, |
390 | <&gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, | |
391 | <&gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, | |
392 | <&gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, | |
0d3d96ab TP |
393 | <&mpic 5>, |
394 | <&mpic 6>; | |
395 | clocks = <&coreclk 2>, <&refclk>; | |
396 | clock-names = "nbclk", "fixed"; | |
397 | }; | |
398 | ||
153a964a EG |
399 | watchdog@20300 { |
400 | compatible = "marvell,armada-380-wdt"; | |
401 | reg = <0x20300 0x34>, <0x20704 0x4>, <0x18260 0x4>; | |
402 | clocks = <&coreclk 2>, <&refclk>; | |
403 | clock-names = "nbclk", "fixed"; | |
404 | }; | |
405 | ||
19b06d7f TP |
406 | cpurst@20800 { |
407 | compatible = "marvell,armada-370-cpu-reset"; | |
408 | reg = <0x20800 0x10>; | |
409 | }; | |
410 | ||
d7f3ec2b GC |
411 | mpcore-soc-ctrl@20d20 { |
412 | compatible = "marvell,armada-380-mpcore-soc-ctrl"; | |
413 | reg = <0x20d20 0x6c>; | |
414 | }; | |
415 | ||
964a6156 TP |
416 | coherency-fabric@21010 { |
417 | compatible = "marvell,armada-380-coherency-fabric"; | |
418 | reg = <0x21010 0x1c>; | |
419 | }; | |
420 | ||
19b06d7f TP |
421 | pmsu@22000 { |
422 | compatible = "marvell,armada-380-pmsu"; | |
423 | reg = <0x22000 0x1000>; | |
424 | }; | |
425 | ||
0d3d96ab TP |
426 | eth1: ethernet@30000 { |
427 | compatible = "marvell,armada-370-neta"; | |
428 | reg = <0x30000 0x4000>; | |
429 | interrupts-extended = <&mpic 10>; | |
430 | clocks = <&gateclk 3>; | |
431 | status = "disabled"; | |
432 | }; | |
433 | ||
434 | eth2: ethernet@34000 { | |
435 | compatible = "marvell,armada-370-neta"; | |
436 | reg = <0x34000 0x4000>; | |
437 | interrupts-extended = <&mpic 12>; | |
438 | clocks = <&gateclk 2>; | |
439 | status = "disabled"; | |
440 | }; | |
441 | ||
a165c3b6 | 442 | usb@58000 { |
9e81775a GC |
443 | compatible = "marvell,orion-ehci"; |
444 | reg = <0x58000 0x500>; | |
445 | interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; | |
446 | clocks = <&gateclk 18>; | |
447 | status = "disabled"; | |
448 | }; | |
449 | ||
0d3d96ab TP |
450 | xor@60800 { |
451 | compatible = "marvell,orion-xor"; | |
452 | reg = <0x60800 0x100 | |
453 | 0x60a00 0x100>; | |
454 | clocks = <&gateclk 22>; | |
455 | status = "okay"; | |
456 | ||
457 | xor00 { | |
d11548e3 | 458 | interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; |
0d3d96ab TP |
459 | dmacap,memcpy; |
460 | dmacap,xor; | |
461 | }; | |
462 | xor01 { | |
d11548e3 | 463 | interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; |
0d3d96ab TP |
464 | dmacap,memcpy; |
465 | dmacap,xor; | |
466 | dmacap,memset; | |
467 | }; | |
468 | }; | |
469 | ||
470 | xor@60900 { | |
471 | compatible = "marvell,orion-xor"; | |
472 | reg = <0x60900 0x100 | |
473 | 0x60b00 0x100>; | |
474 | clocks = <&gateclk 28>; | |
475 | status = "okay"; | |
476 | ||
477 | xor10 { | |
d11548e3 | 478 | interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; |
0d3d96ab TP |
479 | dmacap,memcpy; |
480 | dmacap,xor; | |
481 | }; | |
482 | xor11 { | |
d11548e3 | 483 | interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; |
0d3d96ab TP |
484 | dmacap,memcpy; |
485 | dmacap,xor; | |
486 | dmacap,memset; | |
487 | }; | |
488 | }; | |
489 | ||
490 | eth0: ethernet@70000 { | |
491 | compatible = "marvell,armada-370-neta"; | |
492 | reg = <0x70000 0x4000>; | |
493 | interrupts-extended = <&mpic 8>; | |
494 | clocks = <&gateclk 4>; | |
495 | status = "disabled"; | |
496 | }; | |
497 | ||
4a25432b | 498 | mdio@72004 { |
0d3d96ab TP |
499 | #address-cells = <1>; |
500 | #size-cells = <0>; | |
501 | compatible = "marvell,orion-mdio"; | |
502 | reg = <0x72004 0x4>; | |
33faf20b | 503 | clocks = <&gateclk 4>; |
0d3d96ab | 504 | }; |
d6bd4b4c | 505 | |
a73c7305 GC |
506 | rtc@a3800 { |
507 | compatible = "marvell,armada-380-rtc"; | |
508 | reg = <0xa3800 0x20>, <0x184a0 0x0c>; | |
509 | reg-names = "rtc", "rtc-soc"; | |
510 | interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; | |
511 | }; | |
512 | ||
d175b6e4 TP |
513 | sata@a8000 { |
514 | compatible = "marvell,armada-380-ahci"; | |
515 | reg = <0xa8000 0x2000>; | |
516 | interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; | |
517 | clocks = <&gateclk 15>; | |
518 | status = "disabled"; | |
519 | }; | |
520 | ||
521 | sata@e0000 { | |
522 | compatible = "marvell,armada-380-ahci"; | |
523 | reg = <0xe0000 0x2000>; | |
524 | interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; | |
525 | clocks = <&gateclk 30>; | |
526 | status = "disabled"; | |
527 | }; | |
528 | ||
d6bd4b4c EG |
529 | coredivclk: clock@e4250 { |
530 | compatible = "marvell,armada-380-corediv-clock"; | |
531 | reg = <0xe4250 0xc>; | |
532 | #clock-cells = <1>; | |
533 | clocks = <&mainpll>; | |
534 | clock-output-names = "nand"; | |
535 | }; | |
93b5577e | 536 | |
c630829a EG |
537 | thermal@e8078 { |
538 | compatible = "marvell,armada380-thermal"; | |
539 | reg = <0xe4078 0x4>, <0xe4074 0x4>; | |
540 | status = "okay"; | |
541 | }; | |
542 | ||
93b5577e EG |
543 | flash@d0000 { |
544 | compatible = "marvell,armada370-nand"; | |
545 | reg = <0xd0000 0x54>; | |
546 | #address-cells = <1>; | |
547 | #size-cells = <1>; | |
548 | interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; | |
549 | clocks = <&coredivclk 0>; | |
550 | status = "disabled"; | |
551 | }; | |
6eccc52b TP |
552 | |
553 | sdhci@d8000 { | |
554 | compatible = "marvell,armada-380-sdhci"; | |
ddbdc579 GC |
555 | reg-names = "sdhci", "mbus", "conf-sdio3"; |
556 | reg = <0xd8000 0x1000>, | |
557 | <0xdc000 0x100>, | |
558 | <0x18454 0x4>; | |
b757258a | 559 | interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; |
6eccc52b TP |
560 | clocks = <&gateclk 17>; |
561 | mrvl,clk-delay-cycles = <0x1F>; | |
562 | status = "disabled"; | |
563 | }; | |
87e2fc37 GC |
564 | |
565 | usb3@f0000 { | |
566 | compatible = "marvell,armada-380-xhci"; | |
567 | reg = <0xf0000 0x4000>,<0xf4000 0x4000>; | |
568 | interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; | |
569 | clocks = <&gateclk 9>; | |
570 | status = "disabled"; | |
571 | }; | |
572 | ||
573 | usb3@f8000 { | |
574 | compatible = "marvell,armada-380-xhci"; | |
575 | reg = <0xf8000 0x4000>,<0xfc000 0x4000>; | |
576 | interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; | |
577 | clocks = <&gateclk 10>; | |
578 | status = "disabled"; | |
579 | }; | |
0d3d96ab TP |
580 | }; |
581 | }; | |
582 | ||
583 | clocks { | |
5bc94c99 EG |
584 | /* 2 GHz fixed main PLL */ |
585 | mainpll: mainpll { | |
586 | compatible = "fixed-clock"; | |
587 | #clock-cells = <0>; | |
588 | clock-frequency = <2000000000>; | |
589 | }; | |
590 | ||
0d3d96ab TP |
591 | /* 25 MHz reference crystal */ |
592 | refclk: oscillator { | |
593 | compatible = "fixed-clock"; | |
594 | #clock-cells = <0>; | |
595 | clock-frequency = <25000000>; | |
596 | }; | |
597 | }; | |
598 | }; |