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ARM: mvebu: a38x: Add more pinctrl functions
[deliverable/linux.git] / arch / arm / boot / dts / armada-38x.dtsi
CommitLineData
0d3d96ab
TP		 1/*
2 * Device Tree Include file for Marvell Armada 38x family of SoCs.
3 *
4 * Copyright (C) 2014 Marvell
5 *
6 * Lior Amsalem <alior@marvell.com>
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9 *
10 * This file is licensed under the terms of the GNU General Public
11 * License version 2. This program is licensed "as is" without any
12 * warranty of any kind, whether express or implied.
13 */
14
15#include "skeleton.dtsi"
f327d43d 16#include <dt-bindings/interrupt-controller/arm-gic.h>
d11548e3 17#include <dt-bindings/interrupt-controller/irq.h>
0d3d96ab
TP		 18
19#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
20
21/ {
22 model = "Marvell Armada 38x family SoC";
8dbdb8e7 23 compatible = "marvell,armada380";
0d3d96ab
TP		 24
25 aliases {
26 gpio0 = &gpio0;
27 gpio1 = &gpio1;
ad6a1b44
MW		 28 ethernet0 = &eth0;
29 ethernet1 = &eth1;
30 ethernet2 = &eth2;
0d3d96ab
TP		 31 };
32
33 soc {
34 compatible = "marvell,armada380-mbus", "marvell,armada370-mbus",
35 "simple-bus";
36 #address-cells = <2>;
37 #size-cells = <1>;
38 controller = <&mbusc>;
39 interrupt-parent = <&gic>;
40 pcie-mem-aperture = <0xe0000000 0x8000000>;
41 pcie-io-aperture = <0xe8000000 0x100000>;
42
43 bootrom {
44 compatible = "marvell,bootrom";
45 reg = <MBUS_ID(0x01, 0x1d) 0 0x200000>;
46 };
47
48 devbus-bootcs {
49 compatible = "marvell,mvebu-devbus";
50 reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
51 ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
52 #address-cells = <1>;
53 #size-cells = <1>;
54 clocks = <&coreclk 0>;
55 status = "disabled";
56 };
57
58 devbus-cs0 {
59 compatible = "marvell,mvebu-devbus";
60 reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
61 ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
62 #address-cells = <1>;
63 #size-cells = <1>;
64 clocks = <&coreclk 0>;
65 status = "disabled";
66 };
67
68 devbus-cs1 {
69 compatible = "marvell,mvebu-devbus";
70 reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
71 ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>;
72 #address-cells = <1>;
73 #size-cells = <1>;
74 clocks = <&coreclk 0>;
75 status = "disabled";
76 };
77
78 devbus-cs2 {
79 compatible = "marvell,mvebu-devbus";
80 reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>;
81 ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>;
82 #address-cells = <1>;
83 #size-cells = <1>;
84 clocks = <&coreclk 0>;
85 status = "disabled";
86 };
87
88 devbus-cs3 {
89 compatible = "marvell,mvebu-devbus";
90 reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>;
91 ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>;
92 #address-cells = <1>;
93 #size-cells = <1>;
94 clocks = <&coreclk 0>;
95 status = "disabled";
96 };
97
98 internal-regs {
99 compatible = "simple-bus";
100 #address-cells = <1>;
101 #size-cells = <1>;
102 ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
103
104 L2: cache-controller@8000 {
105 compatible = "arm,pl310-cache";
106 reg = <0x8000 0x1000>;
107 cache-unified;
108 cache-level = <2>;
109 };
110
964a6156
TP		 111 scu@c000 {
112 compatible = "arm,cortex-a9-scu";
113 reg = <0xc000 0x58>;
114 };
115
0d3d96ab
TP		 116 timer@c600 {
117 compatible = "arm,cortex-a9-twd-timer";
118 reg = <0xc600 0x20>;
d11548e3 119 interrupts = <GIC_PPI 13 (IRQ_TYPE_EDGE_RISING | GIC_CPU_MASK_SIMPLE(2))>;
0d3d96ab
TP		 120 clocks = <&coreclk 2>;
121 };
122
123 gic: interrupt-controller@d000 {
124 compatible = "arm,cortex-a9-gic";
125 #interrupt-cells = <3>;
126 #size-cells = <0>;
127 interrupt-controller;
128 reg = <0xd000 0x1000>,
129 <0xc100 0x100>;
130 };
131
132 spi0: spi@10600 {
133 compatible = "marvell,orion-spi";
134 reg = <0x10600 0x50>;
135 #address-cells = <1>;
136 #size-cells = <0>;
137 cell-index = <0>;
d11548e3 138 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
0d3d96ab
TP		 139 clocks = <&coreclk 0>;
140 status = "disabled";
141 };
142
143 spi1: spi@10680 {
144 compatible = "marvell,orion-spi";
145 reg = <0x10680 0x50>;
146 #address-cells = <1>;
147 #size-cells = <0>;
148 cell-index = <1>;
d11548e3 149 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
0d3d96ab
TP		 150 clocks = <&coreclk 0>;
151 status = "disabled";
152 };
153
154 i2c0: i2c@11000 {
155 compatible = "marvell,mv64xxx-i2c";
156 reg = <0x11000 0x20>;
157 #address-cells = <1>;
158 #size-cells = <0>;
d11548e3 159 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
0d3d96ab
TP		 160 timeout-ms = <1000>;
161 clocks = <&coreclk 0>;
162 status = "disabled";
163 };
164
165 i2c1: i2c@11100 {
166 compatible = "marvell,mv64xxx-i2c";
167 reg = <0x11100 0x20>;
168 #address-cells = <1>;
169 #size-cells = <0>;
d11548e3 170 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
0d3d96ab
TP		 171 timeout-ms = <1000>;
172 clocks = <&coreclk 0>;
173 status = "disabled";
174 };
175
176 serial@12000 {
177 compatible = "snps,dw-apb-uart";
178 reg = <0x12000 0x100>;
179 reg-shift = <2>;
d11548e3 180 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
0d3d96ab 181 reg-io-width = <1>;
64939dc5 182 clocks = <&coreclk 0>;
0d3d96ab
TP		 183 status = "disabled";
184 };
185
186 serial@12100 {
187 compatible = "snps,dw-apb-uart";
188 reg = <0x12100 0x100>;
189 reg-shift = <2>;
d11548e3 190 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
0d3d96ab 191 reg-io-width = <1>;
64939dc5 192 clocks = <&coreclk 0>;
0d3d96ab
TP		 193 status = "disabled";
194 };
195
4a25432b 196 pinctrl@18000 {
0d3d96ab 197 reg = <0x18000 0x20>;
91b4c91f
MR		 198
199 ge0_rgmii_pins: ge-rgmii-pins-0 {
200 marvell,pins = "mpp6", "mpp7", "mpp8",
201 "mpp9", "mpp10", "mpp11",
202 "mpp12", "mpp13", "mpp14",
203 "mpp15", "mpp16", "mpp17";
204 marvell,function = "ge0";
205 };
206
34598503
GC		 207 ge1_rgmii_pins: ge-rgmii-pins-1 {
208 marvell,pins = "mpp21", "mpp27", "mpp28",
209 "mpp29", "mpp30", "mpp31",
210 "mpp32", "mpp37", "mpp38",
211 "mpp39", "mpp40", "mpp41";
212 marvell,function = "ge1";
213 };
214
91b4c91f
MR		 215 i2c0_pins: i2c-pins-0 {
216 marvell,pins = "mpp2", "mpp3";
217 marvell,function = "i2c0";
218 };
219
220 mdio_pins: mdio-pins {
221 marvell,pins = "mpp4", "mpp5";
222 marvell,function = "ge";
223 };
224
225 ref_clk0_pins: ref-clk-pins-0 {
226 marvell,pins = "mpp45";
227 marvell,function = "ref";
228 };
229
34598503
GC		 230 ref_clk1_pins: ref-clk-pins-1 {
231 marvell,pins = "mpp46";
232 marvell,function = "ref";
233 };
234
235 spi0_pins: spi-pins-0 {
236 marvell,pins = "mpp22", "mpp23", "mpp24",
237 "mpp25";
238 marvell,function = "spi0";
239 };
240
91b4c91f
MR		 241 spi1_pins: spi-pins-1 {
242 marvell,pins = "mpp56", "mpp57", "mpp58",
243 "mpp59";
244 marvell,function = "spi1";
245 };
246
247 uart0_pins: uart-pins-0 {
248 marvell,pins = "mpp0", "mpp1";
249 marvell,function = "ua0";
250 };
251
252 uart1_pins: uart-pins-1 {
253 marvell,pins = "mpp19", "mpp20";
254 marvell,function = "ua1";
255 };
34598503
GC		 256
257 sdhci_pins: sdhci-pins {
258 marvell,pins = "mpp48", "mpp49", "mpp50",
259 "mpp52", "mpp53", "mpp54",
260 "mpp55", "mpp57", "mpp58",
261 "mpp59";
262 marvell,function = "sd0";
263 };
264
265 sata0_pins: sata-pins-0 {
266 marvell,pins = "mpp20";
267 marvell,function = "sata0";
268 };
269
270 sata1_pins: sata-pins-1 {
271 marvell,pins = "mpp19";
272 marvell,function = "sata1";
273 };
274
275 sata2_pins: sata-pins-2 {
276 marvell,pins = "mpp47";
277 marvell,function = "sata2";
278 };
279
280 sata3_pins: sata-pins-3 {
281 marvell,pins = "mpp44";
282 marvell,function = "sata3";
283 };
0d3d96ab
TP		 284 };
285
286 gpio0: gpio@18100 {
287 compatible = "marvell,orion-gpio";
288 reg = <0x18100 0x40>;
289 ngpios = <32>;
290 gpio-controller;
291 #gpio-cells = <2>;
292 interrupt-controller;
293 #interrupt-cells = <2>;
d11548e3
TP		 294 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
295 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
296 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
297 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
0d3d96ab
TP		 298 };
299
300 gpio1: gpio@18140 {
301 compatible = "marvell,orion-gpio";
302 reg = <0x18140 0x40>;
303 ngpios = <28>;
304 gpio-controller;
305 #gpio-cells = <2>;
306 interrupt-controller;
307 #interrupt-cells = <2>;
d11548e3
TP		 308 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
309 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
310 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
311 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
0d3d96ab
TP		 312 };
313
314 system-controller@18200 {
315 compatible = "marvell,armada-380-system-controller",
316 "marvell,armada-370-xp-system-controller";
317 reg = <0x18200 0x100>;
318 };
319
320 gateclk: clock-gating-control@18220 {
321 compatible = "marvell,armada-380-gating-clock";
322 reg = <0x18220 0x4>;
323 clocks = <&coreclk 0>;
324 #clock-cells = <1>;
325 };
326
327 coreclk: mvebu-sar@18600 {
328 compatible = "marvell,armada-380-core-clock";
329 reg = <0x18600 0x04>;
330 #clock-cells = <1>;
331 };
332
333 mbusc: mbus-controller@20000 {
334 compatible = "marvell,mbus-controller";
335 reg = <0x20000 0x100>, <0x20180 0x20>;
336 };
337
338 mpic: interrupt-controller@20000 {
339 compatible = "marvell,mpic";
340 reg = <0x20a00 0x2d0>, <0x21070 0x58>;
341 #interrupt-cells = <1>;
342 #size-cells = <1>;
343 interrupt-controller;
344 msi-controller;
d11548e3 345 interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
0d3d96ab
TP		 346 };
347
348 timer@20300 {
349 compatible = "marvell,armada-380-timer",
350 "marvell,armada-xp-timer";
351 reg = <0x20300 0x30>, <0x21040 0x30>;
d11548e3
TP		 352 interrupts-extended = <&gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
353 <&gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
354 <&gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
355 <&gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
0d3d96ab
TP		 356 <&mpic 5>,
357 <&mpic 6>;
358 clocks = <&coreclk 2>, <&refclk>;
359 clock-names = "nbclk", "fixed";
360 };
361
153a964a
EG		 362 watchdog@20300 {
363 compatible = "marvell,armada-380-wdt";
364 reg = <0x20300 0x34>, <0x20704 0x4>, <0x18260 0x4>;
365 clocks = <&coreclk 2>, <&refclk>;
366 clock-names = "nbclk", "fixed";
367 };
368
19b06d7f
TP		 369 cpurst@20800 {
370 compatible = "marvell,armada-370-cpu-reset";
371 reg = <0x20800 0x10>;
372 };
373
d7f3ec2b
GC		 374 mpcore-soc-ctrl@20d20 {
375 compatible = "marvell,armada-380-mpcore-soc-ctrl";
376 reg = <0x20d20 0x6c>;
377 };
378
964a6156
TP		 379 coherency-fabric@21010 {
380 compatible = "marvell,armada-380-coherency-fabric";
381 reg = <0x21010 0x1c>;
382 };
383
19b06d7f
TP		 384 pmsu@22000 {
385 compatible = "marvell,armada-380-pmsu";
386 reg = <0x22000 0x1000>;
387 };
388
0d3d96ab
TP		 389 eth1: ethernet@30000 {
390 compatible = "marvell,armada-370-neta";
391 reg = <0x30000 0x4000>;
392 interrupts-extended = <&mpic 10>;
393 clocks = <&gateclk 3>;
394 status = "disabled";
395 };
396
397 eth2: ethernet@34000 {
398 compatible = "marvell,armada-370-neta";
399 reg = <0x34000 0x4000>;
400 interrupts-extended = <&mpic 12>;
401 clocks = <&gateclk 2>;
402 status = "disabled";
403 };
404
9e81775a
GC		 405 usb@50000 {
406 compatible = "marvell,orion-ehci";
407 reg = <0x58000 0x500>;
408 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
409 clocks = <&gateclk 18>;
410 status = "disabled";
411 };
412
0d3d96ab
TP		 413 xor@60800 {
414 compatible = "marvell,orion-xor";
415 reg = <0x60800 0x100
416 0x60a00 0x100>;
417 clocks = <&gateclk 22>;
418 status = "okay";
419
420 xor00 {
d11548e3 421 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
0d3d96ab
TP		 422 dmacap,memcpy;
423 dmacap,xor;
424 };
425 xor01 {
d11548e3 426 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
0d3d96ab
TP		 427 dmacap,memcpy;
428 dmacap,xor;
429 dmacap,memset;
430 };
431 };
432
433 xor@60900 {
434 compatible = "marvell,orion-xor";
435 reg = <0x60900 0x100
436 0x60b00 0x100>;
437 clocks = <&gateclk 28>;
438 status = "okay";
439
440 xor10 {
d11548e3 441 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
0d3d96ab
TP		 442 dmacap,memcpy;
443 dmacap,xor;
444 };
445 xor11 {
d11548e3 446 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
0d3d96ab
TP		 447 dmacap,memcpy;
448 dmacap,xor;
449 dmacap,memset;
450 };
451 };
452
453 eth0: ethernet@70000 {
454 compatible = "marvell,armada-370-neta";
455 reg = <0x70000 0x4000>;
456 interrupts-extended = <&mpic 8>;
457 clocks = <&gateclk 4>;
458 status = "disabled";
459 };
460
4a25432b 461 mdio@72004 {
0d3d96ab
TP		 462 #address-cells = <1>;
463 #size-cells = <0>;
464 compatible = "marvell,orion-mdio";
465 reg = <0x72004 0x4>;
33faf20b 466 clocks = <&gateclk 4>;
0d3d96ab 467 };
d6bd4b4c 468
d175b6e4
TP		 469 sata@a8000 {
470 compatible = "marvell,armada-380-ahci";
471 reg = <0xa8000 0x2000>;
472 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
473 clocks = <&gateclk 15>;
474 status = "disabled";
475 };
476
477 sata@e0000 {
478 compatible = "marvell,armada-380-ahci";
479 reg = <0xe0000 0x2000>;
480 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
481 clocks = <&gateclk 30>;
482 status = "disabled";
483 };
484
d6bd4b4c
EG		 485 coredivclk: clock@e4250 {
486 compatible = "marvell,armada-380-corediv-clock";
487 reg = <0xe4250 0xc>;
488 #clock-cells = <1>;
489 clocks = <&mainpll>;
490 clock-output-names = "nand";
491 };
93b5577e 492
c630829a
EG		 493 thermal@e8078 {
494 compatible = "marvell,armada380-thermal";
495 reg = <0xe4078 0x4>, <0xe4074 0x4>;
496 status = "okay";
497 };
498
93b5577e
EG		 499 flash@d0000 {
500 compatible = "marvell,armada370-nand";
501 reg = <0xd0000 0x54>;
502 #address-cells = <1>;
503 #size-cells = <1>;
504 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
505 clocks = <&coredivclk 0>;
506 status = "disabled";
507 };
6eccc52b
TP		 508
509 sdhci@d8000 {
510 compatible = "marvell,armada-380-sdhci";
511 reg = <0xd8000 0x1000>, <0xdc000 0x100>;
512 interrupts = <0 25 0x4>;
513 clocks = <&gateclk 17>;
514 mrvl,clk-delay-cycles = <0x1F>;
515 status = "disabled";
516 };
87e2fc37
GC		 517
518 usb3@f0000 {
519 compatible = "marvell,armada-380-xhci";
520 reg = <0xf0000 0x4000>,<0xf4000 0x4000>;
521 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
522 clocks = <&gateclk 9>;
523 status = "disabled";
524 };
525
526 usb3@f8000 {
527 compatible = "marvell,armada-380-xhci";
528 reg = <0xf8000 0x4000>,<0xfc000 0x4000>;
529 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
530 clocks = <&gateclk 10>;
531 status = "disabled";
532 };
0d3d96ab
TP		 533 };
534 };
535
536 clocks {
5bc94c99
EG		 537 /* 2 GHz fixed main PLL */
538 mainpll: mainpll {
539 compatible = "fixed-clock";
540 #clock-cells = <0>;
541 clock-frequency = <2000000000>;
542 };
543
0d3d96ab
TP		 544 /* 25 MHz reference crystal */
545 refclk: oscillator {
546 compatible = "fixed-clock";
547 #clock-cells = <0>;
548 clock-frequency = <25000000>;
549 };
550 };
551};
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