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ARM: mvebu: armada-388-rd: Relicense the device tree under GPLv2+/X11
[deliverable/linux.git] / arch / arm / boot / dts / armada-38x.dtsi
CommitLineData
0d3d96ab
TP		 1/*
2 * Device Tree Include file for Marvell Armada 38x family of SoCs.
3 *
4 * Copyright (C) 2014 Marvell
5 *
6 * Lior Amsalem <alior@marvell.com>
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9 *
10 * This file is licensed under the terms of the GNU General Public
11 * License version 2. This program is licensed "as is" without any
12 * warranty of any kind, whether express or implied.
13 */
14
15#include "skeleton.dtsi"
f327d43d 16#include <dt-bindings/interrupt-controller/arm-gic.h>
d11548e3 17#include <dt-bindings/interrupt-controller/irq.h>
0d3d96ab
TP		 18
19#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
20
21/ {
22 model = "Marvell Armada 38x family SoC";
8dbdb8e7 23 compatible = "marvell,armada380";
0d3d96ab
TP		 24
25 aliases {
26 gpio0 = &gpio0;
27 gpio1 = &gpio1;
ad6a1b44
MW		 28 ethernet0 = &eth0;
29 ethernet1 = &eth1;
30 ethernet2 = &eth2;
0d3d96ab
TP		 31 };
32
33 soc {
a9e274c4 34 compatible = "marvell,armada380-mbus", "simple-bus";
0d3d96ab
TP		 35 #address-cells = <2>;
36 #size-cells = <1>;
37 controller = <&mbusc>;
38 interrupt-parent = <&gic>;
39 pcie-mem-aperture = <0xe0000000 0x8000000>;
40 pcie-io-aperture = <0xe8000000 0x100000>;
41
42 bootrom {
43 compatible = "marvell,bootrom";
44 reg = <MBUS_ID(0x01, 0x1d) 0 0x200000>;
45 };
46
47 devbus-bootcs {
48 compatible = "marvell,mvebu-devbus";
49 reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
50 ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
51 #address-cells = <1>;
52 #size-cells = <1>;
53 clocks = <&coreclk 0>;
54 status = "disabled";
55 };
56
57 devbus-cs0 {
58 compatible = "marvell,mvebu-devbus";
59 reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
60 ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
61 #address-cells = <1>;
62 #size-cells = <1>;
63 clocks = <&coreclk 0>;
64 status = "disabled";
65 };
66
67 devbus-cs1 {
68 compatible = "marvell,mvebu-devbus";
69 reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
70 ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>;
71 #address-cells = <1>;
72 #size-cells = <1>;
73 clocks = <&coreclk 0>;
74 status = "disabled";
75 };
76
77 devbus-cs2 {
78 compatible = "marvell,mvebu-devbus";
79 reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>;
80 ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>;
81 #address-cells = <1>;
82 #size-cells = <1>;
83 clocks = <&coreclk 0>;
84 status = "disabled";
85 };
86
87 devbus-cs3 {
88 compatible = "marvell,mvebu-devbus";
89 reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>;
90 ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>;
91 #address-cells = <1>;
92 #size-cells = <1>;
93 clocks = <&coreclk 0>;
94 status = "disabled";
95 };
96
97 internal-regs {
98 compatible = "simple-bus";
99 #address-cells = <1>;
100 #size-cells = <1>;
101 ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
102
103 L2: cache-controller@8000 {
104 compatible = "arm,pl310-cache";
105 reg = <0x8000 0x1000>;
106 cache-unified;
107 cache-level = <2>;
108 };
109
964a6156
TP		 110 scu@c000 {
111 compatible = "arm,cortex-a9-scu";
112 reg = <0xc000 0x58>;
113 };
114
0d3d96ab
TP		 115 timer@c600 {
116 compatible = "arm,cortex-a9-twd-timer";
117 reg = <0xc600 0x20>;
d11548e3 118 interrupts = <GIC_PPI 13 (IRQ_TYPE_EDGE_RISING | GIC_CPU_MASK_SIMPLE(2))>;
0d3d96ab
TP		 119 clocks = <&coreclk 2>;
120 };
121
122 gic: interrupt-controller@d000 {
123 compatible = "arm,cortex-a9-gic";
124 #interrupt-cells = <3>;
125 #size-cells = <0>;
126 interrupt-controller;
127 reg = <0xd000 0x1000>,
128 <0xc100 0x100>;
129 };
130
131 spi0: spi@10600 {
132 compatible = "marvell,orion-spi";
133 reg = <0x10600 0x50>;
134 #address-cells = <1>;
135 #size-cells = <0>;
136 cell-index = <0>;
d11548e3 137 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
0d3d96ab
TP		 138 clocks = <&coreclk 0>;
139 status = "disabled";
140 };
141
142 spi1: spi@10680 {
143 compatible = "marvell,orion-spi";
144 reg = <0x10680 0x50>;
145 #address-cells = <1>;
146 #size-cells = <0>;
147 cell-index = <1>;
d11548e3 148 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
0d3d96ab
TP		 149 clocks = <&coreclk 0>;
150 status = "disabled";
151 };
152
153 i2c0: i2c@11000 {
154 compatible = "marvell,mv64xxx-i2c";
155 reg = <0x11000 0x20>;
156 #address-cells = <1>;
157 #size-cells = <0>;
d11548e3 158 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
0d3d96ab
TP		 159 timeout-ms = <1000>;
160 clocks = <&coreclk 0>;
161 status = "disabled";
162 };
163
164 i2c1: i2c@11100 {
165 compatible = "marvell,mv64xxx-i2c";
166 reg = <0x11100 0x20>;
167 #address-cells = <1>;
168 #size-cells = <0>;
d11548e3 169 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
0d3d96ab
TP		 170 timeout-ms = <1000>;
171 clocks = <&coreclk 0>;
172 status = "disabled";
173 };
174
10c5c472 175 uart0: serial@12000 {
0d3d96ab
TP		 176 compatible = "snps,dw-apb-uart";
177 reg = <0x12000 0x100>;
178 reg-shift = <2>;
d11548e3 179 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
0d3d96ab 180 reg-io-width = <1>;
64939dc5 181 clocks = <&coreclk 0>;
0d3d96ab
TP		 182 status = "disabled";
183 };
184
185 serial@12100 {
186 compatible = "snps,dw-apb-uart";
187 reg = <0x12100 0x100>;
188 reg-shift = <2>;
d11548e3 189 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
0d3d96ab 190 reg-io-width = <1>;
64939dc5 191 clocks = <&coreclk 0>;
0d3d96ab
TP		 192 status = "disabled";
193 };
194
10c5c472 195 pinctrl: pinctrl@18000 {
0d3d96ab 196 reg = <0x18000 0x20>;
91b4c91f
MR		 197
198 ge0_rgmii_pins: ge-rgmii-pins-0 {
199 marvell,pins = "mpp6", "mpp7", "mpp8",
200 "mpp9", "mpp10", "mpp11",
201 "mpp12", "mpp13", "mpp14",
202 "mpp15", "mpp16", "mpp17";
203 marvell,function = "ge0";
204 };
205
34598503
GC		 206 ge1_rgmii_pins: ge-rgmii-pins-1 {
207 marvell,pins = "mpp21", "mpp27", "mpp28",
208 "mpp29", "mpp30", "mpp31",
209 "mpp32", "mpp37", "mpp38",
210 "mpp39", "mpp40", "mpp41";
211 marvell,function = "ge1";
212 };
213
91b4c91f
MR		 214 i2c0_pins: i2c-pins-0 {
215 marvell,pins = "mpp2", "mpp3";
216 marvell,function = "i2c0";
217 };
218
219 mdio_pins: mdio-pins {
220 marvell,pins = "mpp4", "mpp5";
221 marvell,function = "ge";
222 };
223
224 ref_clk0_pins: ref-clk-pins-0 {
225 marvell,pins = "mpp45";
226 marvell,function = "ref";
227 };
228
34598503
GC		 229 ref_clk1_pins: ref-clk-pins-1 {
230 marvell,pins = "mpp46";
231 marvell,function = "ref";
232 };
233
234 spi0_pins: spi-pins-0 {
235 marvell,pins = "mpp22", "mpp23", "mpp24",
236 "mpp25";
237 marvell,function = "spi0";
238 };
239
91b4c91f
MR		 240 spi1_pins: spi-pins-1 {
241 marvell,pins = "mpp56", "mpp57", "mpp58",
242 "mpp59";
243 marvell,function = "spi1";
244 };
245
246 uart0_pins: uart-pins-0 {
247 marvell,pins = "mpp0", "mpp1";
248 marvell,function = "ua0";
249 };
250
251 uart1_pins: uart-pins-1 {
252 marvell,pins = "mpp19", "mpp20";
253 marvell,function = "ua1";
254 };
34598503
GC		 255
256 sdhci_pins: sdhci-pins {
257 marvell,pins = "mpp48", "mpp49", "mpp50",
258 "mpp52", "mpp53", "mpp54",
259 "mpp55", "mpp57", "mpp58",
260 "mpp59";
261 marvell,function = "sd0";
262 };
263
264 sata0_pins: sata-pins-0 {
265 marvell,pins = "mpp20";
266 marvell,function = "sata0";
267 };
268
269 sata1_pins: sata-pins-1 {
270 marvell,pins = "mpp19";
271 marvell,function = "sata1";
272 };
273
274 sata2_pins: sata-pins-2 {
275 marvell,pins = "mpp47";
276 marvell,function = "sata2";
277 };
278
279 sata3_pins: sata-pins-3 {
280 marvell,pins = "mpp44";
281 marvell,function = "sata3";
282 };
0d3d96ab
TP		 283 };
284
285 gpio0: gpio@18100 {
286 compatible = "marvell,orion-gpio";
287 reg = <0x18100 0x40>;
288 ngpios = <32>;
289 gpio-controller;
290 #gpio-cells = <2>;
291 interrupt-controller;
292 #interrupt-cells = <2>;
d11548e3
TP		 293 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
294 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
295 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
296 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
0d3d96ab
TP		 297 };
298
299 gpio1: gpio@18140 {
300 compatible = "marvell,orion-gpio";
301 reg = <0x18140 0x40>;
302 ngpios = <28>;
303 gpio-controller;
304 #gpio-cells = <2>;
305 interrupt-controller;
306 #interrupt-cells = <2>;
d11548e3
TP		 307 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
308 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
309 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
310 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
0d3d96ab
TP		 311 };
312
313 system-controller@18200 {
314 compatible = "marvell,armada-380-system-controller",
315 "marvell,armada-370-xp-system-controller";
316 reg = <0x18200 0x100>;
317 };
318
319 gateclk: clock-gating-control@18220 {
320 compatible = "marvell,armada-380-gating-clock";
321 reg = <0x18220 0x4>;
322 clocks = <&coreclk 0>;
323 #clock-cells = <1>;
324 };
325
326 coreclk: mvebu-sar@18600 {
327 compatible = "marvell,armada-380-core-clock";
328 reg = <0x18600 0x04>;
329 #clock-cells = <1>;
330 };
331
332 mbusc: mbus-controller@20000 {
333 compatible = "marvell,mbus-controller";
334 reg = <0x20000 0x100>, <0x20180 0x20>;
335 };
336
337 mpic: interrupt-controller@20000 {
338 compatible = "marvell,mpic";
339 reg = <0x20a00 0x2d0>, <0x21070 0x58>;
340 #interrupt-cells = <1>;
341 #size-cells = <1>;
342 interrupt-controller;
343 msi-controller;
d11548e3 344 interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
0d3d96ab
TP		 345 };
346
347 timer@20300 {
348 compatible = "marvell,armada-380-timer",
349 "marvell,armada-xp-timer";
350 reg = <0x20300 0x30>, <0x21040 0x30>;
d11548e3
TP		 351 interrupts-extended = <&gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
352 <&gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
353 <&gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
354 <&gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
0d3d96ab
TP		 355 <&mpic 5>,
356 <&mpic 6>;
357 clocks = <&coreclk 2>, <&refclk>;
358 clock-names = "nbclk", "fixed";
359 };
360
153a964a
EG		 361 watchdog@20300 {
362 compatible = "marvell,armada-380-wdt";
363 reg = <0x20300 0x34>, <0x20704 0x4>, <0x18260 0x4>;
364 clocks = <&coreclk 2>, <&refclk>;
365 clock-names = "nbclk", "fixed";
366 };
367
19b06d7f
TP		 368 cpurst@20800 {
369 compatible = "marvell,armada-370-cpu-reset";
370 reg = <0x20800 0x10>;
371 };
372
d7f3ec2b
GC		 373 mpcore-soc-ctrl@20d20 {
374 compatible = "marvell,armada-380-mpcore-soc-ctrl";
375 reg = <0x20d20 0x6c>;
376 };
377
964a6156
TP		 378 coherency-fabric@21010 {
379 compatible = "marvell,armada-380-coherency-fabric";
380 reg = <0x21010 0x1c>;
381 };
382
19b06d7f
TP		 383 pmsu@22000 {
384 compatible = "marvell,armada-380-pmsu";
385 reg = <0x22000 0x1000>;
386 };
387
0d3d96ab
TP		 388 eth1: ethernet@30000 {
389 compatible = "marvell,armada-370-neta";
390 reg = <0x30000 0x4000>;
391 interrupts-extended = <&mpic 10>;
392 clocks = <&gateclk 3>;
393 status = "disabled";
394 };
395
396 eth2: ethernet@34000 {
397 compatible = "marvell,armada-370-neta";
398 reg = <0x34000 0x4000>;
399 interrupts-extended = <&mpic 12>;
400 clocks = <&gateclk 2>;
401 status = "disabled";
402 };
403
9e81775a
GC		 404 usb@50000 {
405 compatible = "marvell,orion-ehci";
406 reg = <0x58000 0x500>;
407 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
408 clocks = <&gateclk 18>;
409 status = "disabled";
410 };
411
0d3d96ab
TP		 412 xor@60800 {
413 compatible = "marvell,orion-xor";
414 reg = <0x60800 0x100
415 0x60a00 0x100>;
416 clocks = <&gateclk 22>;
417 status = "okay";
418
419 xor00 {
d11548e3 420 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
0d3d96ab
TP		 421 dmacap,memcpy;
422 dmacap,xor;
423 };
424 xor01 {
d11548e3 425 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
0d3d96ab
TP		 426 dmacap,memcpy;
427 dmacap,xor;
428 dmacap,memset;
429 };
430 };
431
432 xor@60900 {
433 compatible = "marvell,orion-xor";
434 reg = <0x60900 0x100
435 0x60b00 0x100>;
436 clocks = <&gateclk 28>;
437 status = "okay";
438
439 xor10 {
d11548e3 440 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
0d3d96ab
TP		 441 dmacap,memcpy;
442 dmacap,xor;
443 };
444 xor11 {
d11548e3 445 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
0d3d96ab
TP		 446 dmacap,memcpy;
447 dmacap,xor;
448 dmacap,memset;
449 };
450 };
451
452 eth0: ethernet@70000 {
453 compatible = "marvell,armada-370-neta";
454 reg = <0x70000 0x4000>;
455 interrupts-extended = <&mpic 8>;
456 clocks = <&gateclk 4>;
457 status = "disabled";
458 };
459
4a25432b 460 mdio@72004 {
0d3d96ab
TP		 461 #address-cells = <1>;
462 #size-cells = <0>;
463 compatible = "marvell,orion-mdio";
464 reg = <0x72004 0x4>;
33faf20b 465 clocks = <&gateclk 4>;
0d3d96ab 466 };
d6bd4b4c 467
d175b6e4
TP		 468 sata@a8000 {
469 compatible = "marvell,armada-380-ahci";
470 reg = <0xa8000 0x2000>;
471 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
472 clocks = <&gateclk 15>;
473 status = "disabled";
474 };
475
476 sata@e0000 {
477 compatible = "marvell,armada-380-ahci";
478 reg = <0xe0000 0x2000>;
479 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
480 clocks = <&gateclk 30>;
481 status = "disabled";
482 };
483
d6bd4b4c
EG		 484 coredivclk: clock@e4250 {
485 compatible = "marvell,armada-380-corediv-clock";
486 reg = <0xe4250 0xc>;
487 #clock-cells = <1>;
488 clocks = <&mainpll>;
489 clock-output-names = "nand";
490 };
93b5577e 491
c630829a
EG		 492 thermal@e8078 {
493 compatible = "marvell,armada380-thermal";
494 reg = <0xe4078 0x4>, <0xe4074 0x4>;
495 status = "okay";
496 };
497
93b5577e
EG		 498 flash@d0000 {
499 compatible = "marvell,armada370-nand";
500 reg = <0xd0000 0x54>;
501 #address-cells = <1>;
502 #size-cells = <1>;
503 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
504 clocks = <&coredivclk 0>;
505 status = "disabled";
506 };
6eccc52b
TP		 507
508 sdhci@d8000 {
509 compatible = "marvell,armada-380-sdhci";
510 reg = <0xd8000 0x1000>, <0xdc000 0x100>;
511 interrupts = <0 25 0x4>;
512 clocks = <&gateclk 17>;
513 mrvl,clk-delay-cycles = <0x1F>;
514 status = "disabled";
515 };
87e2fc37
GC		 516
517 usb3@f0000 {
518 compatible = "marvell,armada-380-xhci";
519 reg = <0xf0000 0x4000>,<0xf4000 0x4000>;
520 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
521 clocks = <&gateclk 9>;
522 status = "disabled";
523 };
524
525 usb3@f8000 {
526 compatible = "marvell,armada-380-xhci";
527 reg = <0xf8000 0x4000>,<0xfc000 0x4000>;
528 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
529 clocks = <&gateclk 10>;
530 status = "disabled";
531 };
0d3d96ab
TP		 532 };
533 };
534
535 clocks {
5bc94c99
EG		 536 /* 2 GHz fixed main PLL */
537 mainpll: mainpll {
538 compatible = "fixed-clock";
539 #clock-cells = <0>;
540 clock-frequency = <2000000000>;
541 };
542
0d3d96ab
TP		 543 /* 25 MHz reference crystal */
544 refclk: oscillator {
545 compatible = "fixed-clock";
546 #clock-cells = <0>;
547 clock-frequency = <25000000>;
548 };
549 };
550};
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