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538da83d TP |
1 | /* |
2 | * Device Tree Include file for Marvell Armada 39x family of SoCs. | |
3 | * | |
4 | * Copyright (C) 2015 Marvell | |
5 | * | |
6 | * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> | |
7 | * | |
8 | * This file is dual-licensed: you can use it either under the terms | |
9 | * of the GPL or the X11 license, at your option. Note that this dual | |
10 | * licensing only applies to this file, and not this project as a | |
11 | * whole. | |
12 | * | |
13 | * a) This file is free software; you can redistribute it and/or | |
14 | * modify it under the terms of the GNU General Public License as | |
15 | * published by the Free Software Foundation; either version 2 of the | |
16 | * License, or (at your option) any later version. | |
17 | * | |
18 | * This file is distributed in the hope that it will be useful | |
19 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
20 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
21 | * GNU General Public License for more details. | |
22 | * | |
23 | * Or, alternatively | |
24 | * | |
25 | * b) Permission is hereby granted, free of charge, to any person | |
26 | * obtaining a copy of this software and associated documentation | |
27 | * files (the "Software"), to deal in the Software without | |
28 | * restriction, including without limitation the rights to use | |
29 | * copy, modify, merge, publish, distribute, sublicense, and/or | |
30 | * sell copies of the Software, and to permit persons to whom the | |
31 | * Software is furnished to do so, subject to the following | |
32 | * conditions: | |
33 | * | |
34 | * The above copyright notice and this permission notice shall be | |
35 | * included in all copies or substantial portions of the Software. | |
36 | * | |
37 | * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND | |
38 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES | |
39 | * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
40 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT | |
41 | * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY | |
42 | * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
43 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
44 | * OTHER DEALINGS IN THE SOFTWARE. | |
45 | */ | |
46 | ||
47 | #include "skeleton.dtsi" | |
48 | #include <dt-bindings/interrupt-controller/arm-gic.h> | |
49 | #include <dt-bindings/interrupt-controller/irq.h> | |
50 | ||
51 | #define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16)) | |
52 | ||
53 | / { | |
54 | model = "Marvell Armada 39x family SoC"; | |
55 | compatible = "marvell,armada390"; | |
56 | ||
57 | aliases { | |
58 | serial0 = &uart0; | |
59 | serial1 = &uart1; | |
60 | serial2 = &uart2; | |
61 | serial3 = &uart3; | |
62 | }; | |
63 | ||
64 | cpus { | |
65 | #address-cells = <1>; | |
66 | #size-cells = <0>; | |
67 | enable-method = "marvell,armada-390-smp"; | |
68 | ||
69 | cpu@0 { | |
70 | device_type = "cpu"; | |
71 | compatible = "arm,cortex-a9"; | |
72 | reg = <0>; | |
73 | }; | |
74 | cpu@1 { | |
75 | device_type = "cpu"; | |
76 | compatible = "arm,cortex-a9"; | |
77 | reg = <1>; | |
78 | }; | |
79 | }; | |
80 | ||
81 | soc { | |
82 | compatible = "marvell,armada390-mbus", "marvell,armadaxp-mbus", | |
83 | "simple-bus"; | |
84 | #address-cells = <2>; | |
85 | #size-cells = <1>; | |
86 | controller = <&mbusc>; | |
87 | interrupt-parent = <&gic>; | |
88 | pcie-mem-aperture = <0xe0000000 0x8000000>; | |
89 | pcie-io-aperture = <0xe8000000 0x100000>; | |
90 | ||
91 | bootrom { | |
92 | compatible = "marvell,bootrom"; | |
93 | reg = <MBUS_ID(0x01, 0x1d) 0 0x200000>; | |
94 | }; | |
95 | ||
96 | internal-regs { | |
97 | compatible = "simple-bus"; | |
98 | #address-cells = <1>; | |
99 | #size-cells = <1>; | |
100 | ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>; | |
101 | ||
102 | L2: cache-controller@8000 { | |
103 | compatible = "arm,pl310-cache"; | |
104 | reg = <0x8000 0x1000>; | |
105 | cache-unified; | |
106 | cache-level = <2>; | |
c8f5a878 TP |
107 | arm,double-linefill-incr = <1>; |
108 | arm,double-linefill-wrap = <0>; | |
109 | arm,double-linefill = <1>; | |
110 | prefetch-data = <1>; | |
538da83d TP |
111 | }; |
112 | ||
113 | scu@c000 { | |
114 | compatible = "arm,cortex-a9-scu"; | |
115 | reg = <0xc000 0x100>; | |
116 | }; | |
117 | ||
118 | timer@c600 { | |
119 | compatible = "arm,cortex-a9-twd-timer"; | |
120 | reg = <0xc600 0x20>; | |
121 | interrupts = <GIC_PPI 13 (IRQ_TYPE_EDGE_RISING | GIC_CPU_MASK_SIMPLE(2))>; | |
122 | clocks = <&coreclk 2>; | |
123 | }; | |
124 | ||
125 | gic: interrupt-controller@d000 { | |
126 | compatible = "arm,cortex-a9-gic"; | |
127 | #interrupt-cells = <3>; | |
128 | #size-cells = <0>; | |
129 | interrupt-controller; | |
130 | reg = <0xd000 0x1000>, | |
131 | <0xc100 0x100>; | |
132 | }; | |
133 | ||
134 | spi0: spi@10600 { | |
2d295928 GC |
135 | compatible = "marvell,armada-390-spi", |
136 | "marvell,orion-spi"; | |
538da83d TP |
137 | reg = <0x10600 0x50>; |
138 | #address-cells = <1>; | |
139 | #size-cells = <0>; | |
140 | cell-index = <0>; | |
141 | interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; | |
142 | clocks = <&coreclk 0>; | |
143 | status = "disabled"; | |
144 | }; | |
145 | ||
146 | spi1: spi@10680 { | |
2d295928 GC |
147 | compatible = "marvell,armada-390-spi", |
148 | "marvell,orion-spi"; | |
538da83d TP |
149 | reg = <0x10680 0x50>; |
150 | #address-cells = <1>; | |
151 | #size-cells = <0>; | |
152 | cell-index = <1>; | |
153 | interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; | |
154 | clocks = <&coreclk 0>; | |
155 | status = "disabled"; | |
156 | }; | |
157 | ||
158 | i2c0: i2c@11000 { | |
159 | compatible = "marvell,mv64xxx-i2c"; | |
160 | reg = <0x11000 0x20>; | |
161 | #address-cells = <1>; | |
162 | #size-cells = <0>; | |
163 | interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; | |
164 | timeout-ms = <1000>; | |
165 | clocks = <&coreclk 0>; | |
166 | status = "disabled"; | |
167 | }; | |
168 | ||
169 | i2c1: i2c@11100 { | |
170 | compatible = "marvell,mv64xxx-i2c"; | |
171 | reg = <0x11100 0x20>; | |
172 | #address-cells = <1>; | |
173 | #size-cells = <0>; | |
174 | interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; | |
175 | timeout-ms = <1000>; | |
176 | clocks = <&coreclk 0>; | |
177 | status = "disabled"; | |
178 | }; | |
179 | ||
180 | i2c2: i2c@11200 { | |
181 | compatible = "marvell,mv64xxx-i2c"; | |
182 | reg = <0x11200 0x20>; | |
183 | #address-cells = <1>; | |
184 | #size-cells = <0>; | |
185 | interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; | |
186 | timeout-ms = <1000>; | |
187 | clocks = <&coreclk 0>; | |
188 | status = "disabled"; | |
189 | }; | |
190 | ||
191 | i2c3: i2c@11300 { | |
192 | compatible = "marvell,mv64xxx-i2c"; | |
193 | reg = <0x11300 0x20>; | |
194 | #address-cells = <1>; | |
195 | #size-cells = <0>; | |
196 | interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; | |
197 | timeout-ms = <1000>; | |
198 | clocks = <&coreclk 0>; | |
199 | status = "disabled"; | |
200 | }; | |
201 | ||
202 | uart0: serial@12000 { | |
203 | compatible = "snps,dw-apb-uart"; | |
204 | reg = <0x12000 0x100>; | |
205 | reg-shift = <2>; | |
206 | interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; | |
207 | reg-io-width = <1>; | |
208 | clocks = <&coreclk 0>; | |
209 | status = "disabled"; | |
210 | }; | |
211 | ||
212 | uart1: serial@12100 { | |
213 | compatible = "snps,dw-apb-uart"; | |
214 | reg = <0x12100 0x100>; | |
215 | reg-shift = <2>; | |
216 | interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; | |
217 | reg-io-width = <1>; | |
218 | clocks = <&coreclk 0>; | |
219 | status = "disabled"; | |
220 | }; | |
221 | ||
222 | uart2: serial@12200 { | |
223 | compatible = "snps,dw-apb-uart"; | |
224 | reg = <0x12200 0x100>; | |
225 | reg-shift = <2>; | |
226 | interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; | |
227 | reg-io-width = <1>; | |
228 | clocks = <&coreclk 0>; | |
229 | status = "disabled"; | |
230 | }; | |
231 | ||
232 | uart3: serial@12300 { | |
233 | compatible = "snps,dw-apb-uart"; | |
234 | reg = <0x12300 0x100>; | |
235 | reg-shift = <2>; | |
236 | interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; | |
237 | reg-io-width = <1>; | |
238 | clocks = <&coreclk 0>; | |
239 | status = "disabled"; | |
240 | }; | |
241 | ||
242 | pinctrl@18000 { | |
243 | i2c0_pins: i2c0-pins { | |
244 | marvell,pins = "mpp2", "mpp3"; | |
245 | marvell,function = "i2c0"; | |
246 | }; | |
247 | ||
248 | uart0_pins: uart0-pins { | |
249 | marvell,pins = "mpp0", "mpp1"; | |
250 | marvell,function = "ua0"; | |
251 | }; | |
252 | ||
253 | uart1_pins: uart1-pins { | |
254 | marvell,pins = "mpp19", "mpp20"; | |
255 | marvell,function = "ua1"; | |
256 | }; | |
257 | ||
258 | spi1_pins: spi1-pins { | |
259 | marvell,pins = "mpp56", "mpp57", "mpp58", "mpp59"; | |
260 | marvell,function = "spi1"; | |
261 | }; | |
262 | ||
263 | nand_pins: nand-pins { | |
264 | marvell,pins = "mpp22", "mpp34", "mpp23", "mpp33", | |
265 | "mpp38", "mpp28", "mpp40", "mpp42", | |
266 | "mpp35", "mpp36", "mpp25", "mpp30", | |
267 | "mpp32"; | |
268 | marvell,function = "dev"; | |
269 | }; | |
270 | }; | |
271 | ||
272 | system-controller@18200 { | |
273 | compatible = "marvell,armada-390-system-controller", | |
274 | "marvell,armada-370-xp-system-controller"; | |
275 | reg = <0x18200 0x100>; | |
276 | }; | |
277 | ||
278 | gateclk: clock-gating-control@18220 { | |
279 | compatible = "marvell,armada-390-gating-clock"; | |
280 | reg = <0x18220 0x4>; | |
281 | clocks = <&coreclk 0>; | |
282 | #clock-cells = <1>; | |
283 | }; | |
284 | ||
285 | coreclk: mvebu-sar@18600 { | |
286 | compatible = "marvell,armada-390-core-clock"; | |
287 | reg = <0x18600 0x04>; | |
288 | #clock-cells = <1>; | |
289 | }; | |
290 | ||
291 | mbusc: mbus-controller@20000 { | |
292 | compatible = "marvell,mbus-controller"; | |
293 | reg = <0x20000 0x100>, <0x20180 0x20>, <0x20250 0x8>; | |
294 | }; | |
295 | ||
296 | mpic: interrupt-controller@20a00 { | |
297 | compatible = "marvell,mpic"; | |
298 | reg = <0x20a00 0x2d0>, <0x21070 0x58>; | |
299 | #interrupt-cells = <1>; | |
300 | #size-cells = <1>; | |
301 | interrupt-controller; | |
302 | msi-controller; | |
303 | interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>; | |
304 | }; | |
305 | ||
306 | timer@20300 { | |
307 | compatible = "marvell,armada-380-timer", | |
308 | "marvell,armada-xp-timer"; | |
309 | reg = <0x20300 0x30>, <0x21040 0x30>; | |
310 | interrupts-extended = <&gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, | |
311 | <&gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, | |
312 | <&gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, | |
313 | <&gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, | |
314 | <&mpic 5>, | |
315 | <&mpic 6>; | |
316 | clocks = <&coreclk 2>, <&coreclk 5>; | |
317 | clock-names = "nbclk", "fixed"; | |
318 | }; | |
319 | ||
320 | cpurst@20800 { | |
321 | compatible = "marvell,armada-370-cpu-reset"; | |
322 | reg = <0x20800 0x10>; | |
323 | }; | |
324 | ||
325 | pmsu@22000 { | |
326 | compatible = "marvell,armada-390-pmsu", | |
327 | "marvell,armada-380-pmsu"; | |
328 | reg = <0x22000 0x1000>; | |
329 | }; | |
330 | ||
331 | xor@60800 { | |
449e1d64 | 332 | compatible = "marvell,armada-380-xor", "marvell,orion-xor"; |
538da83d TP |
333 | reg = <0x60800 0x100 |
334 | 0x60a00 0x100>; | |
335 | clocks = <&gateclk 22>; | |
336 | status = "okay"; | |
337 | ||
338 | xor00 { | |
339 | interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; | |
340 | dmacap,memcpy; | |
341 | dmacap,xor; | |
342 | }; | |
343 | xor01 { | |
344 | interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; | |
345 | dmacap,memcpy; | |
346 | dmacap,xor; | |
347 | dmacap,memset; | |
348 | }; | |
349 | }; | |
350 | ||
351 | xor@60900 { | |
449e1d64 | 352 | compatible = "marvell,armada-380-xor", "marvell,orion-xor"; |
538da83d TP |
353 | reg = <0x60900 0x100 |
354 | 0x60b00 0x100>; | |
355 | clocks = <&gateclk 28>; | |
356 | status = "okay"; | |
357 | ||
358 | xor10 { | |
359 | interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; | |
360 | dmacap,memcpy; | |
361 | dmacap,xor; | |
362 | }; | |
363 | xor11 { | |
364 | interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; | |
365 | dmacap,memcpy; | |
366 | dmacap,xor; | |
367 | dmacap,memset; | |
368 | }; | |
369 | }; | |
370 | ||
371 | flash@d0000 { | |
372 | compatible = "marvell,armada370-nand"; | |
373 | reg = <0xd0000 0x54>; | |
374 | #address-cells = <1>; | |
375 | #size-cells = <1>; | |
376 | interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; | |
377 | clocks = <&coredivclk 0>; | |
378 | status = "disabled"; | |
379 | }; | |
380 | ||
381 | sdhci@d8000 { | |
382 | compatible = "marvell,armada-380-sdhci"; | |
383 | reg = <0xd8000 0x1000>, <0xdc000 0x100>; | |
384 | interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; | |
385 | clocks = <&gateclk 17>; | |
386 | mrvl,clk-delay-cycles = <0x1F>; | |
387 | status = "disabled"; | |
388 | }; | |
389 | ||
390 | coredivclk: clock@e4250 { | |
391 | compatible = "marvell,armada-390-corediv-clock", | |
392 | "marvell,armada-380-corediv-clock"; | |
393 | reg = <0xe4250 0xc>; | |
394 | #clock-cells = <1>; | |
395 | clocks = <&mainpll>; | |
396 | clock-output-names = "nand"; | |
397 | }; | |
398 | }; | |
399 | ||
400 | pcie-controller { | |
401 | compatible = "marvell,armada-370-pcie"; | |
402 | status = "disabled"; | |
403 | device_type = "pci"; | |
404 | ||
405 | #address-cells = <3>; | |
406 | #size-cells = <2>; | |
407 | ||
408 | msi-parent = <&mpic>; | |
409 | bus-range = <0x00 0xff>; | |
410 | ||
411 | ranges = | |
412 | <0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 | |
413 | 0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 | |
414 | 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 | |
415 | 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 | |
416 | 0x82000000 0x1 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 0 MEM */ | |
417 | 0x81000000 0x1 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 0 IO */ | |
418 | 0x82000000 0x2 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 1 MEM */ | |
419 | 0x81000000 0x2 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 1 IO */ | |
420 | 0x82000000 0x3 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 2 MEM */ | |
421 | 0x81000000 0x3 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 2 IO */ | |
422 | 0x82000000 0x4 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 3 MEM */ | |
423 | 0x81000000 0x4 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 3 IO */>; | |
424 | ||
425 | /* | |
426 | * This port can be either x4 or x1. When | |
427 | * configured in x4 by the bootloader, then | |
428 | * pcie@4,0 is not available. | |
429 | */ | |
430 | pcie@1,0 { | |
431 | device_type = "pci"; | |
432 | assigned-addresses = <0x82000800 0 0x80000 0 0x2000>; | |
433 | reg = <0x0800 0 0 0 0>; | |
434 | #address-cells = <3>; | |
435 | #size-cells = <2>; | |
436 | #interrupt-cells = <1>; | |
437 | ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 | |
438 | 0x81000000 0 0 0x81000000 0x1 0 1 0>; | |
439 | interrupt-map-mask = <0 0 0 0>; | |
440 | interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; | |
441 | marvell,pcie-port = <0>; | |
442 | marvell,pcie-lane = <0>; | |
443 | clocks = <&gateclk 8>; | |
444 | status = "disabled"; | |
445 | }; | |
446 | ||
447 | /* x1 port */ | |
448 | pcie@2,0 { | |
449 | device_type = "pci"; | |
450 | assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; | |
451 | reg = <0x1000 0 0 0 0>; | |
452 | #address-cells = <3>; | |
453 | #size-cells = <2>; | |
454 | #interrupt-cells = <1>; | |
455 | ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 | |
456 | 0x81000000 0 0 0x81000000 0x2 0 1 0>; | |
457 | interrupt-map-mask = <0 0 0 0>; | |
458 | interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; | |
459 | marvell,pcie-port = <1>; | |
460 | marvell,pcie-lane = <0>; | |
461 | clocks = <&gateclk 5>; | |
462 | status = "disabled"; | |
463 | }; | |
464 | ||
465 | /* x1 port */ | |
466 | pcie@3,0 { | |
467 | device_type = "pci"; | |
468 | assigned-addresses = <0x82000800 0 0x44000 0 0x2000>; | |
469 | reg = <0x1800 0 0 0 0>; | |
470 | #address-cells = <3>; | |
471 | #size-cells = <2>; | |
472 | #interrupt-cells = <1>; | |
473 | ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 | |
474 | 0x81000000 0 0 0x81000000 0x3 0 1 0>; | |
475 | interrupt-map-mask = <0 0 0 0>; | |
476 | interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; | |
477 | marvell,pcie-port = <2>; | |
478 | marvell,pcie-lane = <0>; | |
479 | clocks = <&gateclk 6>; | |
480 | status = "disabled"; | |
481 | }; | |
482 | ||
483 | /* | |
484 | * x1 port only available when pcie@1,0 is | |
485 | * configured as a x1 port | |
486 | */ | |
487 | pcie@4,0 { | |
488 | device_type = "pci"; | |
489 | assigned-addresses = <0x82000800 0 0x48000 0 0x2000>; | |
490 | reg = <0x2000 0 0 0 0>; | |
491 | #address-cells = <3>; | |
492 | #size-cells = <2>; | |
493 | #interrupt-cells = <1>; | |
494 | ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0 | |
495 | 0x81000000 0 0 0x81000000 0x4 0 1 0>; | |
496 | interrupt-map-mask = <0 0 0 0>; | |
497 | interrupt-map = <0 0 0 0 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; | |
498 | marvell,pcie-port = <3>; | |
499 | marvell,pcie-lane = <0>; | |
500 | clocks = <&gateclk 7>; | |
501 | status = "disabled"; | |
502 | }; | |
503 | }; | |
504 | }; | |
505 | ||
506 | clocks { | |
507 | /* 2 GHz fixed main PLL */ | |
508 | mainpll: mainpll { | |
509 | compatible = "fixed-clock"; | |
510 | #clock-cells = <0>; | |
ae142bd9 | 511 | clock-frequency = <1000000000>; |
538da83d TP |
512 | }; |
513 | }; | |
514 | }; |