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538da83d TP |
1 | /* |
2 | * Device Tree Include file for Marvell Armada 39x family of SoCs. | |
3 | * | |
4 | * Copyright (C) 2015 Marvell | |
5 | * | |
6 | * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> | |
7 | * | |
8 | * This file is dual-licensed: you can use it either under the terms | |
9 | * of the GPL or the X11 license, at your option. Note that this dual | |
10 | * licensing only applies to this file, and not this project as a | |
11 | * whole. | |
12 | * | |
13 | * a) This file is free software; you can redistribute it and/or | |
14 | * modify it under the terms of the GNU General Public License as | |
15 | * published by the Free Software Foundation; either version 2 of the | |
16 | * License, or (at your option) any later version. | |
17 | * | |
18 | * This file is distributed in the hope that it will be useful | |
19 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
20 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
21 | * GNU General Public License for more details. | |
22 | * | |
23 | * Or, alternatively | |
24 | * | |
25 | * b) Permission is hereby granted, free of charge, to any person | |
26 | * obtaining a copy of this software and associated documentation | |
27 | * files (the "Software"), to deal in the Software without | |
28 | * restriction, including without limitation the rights to use | |
29 | * copy, modify, merge, publish, distribute, sublicense, and/or | |
30 | * sell copies of the Software, and to permit persons to whom the | |
31 | * Software is furnished to do so, subject to the following | |
32 | * conditions: | |
33 | * | |
34 | * The above copyright notice and this permission notice shall be | |
35 | * included in all copies or substantial portions of the Software. | |
36 | * | |
37 | * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND | |
38 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES | |
39 | * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
40 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT | |
41 | * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY | |
42 | * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
43 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
44 | * OTHER DEALINGS IN THE SOFTWARE. | |
45 | */ | |
46 | ||
47 | #include "skeleton.dtsi" | |
48 | #include <dt-bindings/interrupt-controller/arm-gic.h> | |
49 | #include <dt-bindings/interrupt-controller/irq.h> | |
50 | ||
51 | #define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16)) | |
52 | ||
53 | / { | |
54 | model = "Marvell Armada 39x family SoC"; | |
55 | compatible = "marvell,armada390"; | |
56 | ||
57 | aliases { | |
d81a914f GJ |
58 | gpio0 = &gpio0; |
59 | gpio1 = &gpio1; | |
538da83d TP |
60 | serial0 = &uart0; |
61 | serial1 = &uart1; | |
62 | serial2 = &uart2; | |
63 | serial3 = &uart3; | |
64 | }; | |
65 | ||
66 | cpus { | |
67 | #address-cells = <1>; | |
68 | #size-cells = <0>; | |
69 | enable-method = "marvell,armada-390-smp"; | |
70 | ||
71 | cpu@0 { | |
72 | device_type = "cpu"; | |
73 | compatible = "arm,cortex-a9"; | |
74 | reg = <0>; | |
75 | }; | |
76 | cpu@1 { | |
77 | device_type = "cpu"; | |
78 | compatible = "arm,cortex-a9"; | |
79 | reg = <1>; | |
80 | }; | |
81 | }; | |
82 | ||
8deebf8b GJ |
83 | pmu { |
84 | compatible = "arm,cortex-a9-pmu"; | |
85 | interrupts-extended = <&mpic 3>; | |
86 | }; | |
87 | ||
538da83d TP |
88 | soc { |
89 | compatible = "marvell,armada390-mbus", "marvell,armadaxp-mbus", | |
90 | "simple-bus"; | |
91 | #address-cells = <2>; | |
92 | #size-cells = <1>; | |
93 | controller = <&mbusc>; | |
94 | interrupt-parent = <&gic>; | |
95 | pcie-mem-aperture = <0xe0000000 0x8000000>; | |
96 | pcie-io-aperture = <0xe8000000 0x100000>; | |
97 | ||
98 | bootrom { | |
99 | compatible = "marvell,bootrom"; | |
100 | reg = <MBUS_ID(0x01, 0x1d) 0 0x200000>; | |
101 | }; | |
102 | ||
103 | internal-regs { | |
104 | compatible = "simple-bus"; | |
105 | #address-cells = <1>; | |
106 | #size-cells = <1>; | |
107 | ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>; | |
108 | ||
109 | L2: cache-controller@8000 { | |
110 | compatible = "arm,pl310-cache"; | |
111 | reg = <0x8000 0x1000>; | |
112 | cache-unified; | |
113 | cache-level = <2>; | |
c8f5a878 TP |
114 | arm,double-linefill-incr = <1>; |
115 | arm,double-linefill-wrap = <0>; | |
116 | arm,double-linefill = <1>; | |
117 | prefetch-data = <1>; | |
538da83d TP |
118 | }; |
119 | ||
120 | scu@c000 { | |
121 | compatible = "arm,cortex-a9-scu"; | |
122 | reg = <0xc000 0x100>; | |
123 | }; | |
124 | ||
125 | timer@c600 { | |
126 | compatible = "arm,cortex-a9-twd-timer"; | |
127 | reg = <0xc600 0x20>; | |
128 | interrupts = <GIC_PPI 13 (IRQ_TYPE_EDGE_RISING | GIC_CPU_MASK_SIMPLE(2))>; | |
129 | clocks = <&coreclk 2>; | |
130 | }; | |
131 | ||
132 | gic: interrupt-controller@d000 { | |
133 | compatible = "arm,cortex-a9-gic"; | |
134 | #interrupt-cells = <3>; | |
135 | #size-cells = <0>; | |
136 | interrupt-controller; | |
137 | reg = <0xd000 0x1000>, | |
138 | <0xc100 0x100>; | |
139 | }; | |
140 | ||
538da83d TP |
141 | i2c0: i2c@11000 { |
142 | compatible = "marvell,mv64xxx-i2c"; | |
143 | reg = <0x11000 0x20>; | |
144 | #address-cells = <1>; | |
145 | #size-cells = <0>; | |
146 | interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; | |
147 | timeout-ms = <1000>; | |
148 | clocks = <&coreclk 0>; | |
149 | status = "disabled"; | |
150 | }; | |
151 | ||
152 | i2c1: i2c@11100 { | |
153 | compatible = "marvell,mv64xxx-i2c"; | |
154 | reg = <0x11100 0x20>; | |
155 | #address-cells = <1>; | |
156 | #size-cells = <0>; | |
157 | interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; | |
158 | timeout-ms = <1000>; | |
159 | clocks = <&coreclk 0>; | |
160 | status = "disabled"; | |
161 | }; | |
162 | ||
163 | i2c2: i2c@11200 { | |
164 | compatible = "marvell,mv64xxx-i2c"; | |
165 | reg = <0x11200 0x20>; | |
166 | #address-cells = <1>; | |
167 | #size-cells = <0>; | |
168 | interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; | |
169 | timeout-ms = <1000>; | |
170 | clocks = <&coreclk 0>; | |
171 | status = "disabled"; | |
172 | }; | |
173 | ||
174 | i2c3: i2c@11300 { | |
175 | compatible = "marvell,mv64xxx-i2c"; | |
176 | reg = <0x11300 0x20>; | |
177 | #address-cells = <1>; | |
178 | #size-cells = <0>; | |
179 | interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; | |
180 | timeout-ms = <1000>; | |
181 | clocks = <&coreclk 0>; | |
182 | status = "disabled"; | |
183 | }; | |
184 | ||
185 | uart0: serial@12000 { | |
186 | compatible = "snps,dw-apb-uart"; | |
187 | reg = <0x12000 0x100>; | |
188 | reg-shift = <2>; | |
189 | interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; | |
190 | reg-io-width = <1>; | |
191 | clocks = <&coreclk 0>; | |
192 | status = "disabled"; | |
193 | }; | |
194 | ||
195 | uart1: serial@12100 { | |
196 | compatible = "snps,dw-apb-uart"; | |
197 | reg = <0x12100 0x100>; | |
198 | reg-shift = <2>; | |
199 | interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; | |
200 | reg-io-width = <1>; | |
201 | clocks = <&coreclk 0>; | |
202 | status = "disabled"; | |
203 | }; | |
204 | ||
205 | uart2: serial@12200 { | |
206 | compatible = "snps,dw-apb-uart"; | |
207 | reg = <0x12200 0x100>; | |
208 | reg-shift = <2>; | |
209 | interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; | |
210 | reg-io-width = <1>; | |
211 | clocks = <&coreclk 0>; | |
212 | status = "disabled"; | |
213 | }; | |
214 | ||
215 | uart3: serial@12300 { | |
216 | compatible = "snps,dw-apb-uart"; | |
217 | reg = <0x12300 0x100>; | |
218 | reg-shift = <2>; | |
219 | interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; | |
220 | reg-io-width = <1>; | |
221 | clocks = <&coreclk 0>; | |
222 | status = "disabled"; | |
223 | }; | |
224 | ||
225 | pinctrl@18000 { | |
226 | i2c0_pins: i2c0-pins { | |
227 | marvell,pins = "mpp2", "mpp3"; | |
228 | marvell,function = "i2c0"; | |
229 | }; | |
230 | ||
231 | uart0_pins: uart0-pins { | |
232 | marvell,pins = "mpp0", "mpp1"; | |
233 | marvell,function = "ua0"; | |
234 | }; | |
235 | ||
236 | uart1_pins: uart1-pins { | |
237 | marvell,pins = "mpp19", "mpp20"; | |
238 | marvell,function = "ua1"; | |
239 | }; | |
240 | ||
241 | spi1_pins: spi1-pins { | |
242 | marvell,pins = "mpp56", "mpp57", "mpp58", "mpp59"; | |
243 | marvell,function = "spi1"; | |
244 | }; | |
245 | ||
246 | nand_pins: nand-pins { | |
247 | marvell,pins = "mpp22", "mpp34", "mpp23", "mpp33", | |
248 | "mpp38", "mpp28", "mpp40", "mpp42", | |
249 | "mpp35", "mpp36", "mpp25", "mpp30", | |
250 | "mpp32"; | |
251 | marvell,function = "dev"; | |
252 | }; | |
253 | }; | |
254 | ||
d81a914f GJ |
255 | gpio0: gpio@18100 { |
256 | compatible = "marvell,orion-gpio"; | |
257 | reg = <0x18100 0x40>; | |
258 | ngpios = <32>; | |
259 | gpio-controller; | |
260 | #gpio-cells = <2>; | |
261 | interrupt-controller; | |
262 | #interrupt-cells = <2>; | |
263 | interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, | |
264 | <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, | |
265 | <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, | |
266 | <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; | |
267 | }; | |
268 | ||
269 | gpio1: gpio@18140 { | |
270 | compatible = "marvell,orion-gpio"; | |
271 | reg = <0x18140 0x40>; | |
272 | ngpios = <28>; | |
273 | gpio-controller; | |
274 | #gpio-cells = <2>; | |
275 | interrupt-controller; | |
276 | #interrupt-cells = <2>; | |
277 | interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, | |
278 | <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, | |
279 | <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, | |
280 | <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; | |
281 | }; | |
282 | ||
538da83d TP |
283 | system-controller@18200 { |
284 | compatible = "marvell,armada-390-system-controller", | |
285 | "marvell,armada-370-xp-system-controller"; | |
286 | reg = <0x18200 0x100>; | |
287 | }; | |
288 | ||
289 | gateclk: clock-gating-control@18220 { | |
290 | compatible = "marvell,armada-390-gating-clock"; | |
291 | reg = <0x18220 0x4>; | |
292 | clocks = <&coreclk 0>; | |
293 | #clock-cells = <1>; | |
294 | }; | |
295 | ||
296 | coreclk: mvebu-sar@18600 { | |
297 | compatible = "marvell,armada-390-core-clock"; | |
298 | reg = <0x18600 0x04>; | |
299 | #clock-cells = <1>; | |
300 | }; | |
301 | ||
302 | mbusc: mbus-controller@20000 { | |
303 | compatible = "marvell,mbus-controller"; | |
304 | reg = <0x20000 0x100>, <0x20180 0x20>, <0x20250 0x8>; | |
305 | }; | |
306 | ||
307 | mpic: interrupt-controller@20a00 { | |
308 | compatible = "marvell,mpic"; | |
309 | reg = <0x20a00 0x2d0>, <0x21070 0x58>; | |
310 | #interrupt-cells = <1>; | |
311 | #size-cells = <1>; | |
312 | interrupt-controller; | |
313 | msi-controller; | |
314 | interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>; | |
315 | }; | |
316 | ||
317 | timer@20300 { | |
318 | compatible = "marvell,armada-380-timer", | |
319 | "marvell,armada-xp-timer"; | |
320 | reg = <0x20300 0x30>, <0x21040 0x30>; | |
321 | interrupts-extended = <&gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, | |
322 | <&gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, | |
323 | <&gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, | |
324 | <&gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, | |
325 | <&mpic 5>, | |
326 | <&mpic 6>; | |
327 | clocks = <&coreclk 2>, <&coreclk 5>; | |
328 | clock-names = "nbclk", "fixed"; | |
329 | }; | |
330 | ||
100a20a9 GJ |
331 | watchdog@20300 { |
332 | compatible = "marvell,armada-380-wdt"; | |
333 | reg = <0x20300 0x34>, <0x20704 0x4>, | |
334 | <0x18260 0x4>; | |
335 | clocks = <&coreclk 2>, <&refclk>; | |
336 | clock-names = "nbclk", "fixed"; | |
337 | }; | |
338 | ||
538da83d TP |
339 | cpurst@20800 { |
340 | compatible = "marvell,armada-370-cpu-reset"; | |
341 | reg = <0x20800 0x10>; | |
342 | }; | |
343 | ||
8deebf8b GJ |
344 | mpcore-soc-ctrl@20d20 { |
345 | compatible = "marvell,armada-380-mpcore-soc-ctrl"; | |
346 | reg = <0x20d20 0x6c>; | |
347 | }; | |
348 | ||
349 | coherency-fabric@21010 { | |
350 | compatible = "marvell,armada-380-coherency-fabric"; | |
351 | reg = <0x21010 0x1c>; | |
352 | }; | |
353 | ||
538da83d TP |
354 | pmsu@22000 { |
355 | compatible = "marvell,armada-390-pmsu", | |
356 | "marvell,armada-380-pmsu"; | |
357 | reg = <0x22000 0x1000>; | |
358 | }; | |
359 | ||
360 | xor@60800 { | |
449e1d64 | 361 | compatible = "marvell,armada-380-xor", "marvell,orion-xor"; |
538da83d TP |
362 | reg = <0x60800 0x100 |
363 | 0x60a00 0x100>; | |
364 | clocks = <&gateclk 22>; | |
365 | status = "okay"; | |
366 | ||
367 | xor00 { | |
368 | interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; | |
369 | dmacap,memcpy; | |
370 | dmacap,xor; | |
371 | }; | |
372 | xor01 { | |
373 | interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; | |
374 | dmacap,memcpy; | |
375 | dmacap,xor; | |
376 | dmacap,memset; | |
377 | }; | |
378 | }; | |
379 | ||
380 | xor@60900 { | |
449e1d64 | 381 | compatible = "marvell,armada-380-xor", "marvell,orion-xor"; |
538da83d TP |
382 | reg = <0x60900 0x100 |
383 | 0x60b00 0x100>; | |
384 | clocks = <&gateclk 28>; | |
385 | status = "okay"; | |
386 | ||
387 | xor10 { | |
388 | interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; | |
389 | dmacap,memcpy; | |
390 | dmacap,xor; | |
391 | }; | |
392 | xor11 { | |
393 | interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; | |
394 | dmacap,memcpy; | |
395 | dmacap,xor; | |
396 | dmacap,memset; | |
397 | }; | |
398 | }; | |
399 | ||
daab5431 GJ |
400 | rtc@a3800 { |
401 | compatible = "marvell,armada-380-rtc"; | |
402 | reg = <0xa3800 0x20>, <0x184a0 0x0c>; | |
403 | reg-names = "rtc", "rtc-soc"; | |
404 | interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; | |
405 | }; | |
406 | ||
538da83d TP |
407 | flash@d0000 { |
408 | compatible = "marvell,armada370-nand"; | |
409 | reg = <0xd0000 0x54>; | |
410 | #address-cells = <1>; | |
411 | #size-cells = <1>; | |
412 | interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; | |
413 | clocks = <&coredivclk 0>; | |
414 | status = "disabled"; | |
415 | }; | |
416 | ||
417 | sdhci@d8000 { | |
418 | compatible = "marvell,armada-380-sdhci"; | |
39f3c23f GJ |
419 | reg-names = "sdhci", "mbus", "conf-sdio3"; |
420 | reg = <0xd8000 0x1000>, | |
421 | <0xdc000 0x100>, | |
422 | <0x18454 0x4>; | |
538da83d TP |
423 | interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; |
424 | clocks = <&gateclk 17>; | |
425 | mrvl,clk-delay-cycles = <0x1F>; | |
426 | status = "disabled"; | |
427 | }; | |
428 | ||
429 | coredivclk: clock@e4250 { | |
430 | compatible = "marvell,armada-390-corediv-clock", | |
431 | "marvell,armada-380-corediv-clock"; | |
432 | reg = <0xe4250 0xc>; | |
433 | #clock-cells = <1>; | |
434 | clocks = <&mainpll>; | |
435 | clock-output-names = "nand"; | |
436 | }; | |
16ae8831 GJ |
437 | |
438 | thermal@e8078 { | |
439 | compatible = "marvell,armada380-thermal"; | |
440 | reg = <0xe4078 0x4>, <0xe4074 0x4>; | |
441 | status = "okay"; | |
442 | }; | |
538da83d TP |
443 | }; |
444 | ||
445 | pcie-controller { | |
446 | compatible = "marvell,armada-370-pcie"; | |
447 | status = "disabled"; | |
448 | device_type = "pci"; | |
449 | ||
450 | #address-cells = <3>; | |
451 | #size-cells = <2>; | |
452 | ||
453 | msi-parent = <&mpic>; | |
454 | bus-range = <0x00 0xff>; | |
455 | ||
456 | ranges = | |
457 | <0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 | |
458 | 0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 | |
459 | 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 | |
460 | 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 | |
461 | 0x82000000 0x1 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 0 MEM */ | |
462 | 0x81000000 0x1 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 0 IO */ | |
463 | 0x82000000 0x2 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 1 MEM */ | |
464 | 0x81000000 0x2 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 1 IO */ | |
465 | 0x82000000 0x3 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 2 MEM */ | |
466 | 0x81000000 0x3 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 2 IO */ | |
467 | 0x82000000 0x4 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 3 MEM */ | |
468 | 0x81000000 0x4 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 3 IO */>; | |
469 | ||
470 | /* | |
471 | * This port can be either x4 or x1. When | |
472 | * configured in x4 by the bootloader, then | |
473 | * pcie@4,0 is not available. | |
474 | */ | |
475 | pcie@1,0 { | |
476 | device_type = "pci"; | |
477 | assigned-addresses = <0x82000800 0 0x80000 0 0x2000>; | |
478 | reg = <0x0800 0 0 0 0>; | |
479 | #address-cells = <3>; | |
480 | #size-cells = <2>; | |
481 | #interrupt-cells = <1>; | |
482 | ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 | |
483 | 0x81000000 0 0 0x81000000 0x1 0 1 0>; | |
484 | interrupt-map-mask = <0 0 0 0>; | |
485 | interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; | |
486 | marvell,pcie-port = <0>; | |
487 | marvell,pcie-lane = <0>; | |
488 | clocks = <&gateclk 8>; | |
489 | status = "disabled"; | |
490 | }; | |
491 | ||
492 | /* x1 port */ | |
493 | pcie@2,0 { | |
494 | device_type = "pci"; | |
495 | assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; | |
496 | reg = <0x1000 0 0 0 0>; | |
497 | #address-cells = <3>; | |
498 | #size-cells = <2>; | |
499 | #interrupt-cells = <1>; | |
500 | ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 | |
501 | 0x81000000 0 0 0x81000000 0x2 0 1 0>; | |
502 | interrupt-map-mask = <0 0 0 0>; | |
503 | interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; | |
504 | marvell,pcie-port = <1>; | |
505 | marvell,pcie-lane = <0>; | |
506 | clocks = <&gateclk 5>; | |
507 | status = "disabled"; | |
508 | }; | |
509 | ||
510 | /* x1 port */ | |
511 | pcie@3,0 { | |
512 | device_type = "pci"; | |
513 | assigned-addresses = <0x82000800 0 0x44000 0 0x2000>; | |
514 | reg = <0x1800 0 0 0 0>; | |
515 | #address-cells = <3>; | |
516 | #size-cells = <2>; | |
517 | #interrupt-cells = <1>; | |
518 | ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 | |
519 | 0x81000000 0 0 0x81000000 0x3 0 1 0>; | |
520 | interrupt-map-mask = <0 0 0 0>; | |
521 | interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; | |
522 | marvell,pcie-port = <2>; | |
523 | marvell,pcie-lane = <0>; | |
524 | clocks = <&gateclk 6>; | |
525 | status = "disabled"; | |
526 | }; | |
527 | ||
528 | /* | |
529 | * x1 port only available when pcie@1,0 is | |
530 | * configured as a x1 port | |
531 | */ | |
532 | pcie@4,0 { | |
533 | device_type = "pci"; | |
534 | assigned-addresses = <0x82000800 0 0x48000 0 0x2000>; | |
535 | reg = <0x2000 0 0 0 0>; | |
536 | #address-cells = <3>; | |
537 | #size-cells = <2>; | |
538 | #interrupt-cells = <1>; | |
539 | ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0 | |
540 | 0x81000000 0 0 0x81000000 0x4 0 1 0>; | |
541 | interrupt-map-mask = <0 0 0 0>; | |
542 | interrupt-map = <0 0 0 0 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; | |
543 | marvell,pcie-port = <3>; | |
544 | marvell,pcie-lane = <0>; | |
545 | clocks = <&gateclk 7>; | |
546 | status = "disabled"; | |
547 | }; | |
548 | }; | |
0160a4b6 SR |
549 | |
550 | spi0: spi@10600 { | |
551 | compatible = "marvell,armada-390-spi", | |
552 | "marvell,orion-spi"; | |
553 | reg = <MBUS_ID(0xf0, 0x01) 0x10600 0x50>; | |
554 | #address-cells = <1>; | |
555 | #size-cells = <0>; | |
556 | cell-index = <0>; | |
557 | interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; | |
558 | clocks = <&coreclk 0>; | |
559 | status = "disabled"; | |
560 | }; | |
561 | ||
562 | spi1: spi@10680 { | |
563 | compatible = "marvell,armada-390-spi", | |
564 | "marvell,orion-spi"; | |
565 | reg = <MBUS_ID(0xf0, 0x01) 0x10680 0x50>; | |
566 | #address-cells = <1>; | |
567 | #size-cells = <0>; | |
568 | cell-index = <1>; | |
569 | interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; | |
570 | clocks = <&coreclk 0>; | |
571 | status = "disabled"; | |
572 | }; | |
538da83d TP |
573 | }; |
574 | ||
575 | clocks { | |
576 | /* 2 GHz fixed main PLL */ | |
577 | mainpll: mainpll { | |
578 | compatible = "fixed-clock"; | |
579 | #clock-cells = <0>; | |
ae142bd9 | 580 | clock-frequency = <1000000000>; |
538da83d | 581 | }; |
100a20a9 GJ |
582 | |
583 | /* 25 MHz reference crystal */ | |
584 | refclk: oscillator { | |
585 | compatible = "fixed-clock"; | |
586 | #clock-cells = <0>; | |
587 | clock-frequency = <25000000>; | |
588 | }; | |
538da83d TP |
589 | }; |
590 | }; |