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1 | /* |
2 | * Device Tree file for Marvell Armada XP evaluation board | |
3 | * (DB-78460-BP) | |
4 | * | |
82066bdb | 5 | * Copyright (C) 2012-2014 Marvell |
9ae6f740 TP |
6 | * |
7 | * Lior Amsalem <alior@marvell.com> | |
8 | * Gregory CLEMENT <gregory.clement@free-electrons.com> | |
9 | * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> | |
10 | * | |
11 | * This file is licensed under the terms of the GNU General Public | |
12 | * License version 2. This program is licensed "as is" without any | |
13 | * warranty of any kind, whether express or implied. | |
82066bdb TP |
14 | * |
15 | * Note: this Device Tree assumes that the bootloader has remapped the | |
16 | * internal registers to 0xf1000000 (instead of the default | |
17 | * 0xd0000000). The 0xf1000000 is the default used by the recent, | |
18 | * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier | |
19 | * boards were delivered with an older version of the bootloader that | |
20 | * left internal registers mapped at 0xd0000000. If you are in this | |
21 | * situation, you should either update your bootloader (preferred | |
22 | * solution) or the below Device Tree should be adjusted. | |
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23 | */ |
24 | ||
25 | /dts-v1/; | |
38149887 | 26 | #include "armada-xp-mv78460.dtsi" |
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27 | |
28 | / { | |
29 | model = "Marvell Armada XP Evaluation Board"; | |
0bec30a7 | 30 | compatible = "marvell,axp-db", "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp"; |
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31 | |
32 | chosen { | |
33 | bootargs = "console=ttyS0,115200 earlyprintk"; | |
34 | }; | |
35 | ||
36 | memory { | |
37 | device_type = "memory"; | |
74898364 | 38 | reg = <0 0x00000000 0 0x80000000>; /* 2 GB */ |
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39 | }; |
40 | ||
41 | soc { | |
82066bdb | 42 | ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000 |
de1af8d4 EG |
43 | MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000 |
44 | MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000>; | |
45 | ||
46 | devbus-bootcs { | |
47 | status = "okay"; | |
48 | ||
49 | /* Device Bus parameters are required */ | |
50 | ||
51 | /* Read parameters */ | |
f3aec8f3 | 52 | devbus,bus-width = <16>; |
de1af8d4 EG |
53 | devbus,turn-off-ps = <60000>; |
54 | devbus,badr-skew-ps = <0>; | |
55 | devbus,acc-first-ps = <124000>; | |
56 | devbus,acc-next-ps = <248000>; | |
57 | devbus,rd-setup-ps = <0>; | |
58 | devbus,rd-hold-ps = <0>; | |
59 | ||
60 | /* Write parameters */ | |
61 | devbus,sync-enable = <0>; | |
62 | devbus,wr-high-ps = <60000>; | |
63 | devbus,wr-low-ps = <60000>; | |
64 | devbus,ale-wr-ps = <60000>; | |
65 | ||
66 | /* NOR 16 MiB */ | |
67 | nor@0 { | |
68 | compatible = "cfi-flash"; | |
69 | reg = <0 0x1000000>; | |
70 | bank-width = <2>; | |
71 | }; | |
72 | }; | |
b484ff42 | 73 | |
14fd8ed0 EG |
74 | pcie-controller { |
75 | status = "okay"; | |
76 | ||
77 | /* | |
78 | * All 6 slots are physically present as | |
79 | * standard PCIe slots on the board. | |
80 | */ | |
81 | pcie@1,0 { | |
82 | /* Port 0, Lane 0 */ | |
83 | status = "okay"; | |
84 | }; | |
85 | pcie@2,0 { | |
86 | /* Port 0, Lane 1 */ | |
87 | status = "okay"; | |
88 | }; | |
89 | pcie@3,0 { | |
90 | /* Port 0, Lane 2 */ | |
91 | status = "okay"; | |
92 | }; | |
93 | pcie@4,0 { | |
94 | /* Port 0, Lane 3 */ | |
95 | status = "okay"; | |
96 | }; | |
97 | pcie@9,0 { | |
98 | /* Port 2, Lane 0 */ | |
99 | status = "okay"; | |
100 | }; | |
101 | pcie@10,0 { | |
102 | /* Port 3, Lane 0 */ | |
103 | status = "okay"; | |
104 | }; | |
105 | }; | |
106 | ||
467f54b2 GC |
107 | internal-regs { |
108 | serial@12000 { | |
467f54b2 | 109 | status = "okay"; |
f01959a9 | 110 | }; |
467f54b2 | 111 | serial@12100 { |
467f54b2 | 112 | status = "okay"; |
f01959a9 | 113 | }; |
467f54b2 | 114 | serial@12200 { |
467f54b2 | 115 | status = "okay"; |
f01959a9 | 116 | }; |
467f54b2 | 117 | serial@12300 { |
467f54b2 | 118 | status = "okay"; |
f01959a9 | 119 | }; |
200506b1 | 120 | |
467f54b2 GC |
121 | sata@a0000 { |
122 | nr-ports = <2>; | |
123 | status = "okay"; | |
124 | }; | |
200506b1 | 125 | |
467f54b2 GC |
126 | mdio { |
127 | phy0: ethernet-phy@0 { | |
128 | reg = <0>; | |
129 | }; | |
200506b1 | 130 | |
467f54b2 GC |
131 | phy1: ethernet-phy@1 { |
132 | reg = <1>; | |
133 | }; | |
1f24a21f | 134 | |
467f54b2 GC |
135 | phy2: ethernet-phy@2 { |
136 | reg = <25>; | |
137 | }; | |
1f24a21f | 138 | |
467f54b2 GC |
139 | phy3: ethernet-phy@3 { |
140 | reg = <27>; | |
141 | }; | |
1f24a21f | 142 | }; |
bf4f9c63 | 143 | |
467f54b2 GC |
144 | ethernet@70000 { |
145 | status = "okay"; | |
146 | phy = <&phy0>; | |
147 | phy-mode = "rgmii-id"; | |
148 | }; | |
149 | ethernet@74000 { | |
150 | status = "okay"; | |
151 | phy = <&phy1>; | |
152 | phy-mode = "rgmii-id"; | |
153 | }; | |
154 | ethernet@30000 { | |
155 | status = "okay"; | |
156 | phy = <&phy2>; | |
157 | phy-mode = "sgmii"; | |
158 | }; | |
159 | ethernet@34000 { | |
160 | status = "okay"; | |
161 | phy = <&phy3>; | |
162 | phy-mode = "sgmii"; | |
163 | }; | |
bf4f9c63 | 164 | |
467f54b2 GC |
165 | mvsdio@d4000 { |
166 | pinctrl-0 = <&sdio_pins>; | |
167 | pinctrl-names = "default"; | |
bf4f9c63 | 168 | status = "okay"; |
467f54b2 | 169 | /* No CD or WP GPIOs */ |
d87b5fbb | 170 | broken-cd; |
bf4f9c63 | 171 | }; |
467f54b2 GC |
172 | |
173 | usb@50000 { | |
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174 | status = "okay"; |
175 | }; | |
467f54b2 GC |
176 | |
177 | usb@51000 { | |
bf4f9c63 TP |
178 | status = "okay"; |
179 | }; | |
467f54b2 GC |
180 | |
181 | usb@52000 { | |
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182 | status = "okay"; |
183 | }; | |
467f54b2 GC |
184 | |
185 | spi0: spi@10600 { | |
bf4f9c63 | 186 | status = "okay"; |
467f54b2 GC |
187 | |
188 | spi-flash@0 { | |
189 | #address-cells = <1>; | |
190 | #size-cells = <1>; | |
191 | compatible = "m25p64"; | |
192 | reg = <0>; /* Chip select 0 */ | |
193 | spi-max-frequency = <20000000>; | |
194 | }; | |
bf4f9c63 | 195 | }; |
bf4f9c63 | 196 | }; |
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197 | }; |
198 | }; |