Commit | Line | Data |
---|---|---|
568fc0a3 GC |
1 | /* |
2 | * Device Tree file for Marvell Armada XP development board | |
3 | * (DB-MV784MP-GP) | |
4 | * | |
91ed3220 | 5 | * Copyright (C) 2013-2014 Marvell |
568fc0a3 GC |
6 | * |
7 | * Lior Amsalem <alior@marvell.com> | |
8 | * Gregory CLEMENT <gregory.clement@free-electrons.com> | |
9 | * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> | |
10 | * | |
a0f22f8e GC |
11 | * This file is dual-licensed: you can use it either under the terms |
12 | * of the GPL or the X11 license, at your option. Note that this dual | |
13 | * licensing only applies to this file, and not this project as a | |
14 | * whole. | |
15 | * | |
16 | * a) This file is free software; you can redistribute it and/or | |
17 | * modify it under the terms of the GNU General Public License as | |
18 | * published by the Free Software Foundation; either version 2 of the | |
19 | * License, or (at your option) any later version. | |
20 | * | |
21 | * This file is distributed in the hope that it will be useful | |
22 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
23 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
24 | * GNU General Public License for more details. | |
25 | * | |
26 | * Or, alternatively | |
27 | * | |
28 | * b) Permission is hereby granted, free of charge, to any person | |
29 | * obtaining a copy of this software and associated documentation | |
30 | * files (the "Software"), to deal in the Software without | |
31 | * restriction, including without limitation the rights to use | |
32 | * copy, modify, merge, publish, distribute, sublicense, and/or | |
33 | * sell copies of the Software, and to permit persons to whom the | |
34 | * Software is furnished to do so, subject to the following | |
35 | * conditions: | |
36 | * | |
37 | * The above copyright notice and this permission notice shall be | |
38 | * included in all copies or substantial portions of the Software. | |
39 | * | |
40 | * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND | |
41 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES | |
42 | * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
43 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT | |
44 | * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY | |
45 | * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
46 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
47 | * OTHER DEALINGS IN THE SOFTWARE. | |
91ed3220 TP |
48 | * |
49 | * Note: this Device Tree assumes that the bootloader has remapped the | |
50 | * internal registers to 0xf1000000 (instead of the default | |
51 | * 0xd0000000). The 0xf1000000 is the default used by the recent, | |
52 | * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier | |
53 | * boards were delivered with an older version of the bootloader that | |
54 | * left internal registers mapped at 0xd0000000. If you are in this | |
55 | * situation, you should either update your bootloader (preferred | |
56 | * solution) or the below Device Tree should be adjusted. | |
568fc0a3 GC |
57 | */ |
58 | ||
59 | /dts-v1/; | |
389a367a | 60 | #include <dt-bindings/gpio/gpio.h> |
38149887 | 61 | #include "armada-xp-mv78460.dtsi" |
568fc0a3 GC |
62 | |
63 | / { | |
64 | model = "Marvell Armada XP Development Board DB-MV784MP-GP"; | |
65 | compatible = "marvell,axp-gp", "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp"; | |
66 | ||
67 | chosen { | |
9552203c | 68 | stdout-path = "serial0:115200n8"; |
568fc0a3 GC |
69 | }; |
70 | ||
71 | memory { | |
72 | device_type = "memory"; | |
568fc0a3 | 73 | /* |
74898364 GC |
74 | * 8 GB of plug-in RAM modules by default.The amount |
75 | * of memory available can be changed by the | |
76 | * bootloader according the size of the module | |
91ed3220 TP |
77 | * actually plugged. However, memory between |
78 | * 0xF0000000 to 0xFFFFFFFF cannot be used, as it is | |
79 | * the address range used for I/O (internal registers, | |
80 | * MBus windows). | |
568fc0a3 | 81 | */ |
91ed3220 | 82 | reg = <0x00000000 0x00000000 0x00000000 0xf0000000>, |
74898364 | 83 | <0x00000001 0x00000000 0x00000001 0x00000000>; |
568fc0a3 GC |
84 | }; |
85 | ||
389a367a TP |
86 | cpus { |
87 | pm_pic { | |
88 | ctrl-gpios = <&gpio0 16 GPIO_ACTIVE_LOW>, | |
89 | <&gpio0 17 GPIO_ACTIVE_LOW>, | |
90 | <&gpio0 18 GPIO_ACTIVE_LOW>; | |
91 | }; | |
92 | }; | |
93 | ||
568fc0a3 | 94 | soc { |
91ed3220 | 95 | ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000 |
de1af8d4 | 96 | MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000 |
c466d997 | 97 | MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000 |
d7d5a43c | 98 | MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000 |
1200b680 | 99 | MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000 |
9dd7a57e | 100 | MBUS_ID(0x0c, 0x04) 0 0 0xf1200000 0x100000>; |
de1af8d4 EG |
101 | |
102 | devbus-bootcs { | |
103 | status = "okay"; | |
104 | ||
105 | /* Device Bus parameters are required */ | |
106 | ||
107 | /* Read parameters */ | |
1a88f809 | 108 | devbus,bus-width = <16>; |
de1af8d4 EG |
109 | devbus,turn-off-ps = <60000>; |
110 | devbus,badr-skew-ps = <0>; | |
111 | devbus,acc-first-ps = <124000>; | |
112 | devbus,acc-next-ps = <248000>; | |
113 | devbus,rd-setup-ps = <0>; | |
114 | devbus,rd-hold-ps = <0>; | |
115 | ||
116 | /* Write parameters */ | |
117 | devbus,sync-enable = <0>; | |
118 | devbus,wr-high-ps = <60000>; | |
119 | devbus,wr-low-ps = <60000>; | |
120 | devbus,ale-wr-ps = <60000>; | |
121 | ||
122 | /* NOR 16 MiB */ | |
123 | nor@0 { | |
124 | compatible = "cfi-flash"; | |
125 | reg = <0 0x1000000>; | |
126 | bank-width = <2>; | |
127 | }; | |
128 | }; | |
c6c003af | 129 | |
14fd8ed0 EG |
130 | pcie-controller { |
131 | status = "okay"; | |
132 | ||
133 | /* | |
134 | * The 3 slots are physically present as | |
135 | * standard PCIe slots on the board. | |
136 | */ | |
137 | pcie@1,0 { | |
138 | /* Port 0, Lane 0 */ | |
139 | status = "okay"; | |
140 | }; | |
141 | pcie@9,0 { | |
142 | /* Port 2, Lane 0 */ | |
143 | status = "okay"; | |
144 | }; | |
145 | pcie@10,0 { | |
146 | /* Port 3, Lane 0 */ | |
147 | status = "okay"; | |
148 | }; | |
149 | }; | |
150 | ||
467f54b2 GC |
151 | internal-regs { |
152 | serial@12000 { | |
467f54b2 | 153 | status = "okay"; |
568fc0a3 | 154 | }; |
467f54b2 | 155 | serial@12100 { |
467f54b2 | 156 | status = "okay"; |
568fc0a3 | 157 | }; |
467f54b2 | 158 | serial@12200 { |
467f54b2 GC |
159 | status = "okay"; |
160 | }; | |
161 | serial@12300 { | |
467f54b2 | 162 | status = "okay"; |
568fc0a3 | 163 | }; |
389a367a TP |
164 | pinctrl { |
165 | pinctrl-0 = <&pic_pins>; | |
166 | pinctrl-names = "default"; | |
167 | pic_pins: pic-pins-0 { | |
168 | marvell,pins = "mpp16", "mpp17", | |
169 | "mpp18"; | |
170 | marvell,function = "gpio"; | |
171 | }; | |
172 | }; | |
467f54b2 GC |
173 | sata@a0000 { |
174 | nr-ports = <2>; | |
175 | status = "okay"; | |
568fc0a3 | 176 | }; |
568fc0a3 | 177 | |
467f54b2 GC |
178 | mdio { |
179 | phy0: ethernet-phy@0 { | |
180 | reg = <16>; | |
181 | }; | |
9dc3e346 | 182 | |
467f54b2 GC |
183 | phy1: ethernet-phy@1 { |
184 | reg = <17>; | |
185 | }; | |
9dc3e346 | 186 | |
467f54b2 GC |
187 | phy2: ethernet-phy@2 { |
188 | reg = <18>; | |
189 | }; | |
da8d1b38 | 190 | |
467f54b2 GC |
191 | phy3: ethernet-phy@3 { |
192 | reg = <19>; | |
193 | }; | |
da8d1b38 | 194 | }; |
513a7917 | 195 | |
467f54b2 GC |
196 | ethernet@70000 { |
197 | status = "okay"; | |
198 | phy = <&phy0>; | |
80fa10f4 | 199 | phy-mode = "qsgmii"; |
9dd7a57e MW |
200 | buffer-manager = <&bm>; |
201 | bm,pool-long = <0>; | |
467f54b2 GC |
202 | }; |
203 | ethernet@74000 { | |
204 | status = "okay"; | |
205 | phy = <&phy1>; | |
80fa10f4 | 206 | phy-mode = "qsgmii"; |
9dd7a57e MW |
207 | buffer-manager = <&bm>; |
208 | bm,pool-long = <1>; | |
467f54b2 GC |
209 | }; |
210 | ethernet@30000 { | |
211 | status = "okay"; | |
212 | phy = <&phy2>; | |
80fa10f4 | 213 | phy-mode = "qsgmii"; |
9dd7a57e MW |
214 | buffer-manager = <&bm>; |
215 | bm,pool-long = <2>; | |
467f54b2 GC |
216 | }; |
217 | ethernet@34000 { | |
218 | status = "okay"; | |
219 | phy = <&phy3>; | |
80fa10f4 | 220 | phy-mode = "qsgmii"; |
9dd7a57e MW |
221 | buffer-manager = <&bm>; |
222 | bm,pool-long = <3>; | |
467f54b2 | 223 | }; |
513a7917 | 224 | |
0e99b153 TP |
225 | /* Front-side USB slot */ |
226 | usb@50000 { | |
227 | status = "okay"; | |
228 | }; | |
229 | ||
230 | /* Back-side USB slot */ | |
231 | usb@51000 { | |
232 | status = "okay"; | |
233 | }; | |
234 | ||
467f54b2 | 235 | spi0: spi@10600 { |
513a7917 | 236 | status = "okay"; |
467f54b2 GC |
237 | |
238 | spi-flash@0 { | |
239 | #address-cells = <1>; | |
240 | #size-cells = <1>; | |
e9f3ed4a | 241 | compatible = "n25q128a13", "jedec,spi-nor"; |
467f54b2 GC |
242 | reg = <0>; /* Chip select 0 */ |
243 | spi-max-frequency = <108000000>; | |
244 | }; | |
513a7917 | 245 | }; |
2be2bc39 | 246 | |
9dd7a57e MW |
247 | bm@c0000 { |
248 | status = "okay"; | |
249 | }; | |
250 | ||
2be2bc39 EG |
251 | nand@d0000 { |
252 | status = "okay"; | |
253 | num-cs = <1>; | |
254 | marvell,nand-keep-config; | |
255 | marvell,nand-enable-arbiter; | |
256 | nand-on-flash-bbt; | |
257 | }; | |
513a7917 | 258 | }; |
9dd7a57e MW |
259 | |
260 | bm-bppi { | |
261 | status = "okay"; | |
262 | }; | |
568fc0a3 GC |
263 | }; |
264 | }; |