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568fc0a3 GC |
1 | /* |
2 | * Device Tree file for Marvell Armada XP development board | |
3 | * (DB-MV784MP-GP) | |
4 | * | |
5 | * Copyright (C) 2013 Marvell | |
6 | * | |
7 | * Lior Amsalem <alior@marvell.com> | |
8 | * Gregory CLEMENT <gregory.clement@free-electrons.com> | |
9 | * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> | |
10 | * | |
11 | * This file is licensed under the terms of the GNU General Public | |
12 | * License version 2. This program is licensed "as is" without any | |
13 | * warranty of any kind, whether express or implied. | |
14 | */ | |
15 | ||
16 | /dts-v1/; | |
17 | /include/ "armada-xp-mv78460.dtsi" | |
18 | ||
19 | / { | |
20 | model = "Marvell Armada XP Development Board DB-MV784MP-GP"; | |
21 | compatible = "marvell,axp-gp", "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp"; | |
22 | ||
23 | chosen { | |
24 | bootargs = "console=ttyS0,115200 earlyprintk"; | |
25 | }; | |
26 | ||
27 | memory { | |
28 | device_type = "memory"; | |
29 | ||
30 | /* | |
31 | * 4 GB of plug-in RAM modules by default but only 3GB | |
32 | * are visible, the amount of memory available can be | |
33 | * changed by the bootloader according the size of the | |
34 | * module actually plugged | |
35 | */ | |
36 | reg = <0x00000000 0xC0000000>; | |
37 | }; | |
38 | ||
39 | soc { | |
467f54b2 GC |
40 | internal-regs { |
41 | serial@12000 { | |
42 | clock-frequency = <250000000>; | |
43 | status = "okay"; | |
568fc0a3 | 44 | }; |
467f54b2 GC |
45 | serial@12100 { |
46 | clock-frequency = <250000000>; | |
47 | status = "okay"; | |
568fc0a3 | 48 | }; |
467f54b2 GC |
49 | serial@12200 { |
50 | clock-frequency = <250000000>; | |
51 | status = "okay"; | |
52 | }; | |
53 | serial@12300 { | |
54 | clock-frequency = <250000000>; | |
55 | status = "okay"; | |
568fc0a3 GC |
56 | }; |
57 | ||
467f54b2 GC |
58 | sata@a0000 { |
59 | nr-ports = <2>; | |
60 | status = "okay"; | |
568fc0a3 | 61 | }; |
568fc0a3 | 62 | |
467f54b2 GC |
63 | mdio { |
64 | phy0: ethernet-phy@0 { | |
65 | reg = <16>; | |
66 | }; | |
9dc3e346 | 67 | |
467f54b2 GC |
68 | phy1: ethernet-phy@1 { |
69 | reg = <17>; | |
70 | }; | |
9dc3e346 | 71 | |
467f54b2 GC |
72 | phy2: ethernet-phy@2 { |
73 | reg = <18>; | |
74 | }; | |
da8d1b38 | 75 | |
467f54b2 GC |
76 | phy3: ethernet-phy@3 { |
77 | reg = <19>; | |
78 | }; | |
da8d1b38 | 79 | }; |
513a7917 | 80 | |
467f54b2 GC |
81 | ethernet@70000 { |
82 | status = "okay"; | |
83 | phy = <&phy0>; | |
84 | phy-mode = "rgmii-id"; | |
85 | }; | |
86 | ethernet@74000 { | |
87 | status = "okay"; | |
88 | phy = <&phy1>; | |
89 | phy-mode = "rgmii-id"; | |
90 | }; | |
91 | ethernet@30000 { | |
92 | status = "okay"; | |
93 | phy = <&phy2>; | |
94 | phy-mode = "rgmii-id"; | |
95 | }; | |
96 | ethernet@34000 { | |
97 | status = "okay"; | |
98 | phy = <&phy3>; | |
99 | phy-mode = "rgmii-id"; | |
100 | }; | |
513a7917 | 101 | |
467f54b2 | 102 | spi0: spi@10600 { |
513a7917 | 103 | status = "okay"; |
467f54b2 GC |
104 | |
105 | spi-flash@0 { | |
106 | #address-cells = <1>; | |
107 | #size-cells = <1>; | |
108 | compatible = "n25q128a13"; | |
109 | reg = <0>; /* Chip select 0 */ | |
110 | spi-max-frequency = <108000000>; | |
111 | }; | |
513a7917 | 112 | }; |
467f54b2 GC |
113 | |
114 | devbus-bootcs@10400 { | |
513a7917 | 115 | status = "okay"; |
467f54b2 GC |
116 | ranges = <0 0xf0000000 0x1000000>; /* @addr 0xf000000, size 0x1000000 */ |
117 | ||
118 | /* Device Bus parameters are required */ | |
119 | ||
120 | /* Read parameters */ | |
121 | devbus,bus-width = <8>; | |
122 | devbus,turn-off-ps = <60000>; | |
123 | devbus,badr-skew-ps = <0>; | |
124 | devbus,acc-first-ps = <124000>; | |
125 | devbus,acc-next-ps = <248000>; | |
126 | devbus,rd-setup-ps = <0>; | |
127 | devbus,rd-hold-ps = <0>; | |
128 | ||
129 | /* Write parameters */ | |
130 | devbus,sync-enable = <0>; | |
131 | devbus,wr-high-ps = <60000>; | |
132 | devbus,wr-low-ps = <60000>; | |
133 | devbus,ale-wr-ps = <60000>; | |
134 | ||
135 | /* NOR 16 MiB */ | |
136 | nor@0 { | |
137 | compatible = "cfi-flash"; | |
138 | reg = <0 0x1000000>; | |
139 | bank-width = <2>; | |
140 | }; | |
513a7917 | 141 | }; |
467f54b2 GC |
142 | |
143 | pcie-controller { | |
513a7917 | 144 | status = "okay"; |
467f54b2 GC |
145 | |
146 | /* | |
147 | * The 3 slots are physically present as | |
148 | * standard PCIe slots on the board. | |
149 | */ | |
150 | pcie@1,0 { | |
151 | /* Port 0, Lane 0 */ | |
152 | status = "okay"; | |
153 | }; | |
154 | pcie@9,0 { | |
155 | /* Port 2, Lane 0 */ | |
156 | status = "okay"; | |
157 | }; | |
158 | pcie@10,0 { | |
159 | /* Port 3, Lane 0 */ | |
160 | status = "okay"; | |
161 | }; | |
513a7917 TP |
162 | }; |
163 | }; | |
568fc0a3 GC |
164 | }; |
165 | }; |