projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 568fc0a3 GC |
1 | /* |
| 2 | * Device Tree file for Marvell Armada XP development board | |
| 3 | * (DB-MV784MP-GP) | |
| 4 | * | |
| 5 | * Copyright (C) 2013 Marvell | |
| 6 | * | |
| 7 | * Lior Amsalem <alior@marvell.com> | |
| 8 | * Gregory CLEMENT <gregory.clement@free-electrons.com> | |
| 9 | * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> | |
| 10 | * | |
| 11 | * This file is licensed under the terms of the GNU General Public | |
| 12 | * License version 2. This program is licensed "as is" without any | |
| 13 | * warranty of any kind, whether express or implied. | |
| 14 | */ | |
| 15 | ||
| 16 | /dts-v1/; | |
| 38149887 | 17 | #include "armada-xp-mv78460.dtsi" |
| 568fc0a3 GC |
18 | |
| 19 | / { | |
| 20 | model = "Marvell Armada XP Development Board DB-MV784MP-GP"; | |
| 21 | compatible = "marvell,axp-gp", "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp"; | |
| 22 | ||
| 23 | chosen { | |
| 24 | bootargs = "console=ttyS0,115200 earlyprintk"; | |
| 25 | }; | |
| 26 | ||
| 27 | memory { | |
| 28 | device_type = "memory"; | |
| 568fc0a3 | 29 | /* |
| 74898364 GC |
30 | * 8 GB of plug-in RAM modules by default.The amount |
| 31 | * of memory available can be changed by the | |
| 32 | * bootloader according the size of the module | |
| 33 | * actually plugged. Only 7GB are usable because | |
| 34 | * addresses from 0xC0000000 to 0xffffffff are used by | |
| 35 | * the internal registers of the SoC. | |
| 568fc0a3 | 36 | */ |
| 74898364 GC |
37 | reg = <0x00000000 0x00000000 0x00000000 0xC0000000>, |
| 38 | <0x00000001 0x00000000 0x00000001 0x00000000>; | |
| 568fc0a3 GC |
39 | }; |
| 40 | ||
| 41 | soc { | |
| 0cd3754a | 42 | ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000 |
| de1af8d4 EG |
43 | MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000 |
| 44 | MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000>; | |
| 45 | ||
| 46 | devbus-bootcs { | |
| 47 | status = "okay"; | |
| 48 | ||
| 49 | /* Device Bus parameters are required */ | |
| 50 | ||
| 51 | /* Read parameters */ | |
| 52 | devbus,bus-width = <8>; | |
| 53 | devbus,turn-off-ps = <60000>; | |
| 54 | devbus,badr-skew-ps = <0>; | |
| 55 | devbus,acc-first-ps = <124000>; | |
| 56 | devbus,acc-next-ps = <248000>; | |
| 57 | devbus,rd-setup-ps = <0>; | |
| 58 | devbus,rd-hold-ps = <0>; | |
| 59 | ||
| 60 | /* Write parameters */ | |
| 61 | devbus,sync-enable = <0>; | |
| 62 | devbus,wr-high-ps = <60000>; | |
| 63 | devbus,wr-low-ps = <60000>; | |
| 64 | devbus,ale-wr-ps = <60000>; | |
| 65 | ||
| 66 | /* NOR 16 MiB */ | |
| 67 | nor@0 { | |
| 68 | compatible = "cfi-flash"; | |
| 69 | reg = <0 0x1000000>; | |
| 70 | bank-width = <2>; | |
| 71 | }; | |
| 72 | }; | |
| c6c003af | 73 | |
| 14fd8ed0 EG |
74 | pcie-controller { |
| 75 | status = "okay"; | |
| 76 | ||
| 77 | /* | |
| 78 | * The 3 slots are physically present as | |
| 79 | * standard PCIe slots on the board. | |
| 80 | */ | |
| 81 | pcie@1,0 { | |
| 82 | /* Port 0, Lane 0 */ | |
| 83 | status = "okay"; | |
| 84 | }; | |
| 85 | pcie@9,0 { | |
| 86 | /* Port 2, Lane 0 */ | |
| 87 | status = "okay"; | |
| 88 | }; | |
| 89 | pcie@10,0 { | |
| 90 | /* Port 3, Lane 0 */ | |
| 91 | status = "okay"; | |
| 92 | }; | |
| 93 | }; | |
| 94 | ||
| 467f54b2 GC |
95 | internal-regs { |
| 96 | serial@12000 { | |
| 97 | clock-frequency = <250000000>; | |
| 98 | status = "okay"; | |
| 568fc0a3 | 99 | }; |
| 467f54b2 GC |
100 | serial@12100 { |
| 101 | clock-frequency = <250000000>; | |
| 102 | status = "okay"; | |
| 568fc0a3 | 103 | }; |
| 467f54b2 GC |
104 | serial@12200 { |
| 105 | clock-frequency = <250000000>; | |
| 106 | status = "okay"; | |
| 107 | }; | |
| 108 | serial@12300 { | |
| 109 | clock-frequency = <250000000>; | |
| 110 | status = "okay"; | |
| 568fc0a3 GC |
111 | }; |
| 112 | ||
| 467f54b2 GC |
113 | sata@a0000 { |
| 114 | nr-ports = <2>; | |
| 115 | status = "okay"; | |
| 568fc0a3 | 116 | }; |
| 568fc0a3 | 117 | |
| 467f54b2 GC |
118 | mdio { |
| 119 | phy0: ethernet-phy@0 { | |
| 120 | reg = <16>; | |
| 121 | }; | |
| 9dc3e346 | 122 | |
| 467f54b2 GC |
123 | phy1: ethernet-phy@1 { |
| 124 | reg = <17>; | |
| 125 | }; | |
| 9dc3e346 | 126 | |
| 467f54b2 GC |
127 | phy2: ethernet-phy@2 { |
| 128 | reg = <18>; | |
| 129 | }; | |
| da8d1b38 | 130 | |
| 467f54b2 GC |
131 | phy3: ethernet-phy@3 { |
| 132 | reg = <19>; | |
| 133 | }; | |
| da8d1b38 | 134 | }; |
| 513a7917 | 135 | |
| 467f54b2 GC |
136 | ethernet@70000 { |
| 137 | status = "okay"; | |
| 138 | phy = <&phy0>; | |
| 139 | phy-mode = "rgmii-id"; | |
| 140 | }; | |
| 141 | ethernet@74000 { | |
| 142 | status = "okay"; | |
| 143 | phy = <&phy1>; | |
| 144 | phy-mode = "rgmii-id"; | |
| 145 | }; | |
| 146 | ethernet@30000 { | |
| 147 | status = "okay"; | |
| 148 | phy = <&phy2>; | |
| 149 | phy-mode = "rgmii-id"; | |
| 150 | }; | |
| 151 | ethernet@34000 { | |
| 152 | status = "okay"; | |
| 153 | phy = <&phy3>; | |
| 154 | phy-mode = "rgmii-id"; | |
| 155 | }; | |
| 513a7917 | 156 | |
| 0e99b153 TP |
157 | /* Front-side USB slot */ |
| 158 | usb@50000 { | |
| 159 | status = "okay"; | |
| 160 | }; | |
| 161 | ||
| 162 | /* Back-side USB slot */ | |
| 163 | usb@51000 { | |
| 164 | status = "okay"; | |
| 165 | }; | |
| 166 | ||
| 467f54b2 | 167 | spi0: spi@10600 { |
| 513a7917 | 168 | status = "okay"; |
| 467f54b2 GC |
169 | |
| 170 | spi-flash@0 { | |
| 171 | #address-cells = <1>; | |
| 172 | #size-cells = <1>; | |
| 173 | compatible = "n25q128a13"; | |
| 174 | reg = <0>; /* Chip select 0 */ | |
| 175 | spi-max-frequency = <108000000>; | |
| 176 | }; | |
| 513a7917 | 177 | }; |
| 513a7917 | 178 | }; |
| 568fc0a3 GC |
179 | }; |
| 180 | }; |