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568fc0a3 GC |
1 | /* |
2 | * Device Tree file for Marvell Armada XP development board | |
3 | * (DB-MV784MP-GP) | |
4 | * | |
5 | * Copyright (C) 2013 Marvell | |
6 | * | |
7 | * Lior Amsalem <alior@marvell.com> | |
8 | * Gregory CLEMENT <gregory.clement@free-electrons.com> | |
9 | * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> | |
10 | * | |
11 | * This file is licensed under the terms of the GNU General Public | |
12 | * License version 2. This program is licensed "as is" without any | |
13 | * warranty of any kind, whether express or implied. | |
14 | */ | |
15 | ||
16 | /dts-v1/; | |
38149887 | 17 | #include "armada-xp-mv78460.dtsi" |
568fc0a3 GC |
18 | |
19 | / { | |
20 | model = "Marvell Armada XP Development Board DB-MV784MP-GP"; | |
21 | compatible = "marvell,axp-gp", "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp"; | |
22 | ||
23 | chosen { | |
24 | bootargs = "console=ttyS0,115200 earlyprintk"; | |
25 | }; | |
26 | ||
27 | memory { | |
28 | device_type = "memory"; | |
568fc0a3 | 29 | /* |
74898364 GC |
30 | * 8 GB of plug-in RAM modules by default.The amount |
31 | * of memory available can be changed by the | |
32 | * bootloader according the size of the module | |
33 | * actually plugged. Only 7GB are usable because | |
34 | * addresses from 0xC0000000 to 0xffffffff are used by | |
35 | * the internal registers of the SoC. | |
568fc0a3 | 36 | */ |
74898364 GC |
37 | reg = <0x00000000 0x00000000 0x00000000 0xC0000000>, |
38 | <0x00000001 0x00000000 0x00000001 0x00000000>; | |
568fc0a3 GC |
39 | }; |
40 | ||
41 | soc { | |
0cd3754a | 42 | ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000 |
de1af8d4 EG |
43 | MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000 |
44 | MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000>; | |
45 | ||
46 | devbus-bootcs { | |
47 | status = "okay"; | |
48 | ||
49 | /* Device Bus parameters are required */ | |
50 | ||
51 | /* Read parameters */ | |
52 | devbus,bus-width = <8>; | |
53 | devbus,turn-off-ps = <60000>; | |
54 | devbus,badr-skew-ps = <0>; | |
55 | devbus,acc-first-ps = <124000>; | |
56 | devbus,acc-next-ps = <248000>; | |
57 | devbus,rd-setup-ps = <0>; | |
58 | devbus,rd-hold-ps = <0>; | |
59 | ||
60 | /* Write parameters */ | |
61 | devbus,sync-enable = <0>; | |
62 | devbus,wr-high-ps = <60000>; | |
63 | devbus,wr-low-ps = <60000>; | |
64 | devbus,ale-wr-ps = <60000>; | |
65 | ||
66 | /* NOR 16 MiB */ | |
67 | nor@0 { | |
68 | compatible = "cfi-flash"; | |
69 | reg = <0 0x1000000>; | |
70 | bank-width = <2>; | |
71 | }; | |
72 | }; | |
c6c003af | 73 | |
467f54b2 GC |
74 | internal-regs { |
75 | serial@12000 { | |
76 | clock-frequency = <250000000>; | |
77 | status = "okay"; | |
568fc0a3 | 78 | }; |
467f54b2 GC |
79 | serial@12100 { |
80 | clock-frequency = <250000000>; | |
81 | status = "okay"; | |
568fc0a3 | 82 | }; |
467f54b2 GC |
83 | serial@12200 { |
84 | clock-frequency = <250000000>; | |
85 | status = "okay"; | |
86 | }; | |
87 | serial@12300 { | |
88 | clock-frequency = <250000000>; | |
89 | status = "okay"; | |
568fc0a3 GC |
90 | }; |
91 | ||
467f54b2 GC |
92 | sata@a0000 { |
93 | nr-ports = <2>; | |
94 | status = "okay"; | |
568fc0a3 | 95 | }; |
568fc0a3 | 96 | |
467f54b2 GC |
97 | mdio { |
98 | phy0: ethernet-phy@0 { | |
99 | reg = <16>; | |
100 | }; | |
9dc3e346 | 101 | |
467f54b2 GC |
102 | phy1: ethernet-phy@1 { |
103 | reg = <17>; | |
104 | }; | |
9dc3e346 | 105 | |
467f54b2 GC |
106 | phy2: ethernet-phy@2 { |
107 | reg = <18>; | |
108 | }; | |
da8d1b38 | 109 | |
467f54b2 GC |
110 | phy3: ethernet-phy@3 { |
111 | reg = <19>; | |
112 | }; | |
da8d1b38 | 113 | }; |
513a7917 | 114 | |
467f54b2 GC |
115 | ethernet@70000 { |
116 | status = "okay"; | |
117 | phy = <&phy0>; | |
118 | phy-mode = "rgmii-id"; | |
119 | }; | |
120 | ethernet@74000 { | |
121 | status = "okay"; | |
122 | phy = <&phy1>; | |
123 | phy-mode = "rgmii-id"; | |
124 | }; | |
125 | ethernet@30000 { | |
126 | status = "okay"; | |
127 | phy = <&phy2>; | |
128 | phy-mode = "rgmii-id"; | |
129 | }; | |
130 | ethernet@34000 { | |
131 | status = "okay"; | |
132 | phy = <&phy3>; | |
133 | phy-mode = "rgmii-id"; | |
134 | }; | |
513a7917 | 135 | |
0e99b153 TP |
136 | /* Front-side USB slot */ |
137 | usb@50000 { | |
138 | status = "okay"; | |
139 | }; | |
140 | ||
141 | /* Back-side USB slot */ | |
142 | usb@51000 { | |
143 | status = "okay"; | |
144 | }; | |
145 | ||
467f54b2 | 146 | spi0: spi@10600 { |
513a7917 | 147 | status = "okay"; |
467f54b2 GC |
148 | |
149 | spi-flash@0 { | |
150 | #address-cells = <1>; | |
151 | #size-cells = <1>; | |
152 | compatible = "n25q128a13"; | |
153 | reg = <0>; /* Chip select 0 */ | |
154 | spi-max-frequency = <108000000>; | |
155 | }; | |
513a7917 | 156 | }; |
467f54b2 | 157 | |
467f54b2 | 158 | pcie-controller { |
513a7917 | 159 | status = "okay"; |
467f54b2 GC |
160 | |
161 | /* | |
162 | * The 3 slots are physically present as | |
163 | * standard PCIe slots on the board. | |
164 | */ | |
165 | pcie@1,0 { | |
166 | /* Port 0, Lane 0 */ | |
167 | status = "okay"; | |
168 | }; | |
169 | pcie@9,0 { | |
170 | /* Port 2, Lane 0 */ | |
171 | status = "okay"; | |
172 | }; | |
173 | pcie@10,0 { | |
174 | /* Port 3, Lane 0 */ | |
175 | status = "okay"; | |
176 | }; | |
513a7917 TP |
177 | }; |
178 | }; | |
568fc0a3 GC |
179 | }; |
180 | }; |