[deliverable/linux.git] / arch / arm / boot / dts / armada-xp-mv78230.dtsi

/*
 * Device Tree Include file for Marvell Armada XP family SoC
 *
 * Copyright (C) 2012 Marvell
 *
 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2.  This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 *
 * Contains definitions specific to the Armada XP MV78230 SoC that are not
 * common to all Armada XP SoCs.
 */

/include/ "armada-xp.dtsi"

/ {
	model = "Marvell Armada XP MV78230 SoC";
	compatible = "marvell,armadaxp-mv78230", "marvell,armadaxp", "marvell,armada-370-xp";

	aliases {
		gpio0 = &gpio0;
		gpio1 = &gpio1;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "marvell,sheeva-v7";
			reg = <0>;
			clocks = <&cpuclk 0>;
		};

		cpu@1 {
			device_type = "cpu";
			compatible = "marvell,sheeva-v7";
			reg = <1>;
			clocks = <&cpuclk 1>;
		};
	};

	soc {
		internal-regs {
			pinctrl {
				compatible = "marvell,mv78230-pinctrl";
				reg = <0x18000 0x38>;

				sdio_pins: sdio-pins {
					marvell,pins = "mpp30", "mpp31", "mpp32",
						       "mpp33", "mpp34", "mpp35";
					marvell,function = "sd0";
				};
			};

			gpio0: gpio@18100 {
				compatible = "marvell,orion-gpio";
				reg = <0x18100 0x40>;
				ngpios = <32>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupts-cells = <2>;
				interrupts = <82>, <83>, <84>, <85>;
			};

			gpio1: gpio@18140 {
				compatible = "marvell,orion-gpio";
				reg = <0x18140 0x40>;
				ngpios = <17>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupts-cells = <2>;
				interrupts = <87>, <88>, <89>;
			};

			/*
			 * MV78230 has 2 PCIe units Gen2.0: One unit can be
			 * configured as x4 or quad x1 lanes. One unit is
			 * x4/x1.
			 */
			pcie-controller {
				compatible = "marvell,armada-xp-pcie";
				status = "disabled";
				device_type = "pci";

#address-cells = <3>;
#size-cells = <2>;

				bus-range = <0x00 0xff>;

				ranges = <0x82000000 0 0x40000 0x40000 0 0x00002000   /* Port 0.0 registers */
					0x82000000 0 0x42000 0x42000 0 0x00002000   /* Port 2.0 registers */
					0x82000000 0 0x44000 0x44000 0 0x00002000   /* Port 0.1 registers */
					0x82000000 0 0x48000 0x48000 0 0x00002000   /* Port 0.2 registers */
					0x82000000 0 0x4c000 0x4c000 0 0x00002000   /* Port 0.3 registers */
					0x82000000 0 0xe0000000 0xe0000000 0 0x08000000   /* non-prefetchable memory */
					0x81000000 0 0	  0xe8000000 0 0x00100000>; /* downstream I/O */

				pcie@1,0 {
					device_type = "pci";
					assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
					reg = <0x0800 0 0 0 0>;
					#address-cells = <3>;
					#size-cells = <2>;
					#interrupt-cells = <1>;
					ranges;
					interrupt-map-mask = <0 0 0 0>;
					interrupt-map = <0 0 0 0 &mpic 58>;
					marvell,pcie-port = <0>;
					marvell,pcie-lane = <0>;
					clocks = <&gateclk 5>;
					status = "disabled";
				};

				pcie@2,0 {
					device_type = "pci";
					assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
					reg = <0x1000 0 0 0 0>;
					#address-cells = <3>;
					#size-cells = <2>;
					#interrupt-cells = <1>;
					ranges;
					interrupt-map-mask = <0 0 0 0>;
					interrupt-map = <0 0 0 0 &mpic 59>;
					marvell,pcie-port = <0>;
					marvell,pcie-lane = <1>;
					clocks = <&gateclk 6>;
					status = "disabled";
				};

				pcie@3,0 {
					device_type = "pci";
					assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
					reg = <0x1800 0 0 0 0>;
					#address-cells = <3>;
					#size-cells = <2>;
					#interrupt-cells = <1>;
					ranges;
					interrupt-map-mask = <0 0 0 0>;
					interrupt-map = <0 0 0 0 &mpic 60>;
					marvell,pcie-port = <0>;
					marvell,pcie-lane = <2>;
					clocks = <&gateclk 7>;
					status = "disabled";
				};

				pcie@4,0 {
					device_type = "pci";
					assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>;
					reg = <0x2000 0 0 0 0>;
					#address-cells = <3>;
					#size-cells = <2>;
					#interrupt-cells = <1>;
					ranges;
					interrupt-map-mask = <0 0 0 0>;
					interrupt-map = <0 0 0 0 &mpic 61>;
					marvell,pcie-port = <0>;
					marvell,pcie-lane = <3>;
					clocks = <&gateclk 8>;
					status = "disabled";
				};

				pcie@9,0 {
					device_type = "pci";
					assigned-addresses = <0x82000800 0 0x42000 0 0x2000>;
					reg = <0x4800 0 0 0 0>;
					#address-cells = <3>;
					#size-cells = <2>;
					#interrupt-cells = <1>;
					ranges;
					interrupt-map-mask = <0 0 0 0>;
					interrupt-map = <0 0 0 0 &mpic 99>;
					marvell,pcie-port = <2>;
					marvell,pcie-lane = <0>;
					clocks = <&gateclk 26>;
					status = "disabled";
				};
			};
		};
	};
};
Commit	Line	Data
f3b42b7c TP	1	/*
	2	* Device Tree Include file for Marvell Armada XP family SoC
	3	*
	4	* Copyright (C) 2012 Marvell
	5	*
	6	* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
	7	*
	8	* This file is licensed under the terms of the GNU General Public
	9	* License version 2. This program is licensed "as is" without any
	10	* warranty of any kind, whether express or implied.
	11	*
	12	* Contains definitions specific to the Armada XP MV78230 SoC that are not
	13	* common to all Armada XP SoCs.
	14	*/
	15
	16	/include/ "armada-xp.dtsi"
	17
	18	/ {
	19	model = "Marvell Armada XP MV78230 SoC";
	20	compatible = "marvell,armadaxp-mv78230", "marvell,armadaxp", "marvell,armada-370-xp";
	21
397d59f3 TP	22	aliases {
	23	gpio0 = &gpio0;
	24	gpio1 = &gpio1;
	25	};
	26
9d202783	27	cpus {
1b2529d0 TP	28	#address-cells = <1>;
1b2529d0 TP	29	#size-cells = <0>;
9d202783	30
1b2529d0 TP	31	cpu@0 {
	32	device_type = "cpu";
	33	compatible = "marvell,sheeva-v7";
	34	reg = <0>;
	35	clocks = <&cpuclk 0>;
	36	};
44cfae9a	37
1b2529d0 TP	38	cpu@1 {
	39	device_type = "cpu";
	40	compatible = "marvell,sheeva-v7";
	41	reg = <1>;
	42	clocks = <&cpuclk 1>;
	43	};
41be8dc1	44	};
9d202783	45
f3b42b7c	46	soc {
467f54b2 GC	47	internal-regs {
	48	pinctrl {
	49	compatible = "marvell,mv78230-pinctrl";
	50	reg = <0x18000 0x38>;
	51
	52	sdio_pins: sdio-pins {
	53	marvell,pins = "mpp30", "mpp31", "mpp32",
	54	"mpp33", "mpp34", "mpp35";
	55	marvell,function = "sd0";
	56	};
6d36e8e0	57	};
9d8f44f0	58
467f54b2 GC	59	gpio0: gpio@18100 {
	60	compatible = "marvell,orion-gpio";
	61	reg = <0x18100 0x40>;
	62	ngpios = <32>;
	63	gpio-controller;
	64	#gpio-cells = <2>;
	65	interrupt-controller;
	66	#interrupts-cells = <2>;
	67	interrupts = <82>, <83>, <84>, <85>;
9d8f44f0 TP	68	};
9d8f44f0 TP	69
467f54b2 GC	70	gpio1: gpio@18140 {
	71	compatible = "marvell,orion-gpio";
	72	reg = <0x18140 0x40>;
	73	ngpios = <17>;
	74	gpio-controller;
	75	#gpio-cells = <2>;
	76	interrupt-controller;
	77	#interrupts-cells = <2>;
	78	interrupts = <87>, <88>, <89>;
9d8f44f0 TP	79	};
9d8f44f0 TP	80
467f54b2 GC	81	/*
	82	* MV78230 has 2 PCIe units Gen2.0: One unit can be
	83	* configured as x4 or quad x1 lanes. One unit is
	84	* x4/x1.
	85	*/
	86	pcie-controller {
	87	compatible = "marvell,armada-xp-pcie";
9d8f44f0	88	status = "disabled";
9d8f44f0	89	device_type = "pci";
9d8f44f0	90
467f54b2 GC	91	#address-cells = <3>;
	92	#size-cells = <2>;
	93
	94	bus-range = <0x00 0xff>;
	95
	96	ranges = <0x82000000 0 0x40000 0x40000 0 0x00002000 /* Port 0.0 registers */
	97	0x82000000 0 0x42000 0x42000 0 0x00002000 /* Port 2.0 registers */
	98	0x82000000 0 0x44000 0x44000 0 0x00002000 /* Port 0.1 registers */
	99	0x82000000 0 0x48000 0x48000 0 0x00002000 /* Port 0.2 registers */
	100	0x82000000 0 0x4c000 0x4c000 0 0x00002000 /* Port 0.3 registers */
	101	0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */
	102	0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */
	103
	104	pcie@1,0 {
	105	device_type = "pci";
	106	assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
	107	reg = <0x0800 0 0 0 0>;
	108	#address-cells = <3>;
	109	#size-cells = <2>;
	110	#interrupt-cells = <1>;
	111	ranges;
	112	interrupt-map-mask = <0 0 0 0>;
	113	interrupt-map = <0 0 0 0 &mpic 58>;
	114	marvell,pcie-port = <0>;
	115	marvell,pcie-lane = <0>;
	116	clocks = <&gateclk 5>;
	117	status = "disabled";
	118	};
	119
	120	pcie@2,0 {
	121	device_type = "pci";
	122	assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
	123	reg = <0x1000 0 0 0 0>;
	124	#address-cells = <3>;
	125	#size-cells = <2>;
	126	#interrupt-cells = <1>;
	127	ranges;
	128	interrupt-map-mask = <0 0 0 0>;
	129	interrupt-map = <0 0 0 0 &mpic 59>;
	130	marvell,pcie-port = <0>;
	131	marvell,pcie-lane = <1>;
	132	clocks = <&gateclk 6>;
	133	status = "disabled";
	134	};
	135
	136	pcie@3,0 {
	137	device_type = "pci";
	138	assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
	139	reg = <0x1800 0 0 0 0>;
	140	#address-cells = <3>;
	141	#size-cells = <2>;
	142	#interrupt-cells = <1>;
	143	ranges;
	144	interrupt-map-mask = <0 0 0 0>;
	145	interrupt-map = <0 0 0 0 &mpic 60>;
	146	marvell,pcie-port = <0>;
	147	marvell,pcie-lane = <2>;
	148	clocks = <&gateclk 7>;
	149	status = "disabled";
	150	};
	151
	152	pcie@4,0 {
	153	device_type = "pci";
	154	assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>;
155	reg = <0x2000 0 0 0 0>;
156	#address-cells = <3>;
157	#size-cells = <2>;
158	#interrupt-cells = <1>;
159	ranges;
160	interrupt-map-mask = <0 0 0 0>;
161	interrupt-map = <0 0 0 0 &mpic 61>;
162	marvell,pcie-port = <0>;
163	marvell,pcie-lane = <3>;
164	clocks = <&gateclk 8>;
165	status = "disabled";
166	};
167
168	pcie@9,0 {
169	device_type = "pci";
170	assigned-addresses = <0x82000800 0 0x42000 0 0x2000>;
171	reg = <0x4800 0 0 0 0>;
172	#address-cells = <3>;
173	#size-cells = <2>;
174	#interrupt-cells = <1>;
175	ranges;
176	interrupt-map-mask = <0 0 0 0>;
177	interrupt-map = <0 0 0 0 &mpic 99>;
178	marvell,pcie-port = <2>;
179	marvell,pcie-lane = <0>;
180	clocks = <&gateclk 26>;
181	status = "disabled";
182	};
9d8f44f0 TP	183	};
9d8f44f0 TP	184	};
f3b42b7c TP	185	};
f3b42b7c TP	186	};