projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| f3b42b7c TP |
1 | /* |
| 2 | * Device Tree Include file for Marvell Armada XP family SoC | |
| 3 | * | |
| 4 | * Copyright (C) 2012 Marvell | |
| 5 | * | |
| 6 | * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> | |
| 7 | * | |
| 8 | * This file is licensed under the terms of the GNU General Public | |
| 9 | * License version 2. This program is licensed "as is" without any | |
| 10 | * warranty of any kind, whether express or implied. | |
| 11 | * | |
| 12 | * Contains definitions specific to the Armada XP MV78460 SoC that are not | |
| 13 | * common to all Armada XP SoCs. | |
| 14 | */ | |
| 15 | ||
| 16 | /include/ "armada-xp.dtsi" | |
| 17 | ||
| 18 | / { | |
| 19 | model = "Marvell Armada XP MV78460 SoC"; | |
| 20 | compatible = "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp"; | |
| 21 | ||
| 397d59f3 TP |
22 | aliases { |
| 23 | gpio0 = &gpio0; | |
| 24 | gpio1 = &gpio1; | |
| 25 | gpio2 = &gpio2; | |
| 26 | }; | |
| 27 | ||
| 9d202783 GC |
28 | |
| 29 | cpus { | |
| 30 | #address-cells = <1>; | |
| 31 | #size-cells = <0>; | |
| 32 | ||
| 33 | cpu@0 { | |
| 34 | device_type = "cpu"; | |
| 35 | compatible = "marvell,sheeva-v7"; | |
| 36 | reg = <0>; | |
| 37 | clocks = <&cpuclk 0>; | |
| 38 | }; | |
| 39 | ||
| 40 | cpu@1 { | |
| 41 | device_type = "cpu"; | |
| 42 | compatible = "marvell,sheeva-v7"; | |
| 43 | reg = <1>; | |
| 44 | clocks = <&cpuclk 1>; | |
| 45 | }; | |
| 46 | ||
| 47 | cpu@2 { | |
| 48 | device_type = "cpu"; | |
| 49 | compatible = "marvell,sheeva-v7"; | |
| 50 | reg = <2>; | |
| 51 | clocks = <&cpuclk 2>; | |
| 52 | }; | |
| 53 | ||
| 54 | cpu@3 { | |
| 55 | device_type = "cpu"; | |
| 56 | compatible = "marvell,sheeva-v7"; | |
| 57 | reg = <3>; | |
| 58 | clocks = <&cpuclk 3>; | |
| 59 | }; | |
| 60 | }; | |
| 61 | ||
| f3b42b7c TP |
62 | soc { |
| 63 | pinctrl { | |
| 64 | compatible = "marvell,mv78460-pinctrl"; | |
| 65 | reg = <0xd0018000 0x38>; | |
| 6d36e8e0 TP |
66 | |
| 67 | sdio_pins: sdio-pins { | |
| 68 | marvell,pins = "mpp30", "mpp31", "mpp32", | |
| 69 | "mpp33", "mpp34", "mpp35"; | |
| 70 | marvell,function = "sd0"; | |
| 71 | }; | |
| f3b42b7c | 72 | }; |
| 397d59f3 TP |
73 | |
| 74 | gpio0: gpio@d0018100 { | |
| 5f79c651 TP |
75 | compatible = "marvell,orion-gpio"; |
| 76 | reg = <0xd0018100 0x40>; | |
| 397d59f3 TP |
77 | ngpios = <32>; |
| 78 | gpio-controller; | |
| 79 | #gpio-cells = <2>; | |
| 80 | interrupt-controller; | |
| 81 | #interrupts-cells = <2>; | |
| 5f79c651 | 82 | interrupts = <82>, <83>, <84>, <85>; |
| 397d59f3 TP |
83 | }; |
| 84 | ||
| 85 | gpio1: gpio@d0018140 { | |
| 5f79c651 TP |
86 | compatible = "marvell,orion-gpio"; |
| 87 | reg = <0xd0018140 0x40>; | |
| 397d59f3 TP |
88 | ngpios = <32>; |
| 89 | gpio-controller; | |
| 90 | #gpio-cells = <2>; | |
| 91 | interrupt-controller; | |
| 92 | #interrupts-cells = <2>; | |
| 5f79c651 | 93 | interrupts = <87>, <88>, <89>, <90>; |
| 397d59f3 TP |
94 | }; |
| 95 | ||
| 96 | gpio2: gpio@d0018180 { | |
| 5f79c651 TP |
97 | compatible = "marvell,orion-gpio"; |
| 98 | reg = <0xd0018180 0x40>; | |
| 397d59f3 TP |
99 | ngpios = <3>; |
| 100 | gpio-controller; | |
| 101 | #gpio-cells = <2>; | |
| 102 | interrupt-controller; | |
| 103 | #interrupts-cells = <2>; | |
| 5f79c651 | 104 | interrupts = <91>; |
| 397d59f3 | 105 | }; |
| 77916519 TP |
106 | |
| 107 | ethernet@d0034000 { | |
| 108 | compatible = "marvell,armada-370-neta"; | |
| 109 | reg = <0xd0034000 0x2500>; | |
| 110 | interrupts = <14>; | |
| 111 | clocks = <&gateclk 1>; | |
| 112 | status = "disabled"; | |
| 113 | }; | |
| f3b42b7c TP |
114 | }; |
| 115 | }; |