[deliverable/linux.git] / arch / arm / boot / dts / armada-xp-mv78460.dtsi

/*
 * Device Tree Include file for Marvell Armada XP family SoC
 *
 * Copyright (C) 2012 Marvell
 *
 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2.  This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 *
 * Contains definitions specific to the Armada XP MV78460 SoC that are not
 * common to all Armada XP SoCs.
 */

/include/ "armada-xp.dtsi"

/ {
	model = "Marvell Armada XP MV78460 SoC";
	compatible = "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp";

	aliases {
		gpio0 = &gpio0;
		gpio1 = &gpio1;
		gpio2 = &gpio2;
	};


	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "marvell,sheeva-v7";
			reg = <0>;
			clocks = <&cpuclk 0>;
		};

		cpu@1 {
			device_type = "cpu";
			compatible = "marvell,sheeva-v7";
			reg = <1>;
			clocks = <&cpuclk 1>;
		};

		cpu@2 {
			device_type = "cpu";
			compatible = "marvell,sheeva-v7";
			reg = <2>;
			clocks = <&cpuclk 2>;
		};

		cpu@3 {
			device_type = "cpu";
			compatible = "marvell,sheeva-v7";
			reg = <3>;
			clocks = <&cpuclk 3>;
		};
	};

	soc {
		internal-regs {
			pinctrl {
				compatible = "marvell,mv78460-pinctrl";
				reg = <0x18000 0x38>;

				sdio_pins: sdio-pins {
					marvell,pins = "mpp30", "mpp31", "mpp32",
						       "mpp33", "mpp34", "mpp35";
					marvell,function = "sd0";
				};
			};

			gpio0: gpio@18100 {
				compatible = "marvell,orion-gpio";
				reg = <0x18100 0x40>;
				ngpios = <32>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupts-cells = <2>;
				interrupts = <82>, <83>, <84>, <85>;
			};

			gpio1: gpio@18140 {
				compatible = "marvell,orion-gpio";
				reg = <0x18140 0x40>;
				ngpios = <32>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupts-cells = <2>;
				interrupts = <87>, <88>, <89>, <90>;
			};

			gpio2: gpio@18180 {
				compatible = "marvell,orion-gpio";
				reg = <0x18180 0x40>;
				ngpios = <3>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupts-cells = <2>;
				interrupts = <91>;
			};

			ethernet@34000 {
				compatible = "marvell,armada-370-neta";
				reg = <0x34000 0x2500>;
				interrupts = <14>;
				clocks = <&gateclk 1>;
				status = "disabled";
			};

			/*
			 * MV78460 has 4 PCIe units Gen2.0: Two units can be
			 * configured as x4 or quad x1 lanes. Two units are
			 * x4/x1.
			 */
			pcie-controller {
				compatible = "marvell,armada-xp-pcie";
				status = "disabled";
				device_type = "pci";

				#address-cells = <3>;
				#size-cells = <2>;

				bus-range = <0x00 0xff>;

				ranges = <0x82000000 0 0x40000 0x40000 0 0x00002000   /* Port 0.0 registers */
					0x82000000 0 0x42000 0x42000 0 0x00002000   /* Port 2.0 registers */
					0x82000000 0 0x44000 0x44000 0 0x00002000   /* Port 0.1 registers */
					0x82000000 0 0x48000 0x48000 0 0x00002000   /* Port 0.2 registers */
					0x82000000 0 0x4c000 0x4c000 0 0x00002000   /* Port 0.3 registers */
					0x82000000 0 0x80000 0x80000 0 0x00002000   /* Port 1.0 registers */
					0x82000000 0 0x82000 0x82000 0 0x00002000   /* Port 3.0 registers */
					0x82000000 0 0x84000 0x84000 0 0x00002000   /* Port 1.1 registers */
					0x82000000 0 0x88000 0x88000 0 0x00002000   /* Port 1.2 registers */
					0x82000000 0 0x8c000 0x8c000 0 0x00002000   /* Port 1.3 registers */
					0x82000000 0 0xe0000000 0xe0000000 0 0x08000000   /* non-prefetchable memory */
					0x81000000 0 0	  0xe8000000 0 0x00100000>; /* downstream I/O */

				pcie@1,0 {
					device_type = "pci";
					assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
					reg = <0x0800 0 0 0 0>;
					#address-cells = <3>;
					#size-cells = <2>;
					#interrupt-cells = <1>;
					ranges;
					interrupt-map-mask = <0 0 0 0>;
					interrupt-map = <0 0 0 0 &mpic 58>;
					marvell,pcie-port = <0>;
					marvell,pcie-lane = <0>;
					clocks = <&gateclk 5>;
					status = "disabled";
				};

				pcie@2,0 {
					device_type = "pci";
					assigned-addresses = <0x82001000 0 0x44000 0 0x2000>;
					reg = <0x1000 0 0 0 0>;
					#address-cells = <3>;
					#size-cells = <2>;
					#interrupt-cells = <1>;
					ranges;
					interrupt-map-mask = <0 0 0 0>;
					interrupt-map = <0 0 0 0 &mpic 59>;
					marvell,pcie-port = <0>;
					marvell,pcie-lane = <1>;
					clocks = <&gateclk 6>;
					status = "disabled";
				};

				pcie@3,0 {
					device_type = "pci";
					assigned-addresses = <0x82001800 0 0x48000 0 0x2000>;
					reg = <0x1800 0 0 0 0>;
					#address-cells = <3>;
					#size-cells = <2>;
					#interrupt-cells = <1>;
					ranges;
					interrupt-map-mask = <0 0 0 0>;
					interrupt-map = <0 0 0 0 &mpic 60>;
					marvell,pcie-port = <0>;
					marvell,pcie-lane = <2>;
					clocks = <&gateclk 7>;
					status = "disabled";
				};

				pcie@4,0 {
					device_type = "pci";
					assigned-addresses = <0x82002000 0 0x4c000 0 0x2000>;
					reg = <0x2000 0 0 0 0>;
					#address-cells = <3>;
					#size-cells = <2>;
					#interrupt-cells = <1>;
					ranges;
					interrupt-map-mask = <0 0 0 0>;
					interrupt-map = <0 0 0 0 &mpic 61>;
					marvell,pcie-port = <0>;
					marvell,pcie-lane = <3>;
					clocks = <&gateclk 8>;
					status = "disabled";
				};

				pcie@5,0 {
					device_type = "pci";
					assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
					reg = <0x2800 0 0 0 0>;
					#address-cells = <3>;
					#size-cells = <2>;
					#interrupt-cells = <1>;
					ranges;
					interrupt-map-mask = <0 0 0 0>;
					interrupt-map = <0 0 0 0 &mpic 62>;
					marvell,pcie-port = <1>;
					marvell,pcie-lane = <0>;
					clocks = <&gateclk 9>;
					status = "disabled";
				};

				pcie@6,0 {
					device_type = "pci";
					assigned-addresses = <0x82003000 0 0x84000 0 0x2000>;
					reg = <0x3000 0 0 0 0>;
					#address-cells = <3>;
					#size-cells = <2>;
					#interrupt-cells = <1>;
					ranges;
					interrupt-map-mask = <0 0 0 0>;
					interrupt-map = <0 0 0 0 &mpic 63>;
					marvell,pcie-port = <1>;
					marvell,pcie-lane = <1>;
					clocks = <&gateclk 10>;
					status = "disabled";
				};

				pcie@7,0 {
					device_type = "pci";
					assigned-addresses = <0x82003800 0 0x88000 0 0x2000>;
					reg = <0x3800 0 0 0 0>;
					#address-cells = <3>;
					#size-cells = <2>;
					#interrupt-cells = <1>;
					ranges;
					interrupt-map-mask = <0 0 0 0>;
					interrupt-map = <0 0 0 0 &mpic 64>;
					marvell,pcie-port = <1>;
					marvell,pcie-lane = <2>;
					clocks = <&gateclk 11>;
					status = "disabled";
				};

				pcie@8,0 {
					device_type = "pci";
					assigned-addresses = <0x82004000 0 0x8c000 0 0x2000>;
					reg = <0x4000 0 0 0 0>;
					#address-cells = <3>;
					#size-cells = <2>;
					#interrupt-cells = <1>;
					ranges;
					interrupt-map-mask = <0 0 0 0>;
					interrupt-map = <0 0 0 0 &mpic 65>;
					marvell,pcie-port = <1>;
					marvell,pcie-lane = <3>;
					clocks = <&gateclk 12>;
					status = "disabled";
				};
				pcie@9,0 {
					device_type = "pci";
					assigned-addresses = <0x82004800 0 0x42000 0 0x2000>;
					reg = <0x4800 0 0 0 0>;
					#address-cells = <3>;
					#size-cells = <2>;
					#interrupt-cells = <1>;
					ranges;
					interrupt-map-mask = <0 0 0 0>;
					interrupt-map = <0 0 0 0 &mpic 99>;
					marvell,pcie-port = <2>;
					marvell,pcie-lane = <0>;
					clocks = <&gateclk 26>;
					status = "disabled";
				};

				pcie@10,0 {
					device_type = "pci";
					assigned-addresses = <0x82005000 0 0x82000 0 0x2000>;
					reg = <0x5000 0 0 0 0>;
					#address-cells = <3>;
					#size-cells = <2>;
					#interrupt-cells = <1>;
					ranges;
					interrupt-map-mask = <0 0 0 0>;
					interrupt-map = <0 0 0 0 &mpic 103>;
					marvell,pcie-port = <3>;
					marvell,pcie-lane = <0>;
					clocks = <&gateclk 27>;
					status = "disabled";
				};
			};
		};
	};
};
Commit	Line	Data
f3b42b7c TP	1	/*
	2	* Device Tree Include file for Marvell Armada XP family SoC
	3	*
	4	* Copyright (C) 2012 Marvell
	5	*
	6	* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
	7	*
	8	* This file is licensed under the terms of the GNU General Public
	9	* License version 2. This program is licensed "as is" without any
	10	* warranty of any kind, whether express or implied.
	11	*
	12	* Contains definitions specific to the Armada XP MV78460 SoC that are not
	13	* common to all Armada XP SoCs.
	14	*/
	15
	16	/include/ "armada-xp.dtsi"
	17
	18	/ {
	19	model = "Marvell Armada XP MV78460 SoC";
	20	compatible = "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp";
	21
397d59f3 TP	22	aliases {
	23	gpio0 = &gpio0;
	24	gpio1 = &gpio1;
	25	gpio2 = &gpio2;
	26	};
	27
9d202783 GC	28
9d202783 GC	29	cpus {
1b2529d0 TP	30	#address-cells = <1>;
1b2529d0 TP	31	#size-cells = <0>;
9d202783	32
1b2529d0 TP	33	cpu@0 {
	34	device_type = "cpu";
	35	compatible = "marvell,sheeva-v7";
	36	reg = <0>;
	37	clocks = <&cpuclk 0>;
	38	};
9d202783	39
1b2529d0 TP	40	cpu@1 {
	41	device_type = "cpu";
	42	compatible = "marvell,sheeva-v7";
	43	reg = <1>;
	44	clocks = <&cpuclk 1>;
	45	};
9d202783	46
1b2529d0 TP	47	cpu@2 {
	48	device_type = "cpu";
	49	compatible = "marvell,sheeva-v7";
	50	reg = <2>;
	51	clocks = <&cpuclk 2>;
	52	};
9d202783	53
1b2529d0 TP	54	cpu@3 {
	55	device_type = "cpu";
	56	compatible = "marvell,sheeva-v7";
	57	reg = <3>;
	58	clocks = <&cpuclk 3>;
	59	};
9d202783 GC	60	};
9d202783 GC	61
f3b42b7c	62	soc {
467f54b2 GC	63	internal-regs {
	64	pinctrl {
	65	compatible = "marvell,mv78460-pinctrl";
	66	reg = <0x18000 0x38>;
6d36e8e0	67
467f54b2 GC	68	sdio_pins: sdio-pins {
	69	marvell,pins = "mpp30", "mpp31", "mpp32",
	70	"mpp33", "mpp34", "mpp35";
	71	marvell,function = "sd0";
	72	};
6d36e8e0	73	};
397d59f3	74
467f54b2 GC	75	gpio0: gpio@18100 {
	76	compatible = "marvell,orion-gpio";
	77	reg = <0x18100 0x40>;
	78	ngpios = <32>;
	79	gpio-controller;
	80	#gpio-cells = <2>;
	81	interrupt-controller;
	82	#interrupts-cells = <2>;
	83	interrupts = <82>, <83>, <84>, <85>;
	84	};
397d59f3	85
467f54b2 GC	86	gpio1: gpio@18140 {
	87	compatible = "marvell,orion-gpio";
	88	reg = <0x18140 0x40>;
	89	ngpios = <32>;
	90	gpio-controller;
	91	#gpio-cells = <2>;
	92	interrupt-controller;
	93	#interrupts-cells = <2>;
	94	interrupts = <87>, <88>, <89>, <90>;
	95	};
397d59f3	96
467f54b2 GC	97	gpio2: gpio@18180 {
	98	compatible = "marvell,orion-gpio";
	99	reg = <0x18180 0x40>;
	100	ngpios = <3>;
	101	gpio-controller;
	102	#gpio-cells = <2>;
	103	interrupt-controller;
	104	#interrupts-cells = <2>;
	105	interrupts = <91>;
	106	};
77916519	107
467f54b2	108	ethernet@34000 {
77916519	109	compatible = "marvell,armada-370-neta";
82a68267	110	reg = <0x34000 0x2500>;
77916519 TP	111	interrupts = <14>;
	112	clocks = <&gateclk 1>;
	113	status = "disabled";
467f54b2	114	};
9d8f44f0	115
467f54b2 GC	116	/*
	117	* MV78460 has 4 PCIe units Gen2.0: Two units can be
	118	* configured as x4 or quad x1 lanes. Two units are
	119	* x4/x1.
	120	*/
	121	pcie-controller {
	122	compatible = "marvell,armada-xp-pcie";
	123	status = "disabled";
	124	device_type = "pci";
9d8f44f0	125
467f54b2 GC	126	#address-cells = <3>;
467f54b2 GC	127	#size-cells = <2>;
9d8f44f0	128
467f54b2	129	bus-range = <0x00 0xff>;
9d8f44f0	130
467f54b2 GC	131	ranges = <0x82000000 0 0x40000 0x40000 0 0x00002000 /* Port 0.0 registers */
	132	0x82000000 0 0x42000 0x42000 0 0x00002000 /* Port 2.0 registers */
	133	0x82000000 0 0x44000 0x44000 0 0x00002000 /* Port 0.1 registers */
	134	0x82000000 0 0x48000 0x48000 0 0x00002000 /* Port 0.2 registers */
	135	0x82000000 0 0x4c000 0x4c000 0 0x00002000 /* Port 0.3 registers */
	136	0x82000000 0 0x80000 0x80000 0 0x00002000 /* Port 1.0 registers */
	137	0x82000000 0 0x82000 0x82000 0 0x00002000 /* Port 3.0 registers */
	138	0x82000000 0 0x84000 0x84000 0 0x00002000 /* Port 1.1 registers */
	139	0x82000000 0 0x88000 0x88000 0 0x00002000 /* Port 1.2 registers */
	140	0x82000000 0 0x8c000 0x8c000 0 0x00002000 /* Port 1.3 registers */
	141	0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */
	142	0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */
9d8f44f0	143
467f54b2 GC	144	pcie@1,0 {
	145	device_type = "pci";
	146	assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
	147	reg = <0x0800 0 0 0 0>;
	148	#address-cells = <3>;
	149	#size-cells = <2>;
	150	#interrupt-cells = <1>;
	151	ranges;
	152	interrupt-map-mask = <0 0 0 0>;
	153	interrupt-map = <0 0 0 0 &mpic 58>;
	154	marvell,pcie-port = <0>;
	155	marvell,pcie-lane = <0>;
	156	clocks = <&gateclk 5>;
	157	status = "disabled";
	158	};
9d8f44f0	159
467f54b2 GC	160	pcie@2,0 {
	161	device_type = "pci";
	162	assigned-addresses = <0x82001000 0 0x44000 0 0x2000>;
	163	reg = <0x1000 0 0 0 0>;
	164	#address-cells = <3>;
	165	#size-cells = <2>;
	166	#interrupt-cells = <1>;
	167	ranges;
	168	interrupt-map-mask = <0 0 0 0>;
	169	interrupt-map = <0 0 0 0 &mpic 59>;
	170	marvell,pcie-port = <0>;
	171	marvell,pcie-lane = <1>;
	172	clocks = <&gateclk 6>;
	173	status = "disabled";
	174	};
9d8f44f0	175
467f54b2 GC	176	pcie@3,0 {
	177	device_type = "pci";
	178	assigned-addresses = <0x82001800 0 0x48000 0 0x2000>;
	179	reg = <0x1800 0 0 0 0>;
	180	#address-cells = <3>;
	181	#size-cells = <2>;
	182	#interrupt-cells = <1>;
	183	ranges;
	184	interrupt-map-mask = <0 0 0 0>;
	185	interrupt-map = <0 0 0 0 &mpic 60>;
	186	marvell,pcie-port = <0>;
	187	marvell,pcie-lane = <2>;
	188	clocks = <&gateclk 7>;
	189	status = "disabled";
	190	};
9d8f44f0	191
467f54b2 GC	192	pcie@4,0 {
	193	device_type = "pci";
	194	assigned-addresses = <0x82002000 0 0x4c000 0 0x2000>;
	195	reg = <0x2000 0 0 0 0>;
	196	#address-cells = <3>;
	197	#size-cells = <2>;
	198	#interrupt-cells = <1>;
	199	ranges;
	200	interrupt-map-mask = <0 0 0 0>;
	201	interrupt-map = <0 0 0 0 &mpic 61>;
	202	marvell,pcie-port = <0>;
	203	marvell,pcie-lane = <3>;
	204	clocks = <&gateclk 8>;
	205	status = "disabled";
	206	};
9d8f44f0	207
467f54b2 GC	208	pcie@5,0 {
	209	device_type = "pci";
	210	assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
	211	reg = <0x2800 0 0 0 0>;
	212	#address-cells = <3>;
	213	#size-cells = <2>;
	214	#interrupt-cells = <1>;
	215	ranges;
	216	interrupt-map-mask = <0 0 0 0>;
	217	interrupt-map = <0 0 0 0 &mpic 62>;
	218	marvell,pcie-port = <1>;
	219	marvell,pcie-lane = <0>;
	220	clocks = <&gateclk 9>;
	221	status = "disabled";
	222	};
9d8f44f0	223
467f54b2 GC	224	pcie@6,0 {
	225	device_type = "pci";
	226	assigned-addresses = <0x82003000 0 0x84000 0 0x2000>;
	227	reg = <0x3000 0 0 0 0>;
	228	#address-cells = <3>;
	229	#size-cells = <2>;
	230	#interrupt-cells = <1>;
	231	ranges;
	232	interrupt-map-mask = <0 0 0 0>;
	233	interrupt-map = <0 0 0 0 &mpic 63>;
	234	marvell,pcie-port = <1>;
	235	marvell,pcie-lane = <1>;
	236	clocks = <&gateclk 10>;
	237	status = "disabled";
	238	};
9d8f44f0	239
467f54b2 GC	240	pcie@7,0 {
	241	device_type = "pci";
	242	assigned-addresses = <0x82003800 0 0x88000 0 0x2000>;
	243	reg = <0x3800 0 0 0 0>;
	244	#address-cells = <3>;
	245	#size-cells = <2>;
	246	#interrupt-cells = <1>;
	247	ranges;
	248	interrupt-map-mask = <0 0 0 0>;
	249	interrupt-map = <0 0 0 0 &mpic 64>;
	250	marvell,pcie-port = <1>;
	251	marvell,pcie-lane = <2>;
	252	clocks = <&gateclk 11>;
	253	status = "disabled";
	254	};
9d8f44f0	255
467f54b2 GC	256	pcie@8,0 {
	257	device_type = "pci";
	258	assigned-addresses = <0x82004000 0 0x8c000 0 0x2000>;
	259	reg = <0x4000 0 0 0 0>;
	260	#address-cells = <3>;
	261	#size-cells = <2>;
	262	#interrupt-cells = <1>;
	263	ranges;
	264	interrupt-map-mask = <0 0 0 0>;
	265	interrupt-map = <0 0 0 0 &mpic 65>;
	266	marvell,pcie-port = <1>;
	267	marvell,pcie-lane = <3>;
	268	clocks = <&gateclk 12>;
	269	status = "disabled";
	270	};
	271	pcie@9,0 {
	272	device_type = "pci";
	273	assigned-addresses = <0x82004800 0 0x42000 0 0x2000>;
	274	reg = <0x4800 0 0 0 0>;
	275	#address-cells = <3>;
	276	#size-cells = <2>;
	277	#interrupt-cells = <1>;
	278	ranges;
	279	interrupt-map-mask = <0 0 0 0>;
	280	interrupt-map = <0 0 0 0 &mpic 99>;
	281	marvell,pcie-port = <2>;
	282	marvell,pcie-lane = <0>;
	283	clocks = <&gateclk 26>;
	284	status = "disabled";
	285	};
9d8f44f0	286
467f54b2 GC	287	pcie@10,0 {
	288	device_type = "pci";
	289	assigned-addresses = <0x82005000 0 0x82000 0 0x2000>;
	290	reg = <0x5000 0 0 0 0>;
	291	#address-cells = <3>;
	292	#size-cells = <2>;
	293	#interrupt-cells = <1>;
	294	ranges;
	295	interrupt-map-mask = <0 0 0 0>;
	296	interrupt-map = <0 0 0 0 &mpic 103>;
	297	marvell,pcie-port = <3>;
	298	marvell,pcie-lane = <0>;
	299	clocks = <&gateclk 27>;
	300	status = "disabled";
	301	};
9d8f44f0 TP	302	};
9d8f44f0 TP	303	};
f3b42b7c	304	};
1b2529d0	305	};