projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 9ae6f740 TP |
1 | /* |
| 2 | * Device Tree Include file for Marvell Armada XP family SoC | |
| 3 | * | |
| 4 | * Copyright (C) 2012 Marvell | |
| 5 | * | |
| 6 | * Lior Amsalem <alior@marvell.com> | |
| 7 | * Gregory CLEMENT <gregory.clement@free-electrons.com> | |
| 8 | * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> | |
| 9 | * Ben Dooks <ben.dooks@codethink.co.uk> | |
| 10 | * | |
| 11 | * This file is licensed under the terms of the GNU General Public | |
| 12 | * License version 2. This program is licensed "as is" without any | |
| 13 | * warranty of any kind, whether express or implied. | |
| 14 | * | |
| 10b683cb | 15 | * Contains definitions specific to the Armada XP SoC that are not |
| 9ae6f740 TP |
16 | * common to all Armada SoCs. |
| 17 | */ | |
| 18 | ||
| 19 | /include/ "armada-370-xp.dtsi" | |
| 20 | ||
| 21 | / { | |
| 22 | model = "Marvell Armada XP family SoC"; | |
| 23 | compatible = "marvell,armadaxp", "marvell,armada-370-xp"; | |
| 24 | ||
| b18ea4dc | 25 | soc { |
| 467f54b2 GC |
26 | internal-regs { |
| 27 | L2: l2-cache { | |
| 28 | compatible = "marvell,aurora-system-cache"; | |
| 29 | reg = <0x08000 0x1000>; | |
| 30 | cache-id-part = <0x100>; | |
| 31 | wt-override; | |
| 32 | }; | |
| 2f96fbb7 | 33 | |
| 467f54b2 GC |
34 | mpic: interrupt-controller@20000 { |
| 35 | reg = <0x20a00 0x2d0>, <0x21070 0x58>; | |
| 36 | }; | |
| 9ae6f740 | 37 | |
| 467f54b2 GC |
38 | armada-370-xp-pmsu@22000 { |
| 39 | compatible = "marvell,armada-370-xp-pmsu"; | |
| 40 | reg = <0x22100 0x430>, <0x20800 0x20>; | |
| 41 | }; | |
| 9ae6f740 | 42 | |
| 467f54b2 | 43 | serial@12200 { |
| b24212fb | 44 | compatible = "snps,dw-apb-uart"; |
| 82a68267 | 45 | reg = <0x12200 0x100>; |
| 9ae6f740 TP |
46 | reg-shift = <2>; |
| 47 | interrupts = <43>; | |
| e366154f | 48 | reg-io-width = <1>; |
| 9ae6f740 | 49 | status = "disabled"; |
| 467f54b2 GC |
50 | }; |
| 51 | serial@12300 { | |
| b24212fb | 52 | compatible = "snps,dw-apb-uart"; |
| 82a68267 | 53 | reg = <0x12300 0x100>; |
| 9ae6f740 TP |
54 | reg-shift = <2>; |
| 55 | interrupts = <44>; | |
| e366154f | 56 | reg-io-width = <1>; |
| 9ae6f740 | 57 | status = "disabled"; |
| 467f54b2 | 58 | }; |
| 9ae6f740 | 59 | |
| 467f54b2 | 60 | timer@20300 { |
| 9ae6f740 | 61 | marvell,timer-25Mhz; |
| 467f54b2 | 62 | }; |
| 9ae6f740 | 63 | |
| 467f54b2 GC |
64 | coreclk: mvebu-sar@18230 { |
| 65 | compatible = "marvell,armada-xp-core-clock"; | |
| 66 | reg = <0x18230 0x08>; | |
| 67 | #clock-cells = <1>; | |
| 68 | }; | |
| 9d202783 | 69 | |
| 467f54b2 GC |
70 | cpuclk: clock-complex@18700 { |
| 71 | #clock-cells = <1>; | |
| 72 | compatible = "marvell,armada-xp-cpu-clock"; | |
| 73 | reg = <0x18700 0xA0>; | |
| 74 | clocks = <&coreclk 1>; | |
| 75 | }; | |
| 9d202783 | 76 | |
| 467f54b2 GC |
77 | gateclk: clock-gating-control@18220 { |
| 78 | compatible = "marvell,armada-xp-gating-clock"; | |
| 79 | reg = <0x18220 0x4>; | |
| 80 | clocks = <&coreclk 0>; | |
| 81 | #clock-cells = <1>; | |
| 82 | }; | |
| 9d202783 | 83 | |
| 467f54b2 | 84 | system-controller@18200 { |
| 9ae6f740 | 85 | compatible = "marvell,armada-370-xp-system-controller"; |
| 82a68267 | 86 | reg = <0x18200 0x500>; |
| 467f54b2 | 87 | }; |
| 323c1010 | 88 | |
| 467f54b2 | 89 | ethernet@30000 { |
| 323c1010 | 90 | compatible = "marvell,armada-370-neta"; |
| 82a68267 | 91 | reg = <0x30000 0x2500>; |
| 323c1010 | 92 | interrupts = <12>; |
| 4aa935a2 | 93 | clocks = <&gateclk 2>; |
| 323c1010 | 94 | status = "disabled"; |
| a1d53dab | 95 | }; |
| a1d53dab | 96 | |
| 467f54b2 GC |
97 | xor@60900 { |
| 98 | compatible = "marvell,orion-xor"; | |
| 99 | reg = <0x60900 0x100 | |
| 100 | 0x60b00 0x100>; | |
| 101 | clocks = <&gateclk 22>; | |
| 102 | status = "okay"; | |
| 103 | ||
| 104 | xor10 { | |
| 105 | interrupts = <51>; | |
| 106 | dmacap,memcpy; | |
| 107 | dmacap,xor; | |
| 108 | }; | |
| 109 | xor11 { | |
| 110 | interrupts = <52>; | |
| 111 | dmacap,memcpy; | |
| 112 | dmacap,xor; | |
| 113 | dmacap,memset; | |
| 114 | }; | |
| a1d53dab | 115 | }; |
| 467f54b2 GC |
116 | |
| 117 | xor@f0900 { | |
| 118 | compatible = "marvell,orion-xor"; | |
| 119 | reg = <0xF0900 0x100 | |
| 120 | 0xF0B00 0x100>; | |
| 121 | clocks = <&gateclk 28>; | |
| 122 | status = "okay"; | |
| 123 | ||
| 124 | xor00 { | |
| 125 | interrupts = <94>; | |
| 126 | dmacap,memcpy; | |
| 127 | dmacap,xor; | |
| 128 | }; | |
| 129 | xor01 { | |
| 130 | interrupts = <95>; | |
| 131 | dmacap,memcpy; | |
| 132 | dmacap,xor; | |
| 133 | dmacap,memset; | |
| 134 | }; | |
| a1d53dab | 135 | }; |
| b2bb806f | 136 | |
| 467f54b2 GC |
137 | usb@50000 { |
| 138 | clocks = <&gateclk 18>; | |
| 139 | }; | |
| b2bb806f | 140 | |
| 467f54b2 GC |
141 | usb@51000 { |
| 142 | clocks = <&gateclk 19>; | |
| 143 | }; | |
| b2bb806f | 144 | |
| 467f54b2 GC |
145 | usb@52000 { |
| 146 | compatible = "marvell,orion-ehci"; | |
| 147 | reg = <0x52000 0x500>; | |
| 148 | interrupts = <47>; | |
| 149 | clocks = <&gateclk 20>; | |
| 150 | status = "disabled"; | |
| 151 | }; | |
| b2bb806f | 152 | |
| 467f54b2 GC |
153 | thermal@182b0 { |
| 154 | compatible = "marvell,armadaxp-thermal"; | |
| 155 | reg = <0x182b0 0x4 | |
| 156 | 0x184d0 0x4>; | |
| 157 | status = "okay"; | |
| 158 | }; | |
| 693a56ea | 159 | }; |
| 9ae6f740 TP |
160 | }; |
| 161 | }; |