[deliverable/linux.git] / arch / arm / boot / dts / armada-xp.dtsi

/*
 * Device Tree Include file for Marvell Armada XP family SoC
 *
 * Copyright (C) 2012 Marvell
 *
 * Lior Amsalem <alior@marvell.com>
 * Gregory CLEMENT <gregory.clement@free-electrons.com>
 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
 * Ben Dooks <ben.dooks@codethink.co.uk>
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 *  a) This file is free software; you can redistribute it and/or
 *     modify it under the terms of the GNU General Public License as
 *     published by the Free Software Foundation; either version 2 of the
 *     License, or (at your option) any later version.
 *
 *     This file is distributed in the hope that it will be useful
 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *     GNU General Public License for more details.
 *
 * Or, alternatively
 *
 *  b) Permission is hereby granted, free of charge, to any person
 *     obtaining a copy of this software and associated documentation
 *     files (the "Software"), to deal in the Software without
 *     restriction, including without limitation the rights to use
 *     copy, modify, merge, publish, distribute, sublicense, and/or
 *     sell copies of the Software, and to permit persons to whom the
 *     Software is furnished to do so, subject to the following
 *     conditions:
 *
 *     The above copyright notice and this permission notice shall be
 *     included in all copies or substantial portions of the Software.
 *
 *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 *     OTHER DEALINGS IN THE SOFTWARE.
 *
 * Contains definitions specific to the Armada XP SoC that are not
 * common to all Armada SoCs.
 */

#include "armada-370-xp.dtsi"

/ {
	model = "Marvell Armada XP family SoC";
	compatible = "marvell,armadaxp", "marvell,armada-370-xp";

	aliases {
		serial2 = &uart2;
		serial3 = &uart3;
	};

	soc {
		compatible = "marvell,armadaxp-mbus", "simple-bus";

		bootrom {
			compatible = "marvell,bootrom";
			reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
		};

		internal-regs {
			sdramc@1400 {
				compatible = "marvell,armada-xp-sdram-controller";
				reg = <0x1400 0x500>;
			};

			L2: l2-cache {
				compatible = "marvell,aurora-system-cache";
				reg = <0x08000 0x1000>;
				cache-id-part = <0x100>;
				cache-level = <2>;
				cache-unified;
				wt-override;
			};

			spi0: spi@10600 {
				pinctrl-0 = <&spi0_pins>;
				pinctrl-names = "default";
			};

			i2c0: i2c@11000 {
				compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
				reg = <0x11000 0x100>;
			};

			i2c1: i2c@11100 {
				compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
				reg = <0x11100 0x100>;
			};

			uart2: serial@12200 {
				compatible = "snps,dw-apb-uart";
				pinctrl-0 = <&uart2_pins>;
				pinctrl-names = "default";
				reg = <0x12200 0x100>;
				reg-shift = <2>;
				interrupts = <43>;
				reg-io-width = <1>;
				clocks = <&coreclk 0>;
				status = "disabled";
			};

			uart3: serial@12300 {
				compatible = "snps,dw-apb-uart";
				pinctrl-0 = <&uart3_pins>;
				pinctrl-names = "default";
				reg = <0x12300 0x100>;
				reg-shift = <2>;
				interrupts = <44>;
				reg-io-width = <1>;
				clocks = <&coreclk 0>;
				status = "disabled";
			};

			system-controller@18200 {
				compatible = "marvell,armada-370-xp-system-controller";
				reg = <0x18200 0x500>;
			};

			gateclk: clock-gating-control@18220 {
				compatible = "marvell,armada-xp-gating-clock";
				reg = <0x18220 0x4>;
				clocks = <&coreclk 0>;
				#clock-cells = <1>;
			};

			coreclk: mvebu-sar@18230 {
				compatible = "marvell,armada-xp-core-clock";
				reg = <0x18230 0x08>;
				#clock-cells = <1>;
			};

			thermal@182b0 {
				compatible = "marvell,armadaxp-thermal";
				reg = <0x182b0 0x4
					0x184d0 0x4>;
				status = "okay";
			};

			cpuclk: clock-complex@18700 {
				#clock-cells = <1>;
				compatible = "marvell,armada-xp-cpu-clock";
				reg = <0x18700 0x24>, <0x1c054 0x10>;
				clocks = <&coreclk 1>;
			};

			interrupt-controller@20a00 {
			      reg = <0x20a00 0x2d0>, <0x21070 0x58>;
			};

			timer@20300 {
				compatible = "marvell,armada-xp-timer";
				clocks = <&coreclk 2>, <&refclk>;
				clock-names = "nbclk", "fixed";
			};

			watchdog@20300 {
				compatible = "marvell,armada-xp-wdt";
				clocks = <&coreclk 2>, <&refclk>;
				clock-names = "nbclk", "fixed";
			};

			cpurst@20800 {
				compatible = "marvell,armada-370-cpu-reset";
				reg = <0x20800 0x20>;
			};

			eth2: ethernet@30000 {
				compatible = "marvell,armada-xp-neta";
				reg = <0x30000 0x4000>;
				interrupts = <12>;
				clocks = <&gateclk 2>;
				status = "disabled";
			};

			usb@50000 {
				clocks = <&gateclk 18>;
			};

			usb@51000 {
				clocks = <&gateclk 19>;
			};

			usb@52000 {
				compatible = "marvell,orion-ehci";
				reg = <0x52000 0x500>;
				interrupts = <47>;
				clocks = <&gateclk 20>;
				status = "disabled";
			};

			xor@60900 {
				compatible = "marvell,orion-xor";
				reg = <0x60900 0x100
				       0x60b00 0x100>;
				clocks = <&gateclk 22>;
				status = "okay";

				xor10 {
					interrupts = <51>;
					dmacap,memcpy;
					dmacap,xor;
				};
				xor11 {
					interrupts = <52>;
					dmacap,memcpy;
					dmacap,xor;
					dmacap,memset;
				};
			};

			ethernet@70000 {
				compatible = "marvell,armada-xp-neta";
			};

			ethernet@74000 {
				compatible = "marvell,armada-xp-neta";
			};

			xor@f0900 {
				compatible = "marvell,orion-xor";
				reg = <0xF0900 0x100
				       0xF0B00 0x100>;
				clocks = <&gateclk 28>;
				status = "okay";

				xor00 {
					interrupts = <94>;
					dmacap,memcpy;
					dmacap,xor;
				};
				xor01 {
					interrupts = <95>;
					dmacap,memcpy;
					dmacap,xor;
					dmacap,memset;
				};
			};
		};
	};

	clocks {
		/* 25 MHz reference crystal */
		refclk: oscillator {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <25000000>;
		};
	};
};

&pinctrl {
	ge0_gmii_pins: ge0-gmii-pins {
		marvell,pins =
		     "mpp0",  "mpp1",  "mpp2",  "mpp3",
		     "mpp4",  "mpp5",  "mpp6",  "mpp7",
		     "mpp8",  "mpp9",  "mpp10", "mpp11",
		     "mpp12", "mpp13", "mpp14", "mpp15",
		     "mpp16", "mpp17", "mpp18", "mpp19",
		     "mpp20", "mpp21", "mpp22", "mpp23";
		marvell,function = "ge0";
	};

	ge0_rgmii_pins: ge0-rgmii-pins {
		marvell,pins =
		     "mpp0", "mpp1", "mpp2", "mpp3",
		     "mpp4", "mpp5", "mpp6", "mpp7",
		     "mpp8", "mpp9", "mpp10", "mpp11";
		marvell,function = "ge0";
	};

	ge1_rgmii_pins: ge1-rgmii-pins {
		marvell,pins =
		     "mpp12", "mpp13", "mpp14", "mpp15",
		     "mpp16", "mpp17", "mpp18", "mpp19",
		     "mpp20", "mpp21", "mpp22", "mpp23";
		marvell,function = "ge1";
	};

	sdio_pins: sdio-pins {
		marvell,pins = "mpp30", "mpp31", "mpp32",
			       "mpp33", "mpp34", "mpp35";
		marvell,function = "sd0";
	};

	spi0_pins: spi0-pins {
		marvell,pins = "mpp36", "mpp37",
			       "mpp38", "mpp39";
		marvell,function = "spi";
	};

	uart2_pins: uart2-pins {
		marvell,pins = "mpp42", "mpp43";
		marvell,function = "uart2";
	};

	uart3_pins: uart3-pins {
		marvell,pins = "mpp44", "mpp45";
		marvell,function = "uart3";
	};
};
Commit	Line	Data
9ae6f740 TP	1	/*
	2	* Device Tree Include file for Marvell Armada XP family SoC
	3	*
	4	* Copyright (C) 2012 Marvell
	5	*
	6	* Lior Amsalem <alior@marvell.com>
	7	* Gregory CLEMENT <gregory.clement@free-electrons.com>
	8	* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
	9	* Ben Dooks <ben.dooks@codethink.co.uk>
	10	*
ee2ff969 GC	11	* This file is dual-licensed: you can use it either under the terms
	12	* of the GPL or the X11 license, at your option. Note that this dual
	13	* licensing only applies to this file, and not this project as a
	14	* whole.
	15	*
	16	* a) This file is free software; you can redistribute it and/or
	17	* modify it under the terms of the GNU General Public License as
	18	* published by the Free Software Foundation; either version 2 of the
	19	* License, or (at your option) any later version.
	20	*
	21	* This file is distributed in the hope that it will be useful
	22	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	23	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	24	* GNU General Public License for more details.
	25	*
	26	* Or, alternatively
	27	*
	28	* b) Permission is hereby granted, free of charge, to any person
	29	* obtaining a copy of this software and associated documentation
	30	* files (the "Software"), to deal in the Software without
	31	* restriction, including without limitation the rights to use
	32	* copy, modify, merge, publish, distribute, sublicense, and/or
	33	* sell copies of the Software, and to permit persons to whom the
	34	* Software is furnished to do so, subject to the following
	35	* conditions:
	36	*
	37	* The above copyright notice and this permission notice shall be
	38	* included in all copies or substantial portions of the Software.
	39	*
	40	* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
	41	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
	42	* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	43	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
	44	* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
	45	* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	46	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	47	* OTHER DEALINGS IN THE SOFTWARE.
9ae6f740	48	*
10b683cb	49	* Contains definitions specific to the Armada XP SoC that are not
9ae6f740 TP	50	* common to all Armada SoCs.
	51	*/
	52
38149887	53	#include "armada-370-xp.dtsi"
9ae6f740 TP	54
	55	/ {
	56	model = "Marvell Armada XP family SoC";
	57	compatible = "marvell,armadaxp", "marvell,armada-370-xp";
	58
be5a9389	59	aliases {
bf6acf16 TP	60	serial2 = &uart2;
bf6acf16 TP	61	serial3 = &uart3;
be5a9389 WT	62	};
be5a9389 WT	63
b18ea4dc	64	soc {
5e12a613 EG	65	compatible = "marvell,armadaxp-mbus", "simple-bus";
5e12a613 EG	66
0cd3754a EG	67	bootrom {
	68	compatible = "marvell,bootrom";
	69	reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
	70	};
	71
467f54b2	72	internal-regs {
6e6db2be TP	73	sdramc@1400 {
	74	compatible = "marvell,armada-xp-sdram-controller";
	75	reg = <0x1400 0x500>;
	76	};
	77
467f54b2 GC	78	L2: l2-cache {
	79	compatible = "marvell,aurora-system-cache";
	80	reg = <0x08000 0x1000>;
	81	cache-id-part = <0x100>;
292a3546	82	cache-level = <2>;
a9ce1afb	83	cache-unified;
467f54b2 GC	84	wt-override;
467f54b2 GC	85	};
2f96fbb7	86
547c653b AE	87	spi0: spi@10600 {
	88	pinctrl-0 = <&spi0_pins>;
	89	pinctrl-names = "default";
	90	};
	91
a095b1c7 JC	92	i2c0: i2c@11000 {
	93	compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
	94	reg = <0x11000 0x100>;
467f54b2	95	};
9ae6f740	96
a095b1c7 JC	97	i2c1: i2c@11100 {
	98	compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
	99	reg = <0x11100 0x100>;
467f54b2	100	};
9ae6f740	101
181d9b28	102	uart2: serial@12200 {
b24212fb	103	compatible = "snps,dw-apb-uart";
d352f41e AE	104	pinctrl-0 = <&uart2_pins>;
d352f41e AE	105	pinctrl-names = "default";
82a68267	106	reg = <0x12200 0x100>;
9ae6f740 TP	107	reg-shift = <2>;
9ae6f740 TP	108	interrupts = <43>;
e366154f	109	reg-io-width = <1>;
64939dc5	110	clocks = <&coreclk 0>;
9ae6f740	111	status = "disabled";
467f54b2	112	};
181d9b28 AE	113
181d9b28 AE	114	uart3: serial@12300 {
b24212fb	115	compatible = "snps,dw-apb-uart";
d352f41e AE	116	pinctrl-0 = <&uart3_pins>;
d352f41e AE	117	pinctrl-names = "default";
82a68267	118	reg = <0x12300 0x100>;
9ae6f740 TP	119	reg-shift = <2>;
9ae6f740 TP	120	interrupts = <44>;
e366154f	121	reg-io-width = <1>;
64939dc5	122	clocks = <&coreclk 0>;
9ae6f740	123	status = "disabled";
467f54b2	124	};
9ae6f740	125
a095b1c7 JC	126	system-controller@18200 {
	127	compatible = "marvell,armada-370-xp-system-controller";
	128	reg = <0x18200 0x500>;
	129	};
	130
	131	gateclk: clock-gating-control@18220 {
	132	compatible = "marvell,armada-xp-gating-clock";
	133	reg = <0x18220 0x4>;
	134	clocks = <&coreclk 0>;
	135	#clock-cells = <1>;
467f54b2	136	};
9ae6f740	137
467f54b2 GC	138	coreclk: mvebu-sar@18230 {
	139	compatible = "marvell,armada-xp-core-clock";
	140	reg = <0x18230 0x08>;
	141	#clock-cells = <1>;
	142	};
9d202783	143
a095b1c7 JC	144	thermal@182b0 {
	145	compatible = "marvell,armadaxp-thermal";
	146	reg = <0x182b0 0x4
	147	0x184d0 0x4>;
	148	status = "okay";
	149	};
	150
467f54b2 GC	151	cpuclk: clock-complex@18700 {
	152	#clock-cells = <1>;
	153	compatible = "marvell,armada-xp-cpu-clock";
b7f01842	154	reg = <0x18700 0x24>, <0x1c054 0x10>;
467f54b2 GC	155	clocks = <&coreclk 1>;
467f54b2 GC	156	};
9d202783	157
24c2573b	158	interrupt-controller@20a00 {
a095b1c7	159	reg = <0x20a00 0x2d0>, <0x21070 0x58>;
467f54b2	160	};
9d202783	161
a095b1c7 JC	162	timer@20300 {
	163	compatible = "marvell,armada-xp-timer";
	164	clocks = <&coreclk 2>, <&refclk>;
	165	clock-names = "nbclk", "fixed";
	166	};
	167
05afeeb9 EG	168	watchdog@20300 {
	169	compatible = "marvell,armada-xp-wdt";
	170	clocks = <&coreclk 2>, <&refclk>;
	171	clock-names = "nbclk", "fixed";
	172	};
	173
b6249d4b GC	174	cpurst@20800 {
	175	compatible = "marvell,armada-370-cpu-reset";
	176	reg = <0x20800 0x20>;
467f54b2	177	};
323c1010	178
be5a9389	179	eth2: ethernet@30000 {
ea3b55fe	180	compatible = "marvell,armada-xp-neta";
cf8088c5	181	reg = <0x30000 0x4000>;
323c1010	182	interrupts = <12>;
4aa935a2	183	clocks = <&gateclk 2>;
323c1010	184	status = "disabled";
a1d53dab	185	};
a1d53dab	186
a095b1c7 JC	187	usb@50000 {
	188	clocks = <&gateclk 18>;
	189	};
	190
	191	usb@51000 {
	192	clocks = <&gateclk 19>;
	193	};
	194
	195	usb@52000 {
	196	compatible = "marvell,orion-ehci";
	197	reg = <0x52000 0x500>;
	198	interrupts = <47>;
	199	clocks = <&gateclk 20>;
	200	status = "disabled";
	201	};
	202
467f54b2 GC	203	xor@60900 {
	204	compatible = "marvell,orion-xor";
	205	reg = <0x60900 0x100
	206	0x60b00 0x100>;
	207	clocks = <&gateclk 22>;
	208	status = "okay";
	209
	210	xor10 {
	211	interrupts = <51>;
	212	dmacap,memcpy;
	213	dmacap,xor;
	214	};
	215	xor11 {
	216	interrupts = <52>;
	217	dmacap,memcpy;
	218	dmacap,xor;
	219	dmacap,memset;
	220	};
a1d53dab	221	};
467f54b2	222
ea3b55fe SG	223	ethernet@70000 {
	224	compatible = "marvell,armada-xp-neta";
	225	};
	226
	227	ethernet@74000 {
	228	compatible = "marvell,armada-xp-neta";
	229	};
	230
467f54b2 GC	231	xor@f0900 {
	232	compatible = "marvell,orion-xor";
	233	reg = <0xF0900 0x100
	234	0xF0B00 0x100>;
	235	clocks = <&gateclk 28>;
	236	status = "okay";
	237
	238	xor00 {
	239	interrupts = <94>;
	240	dmacap,memcpy;
	241	dmacap,xor;
	242	};
	243	xor01 {
	244	interrupts = <95>;
	245	dmacap,memcpy;
	246	dmacap,xor;
	247	dmacap,memset;
	248	};
a1d53dab	249	};
693a56ea	250	};
9ae6f740	251	};
c1bbd430 EG	252
	253	clocks {
	254	/* 25 MHz reference crystal */
	255	refclk: oscillator {
	256	compatible = "fixed-clock";
	257	#clock-cells = <0>;
	258	clock-frequency = <25000000>;
	259	};
	260	};
9ae6f740	261	};
4904a82a AE	262
4904a82a AE	263	&pinctrl {
70ee4e9d	264	ge0_gmii_pins: ge0-gmii-pins {
4904a82a AE	265	marvell,pins =
	266	"mpp0", "mpp1", "mpp2", "mpp3",
	267	"mpp4", "mpp5", "mpp6", "mpp7",
	268	"mpp8", "mpp9", "mpp10", "mpp11",
	269	"mpp12", "mpp13", "mpp14", "mpp15",
	270	"mpp16", "mpp17", "mpp18", "mpp19",
	271	"mpp20", "mpp21", "mpp22", "mpp23";
	272	marvell,function = "ge0";
	273	};
	274
70ee4e9d	275	ge0_rgmii_pins: ge0-rgmii-pins {
4904a82a AE	276	marvell,pins =
	277	"mpp0", "mpp1", "mpp2", "mpp3",
	278	"mpp4", "mpp5", "mpp6", "mpp7",
	279	"mpp8", "mpp9", "mpp10", "mpp11";
	280	marvell,function = "ge0";
	281	};
	282
70ee4e9d	283	ge1_rgmii_pins: ge1-rgmii-pins {
4904a82a AE	284	marvell,pins =
	285	"mpp12", "mpp13", "mpp14", "mpp15",
	286	"mpp16", "mpp17", "mpp18", "mpp19",
	287	"mpp20", "mpp21", "mpp22", "mpp23";
	288	marvell,function = "ge1";
	289	};
	290
	291	sdio_pins: sdio-pins {
	292	marvell,pins = "mpp30", "mpp31", "mpp32",
	293	"mpp33", "mpp34", "mpp35";
	294	marvell,function = "sd0";
	295	};
d352f41e	296
547c653b AE	297	spi0_pins: spi0-pins {
	298	marvell,pins = "mpp36", "mpp37",
	299	"mpp38", "mpp39";
	300	marvell,function = "spi";
	301	};
	302
d352f41e AE	303	uart2_pins: uart2-pins {
	304	marvell,pins = "mpp42", "mpp43";
	305	marvell,function = "uart2";
	306	};
	307
	308	uart3_pins: uart3-pins {
	309	marvell,pins = "mpp44", "mpp45";
	310	marvell,function = "uart3";
	311	};
4904a82a	312	};