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ARM: at91/dt: at91rm9200ek: enable RTC
[deliverable/linux.git] / arch / arm / boot / dts / at91rm9200.dtsi
CommitLineData
fe975cf6
JE		 1/*
2 * at91rm9200.dtsi - Device Tree Include file for AT91RM9200 family SoC
3 *
4 * Copyright (C) 2011 Atmel,
5 * 2011 Nicolas Ferre <nicolas.ferre@atmel.com>,
6 * 2012 Joachim Eastwood <manabian@gmail.com>
7 *
8 * Based on at91sam9260.dtsi
9 *
10 * Licensed under GPLv2 or later.
11 */
12
6db64d29 13#include "skeleton.dtsi"
c9d0f317 14#include <dt-bindings/pinctrl/at91.h>
5e8b3bc3 15#include <dt-bindings/interrupt-controller/irq.h>
92f8629b 16#include <dt-bindings/gpio/gpio.h>
68580013 17#include <dt-bindings/clock/at91.h>
fe975cf6
JE		 18
19/ {
20 model = "Atmel AT91RM9200 family SoC";
21 compatible = "atmel,at91rm9200";
22 interrupt-parent = <&aic>;
23
24 aliases {
25 serial0 = &dbgu;
26 serial1 = &usart0;
27 serial2 = &usart1;
28 serial3 = &usart2;
29 serial4 = &usart3;
30 gpio0 = &pioA;
31 gpio1 = &pioB;
32 gpio2 = &pioC;
33 gpio3 = &pioD;
34 tcb0 = &tcb0;
35 tcb1 = &tcb1;
2d25210d 36 i2c0 = &i2c0;
883a07f6
JE		 37 ssc0 = &ssc0;
38 ssc1 = &ssc1;
39 ssc2 = &ssc2;
fe975cf6
JE		 40 };
41 cpus {
e757a6ee
LP		 42 #address-cells = <0>;
43 #size-cells = <0>;
44
45 cpu {
fe975cf6 46 compatible = "arm,arm920t";
e757a6ee 47 device_type = "cpu";
fe975cf6
JE		 48 };
49 };
50
51 memory {
52 reg = <0x20000000 0x04000000>;
53 };
54
68580013
AB		 55 clocks {
56 slow_xtal: slow_xtal {
57 compatible = "fixed-clock";
58 #clock-cells = <0>;
59 clock-frequency = <0>;
60 };
61
62 main_xtal: main_xtal {
63 compatible = "fixed-clock";
64 #clock-cells = <0>;
65 clock-frequency = <0>;
66 };
67 };
68
fe975cf6
JE		 69 ahb {
70 compatible = "simple-bus";
71 #address-cells = <1>;
72 #size-cells = <1>;
73 ranges;
74
75 apb {
76 compatible = "simple-bus";
77 #address-cells = <1>;
78 #size-cells = <1>;
79 ranges;
80
81 aic: interrupt-controller@fffff000 {
82 #interrupt-cells = <3>;
83 compatible = "atmel,at91rm9200-aic";
84 interrupt-controller;
85 reg = <0xfffff000 0x200>;
86 atmel,external-irqs = <25 26 27 28 29 30 31>;
87 };
88
89 ramc0: ramc@ffffff00 {
90 compatible = "atmel,at91rm9200-sdramc";
91 reg = <0xffffff00 0x100>;
92 };
93
94 pmc: pmc@fffffc00 {
95 compatible = "atmel,at91rm9200-pmc";
96 reg = <0xfffffc00 0x100>;
68580013
AB		 97 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
98 interrupt-controller;
99 #address-cells = <1>;
100 #size-cells = <0>;
101 #interrupt-cells = <1>;
102
103 main_osc: main_osc {
104 compatible = "atmel,at91rm9200-clk-main-osc";
105 #clock-cells = <0>;
106 interrupts-extended = <&pmc AT91_PMC_MOSCS>;
107 clocks = <&main_xtal>;
108 };
109
110 main: mainck {
111 compatible = "atmel,at91rm9200-clk-main";
112 #clock-cells = <0>;
113 clocks = <&main_osc>;
114 };
115
116 plla: pllack {
117 compatible = "atmel,at91rm9200-clk-pll";
118 #clock-cells = <0>;
119 interrupts-extended = <&pmc AT91_PMC_LOCKA>;
120 clocks = <&main>;
121 reg = <0>;
122 atmel,clk-input-range = <1000000 32000000>;
123 #atmel,pll-clk-output-range-cells = <3>;
124 atmel,pll-clk-output-ranges = <80000000 160000000 0>,
125 <150000000 180000000 2>;
126 };
127
128 pllb: pllbck {
129 compatible = "atmel,at91rm9200-clk-pll";
130 #clock-cells = <0>;
131 interrupts-extended = <&pmc AT91_PMC_LOCKB>;
132 clocks = <&main>;
133 reg = <1>;
134 atmel,clk-input-range = <1000000 32000000>;
135 #atmel,pll-clk-output-range-cells = <3>;
136 atmel,pll-clk-output-ranges = <80000000 160000000 0>,
137 <150000000 180000000 2>;
138 };
139
140 mck: masterck {
141 compatible = "atmel,at91rm9200-clk-master";
142 #clock-cells = <0>;
143 interrupts-extended = <&pmc AT91_PMC_MCKRDY>;
144 clocks = <&slow_xtal>, <&main>, <&plla>, <&pllb>;
145 atmel,clk-output-range = <0 80000000>;
146 atmel,clk-divisors = <1 2 3 4>;
147 };
148
149 usb: usbck {
150 compatible = "atmel,at91rm9200-clk-usb";
151 #clock-cells = <0>;
ea4fc621 152 atmel,clk-divisors = <1 2 0 0>;
68580013
AB		 153 clocks = <&pllb>;
154 };
155
156 prog: progck {
157 compatible = "atmel,at91rm9200-clk-programmable";
158 #address-cells = <1>;
159 #size-cells = <0>;
160 interrupt-parent = <&pmc>;
161 clocks = <&slow_xtal>, <&main>, <&plla>, <&pllb>;
162
163 prog0: prog0 {
164 #clock-cells = <0>;
165 reg = <0>;
166 interrupts = <AT91_PMC_PCKRDY(0)>;
167 };
168
169 prog1: prog1 {
170 #clock-cells = <0>;
171 reg = <1>;
172 interrupts = <AT91_PMC_PCKRDY(1)>;
173 };
174
175 prog2: prog2 {
176 #clock-cells = <0>;
177 reg = <2>;
178 interrupts = <AT91_PMC_PCKRDY(2)>;
179 };
180
181 prog3: prog3 {
182 #clock-cells = <0>;
183 reg = <3>;
184 interrupts = <AT91_PMC_PCKRDY(3)>;
185 };
186 };
187
188 systemck {
189 compatible = "atmel,at91rm9200-clk-system";
190 #address-cells = <1>;
191 #size-cells = <0>;
192
193 udpck: udpck {
194 #clock-cells = <0>;
195 reg = <2>;
196 clocks = <&usb>;
197 };
198
199 uhpck: uhpck {
200 #clock-cells = <0>;
201 reg = <4>;
202 clocks = <&usb>;
203 };
204
205 pck0: pck0 {
206 #clock-cells = <0>;
207 reg = <8>;
208 clocks = <&prog0>;
209 };
210
211 pck1: pck1 {
212 #clock-cells = <0>;
213 reg = <9>;
214 clocks = <&prog1>;
215 };
216
217 pck2: pck2 {
218 #clock-cells = <0>;
219 reg = <10>;
220 clocks = <&prog2>;
221 };
222
223 pck3: pck3 {
224 #clock-cells = <0>;
225 reg = <11>;
226 clocks = <&prog3>;
227 };
228 };
229
230 periphck {
231 compatible = "atmel,at91rm9200-clk-peripheral";
232 #address-cells = <1>;
233 #size-cells = <0>;
234 clocks = <&mck>;
235
236 pioA_clk: pioA_clk {
237 #clock-cells = <0>;
238 reg = <2>;
239 };
240
241 pioB_clk: pioB_clk {
242 #clock-cells = <0>;
243 reg = <3>;
244 };
245
246 pioC_clk: pioC_clk {
247 #clock-cells = <0>;
248 reg = <4>;
249 };
250
251 pioD_clk: pioD_clk {
252 #clock-cells = <0>;
253 reg = <5>;
254 };
255
256 usart0_clk: usart0_clk {
257 #clock-cells = <0>;
258 reg = <6>;
259 };
260
261 usart1_clk: usart1_clk {
262 #clock-cells = <0>;
263 reg = <7>;
264 };
265
266 usart2_clk: usart2_clk {
267 #clock-cells = <0>;
268 reg = <8>;
269 };
270
271 usart3_clk: usart3_clk {
272 #clock-cells = <0>;
273 reg = <9>;
274 };
275
276 mci0_clk: mci0_clk {
277 #clock-cells = <0>;
278 reg = <10>;
279 };
280
281 udc_clk: udc_clk {
282 #clock-cells = <0>;
283 reg = <11>;
284 };
285
286 twi0_clk: twi0_clk {
287 reg = <12>;
288 #clock-cells = <0>;
289 };
290
291 spi0_clk: spi0_clk {
292 #clock-cells = <0>;
293 reg = <13>;
294 };
295
296 ssc0_clk: ssc0_clk {
297 #clock-cells = <0>;
298 reg = <14>;
299 };
300
301 ssc1_clk: ssc1_clk {
302 #clock-cells = <0>;
303 reg = <15>;
304 };
305
306 ssc2_clk: ssc2_clk {
307 #clock-cells = <0>;
308 reg = <16>;
309 };
310
311 tc0_clk: tc0_clk {
312 #clock-cells = <0>;
313 reg = <17>;
314 };
315
316 tc1_clk: tc1_clk {
317 #clock-cells = <0>;
318 reg = <18>;
319 };
320
321 tc2_clk: tc2_clk {
322 #clock-cells = <0>;
323 reg = <19>;
324 };
325
326 tc3_clk: tc3_clk {
327 #clock-cells = <0>;
328 reg = <20>;
329 };
330
331 tc4_clk: tc4_clk {
332 #clock-cells = <0>;
333 reg = <21>;
334 };
335
336 tc5_clk: tc5_clk {
337 #clock-cells = <0>;
338 reg = <22>;
339 };
340
341 ohci_clk: ohci_clk {
342 #clock-cells = <0>;
343 reg = <23>;
344 };
345
346 macb0_clk: macb0_clk {
347 #clock-cells = <0>;
348 reg = <24>;
349 };
350 };
fe975cf6
JE		 351 };
352
353 st: timer@fffffd00 {
354 compatible = "atmel,at91rm9200-st";
355 reg = <0xfffffd00 0x100>;
5e8b3bc3 356 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
fe975cf6
JE		 357 };
358
e39f00e5
AB		 359 rtc: rtc@fffffe00 {
360 compatible = "atmel,at91rm9200-rtc";
361 reg = <0xfffffe00 0x40>;
362 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
363 status = "disabled";
364 };
365
fe975cf6
JE		 366 tcb0: timer@fffa0000 {
367 compatible = "atmel,at91rm9200-tcb";
368 reg = <0xfffa0000 0x100>;
5e8b3bc3
JCPV		 369 interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0
370 18 IRQ_TYPE_LEVEL_HIGH 0
371 19 IRQ_TYPE_LEVEL_HIGH 0>;
68580013
AB		 372 clocks = <&tc0_clk>, <&tc1_clk>, <&tc2_clk>;
373 clock-names = "t0_clk", "t1_clk", "t2_clk";
fe975cf6
JE		 374 };
375
376 tcb1: timer@fffa4000 {
377 compatible = "atmel,at91rm9200-tcb";
378 reg = <0xfffa4000 0x100>;
5e8b3bc3
JCPV		 379 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0
380 21 IRQ_TYPE_LEVEL_HIGH 0
381 22 IRQ_TYPE_LEVEL_HIGH 0>;
68580013
AB		 382 clocks = <&tc3_clk>, <&tc4_clk>, <&tc5_clk>;
383 clock-names = "t0_clk", "t1_clk", "t2_clk";
fe975cf6
JE		 384 };
385
2d25210d
JE		 386 i2c0: i2c@fffb8000 {
387 compatible = "atmel,at91rm9200-i2c";
388 reg = <0xfffb8000 0x4000>;
5e8b3bc3 389 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 6>;
2d25210d
JE		 390 pinctrl-names = "default";
391 pinctrl-0 = <&pinctrl_twi>;
68580013 392 clocks = <&twi0_clk>;
2d25210d
JE		 393 #address-cells = <1>;
394 #size-cells = <0>;
395 status = "disabled";
396 };
397
4e4c963e
JE		 398 mmc0: mmc@fffb4000 {
399 compatible = "atmel,hsmci";
400 reg = <0xfffb4000 0x4000>;
5e8b3bc3 401 interrupts = <10 IRQ_TYPE_LEVEL_HIGH 0>;
68580013
AB		 402 clocks = <&mci0_clk>;
403 clock-names = "mci_clk";
4e4c963e
JE		 404 #address-cells = <1>;
405 #size-cells = <0>;
90a69f13 406 pinctrl-names = "default";
4e4c963e
JE		 407 status = "disabled";
408 };
409
883a07f6
JE		 410 ssc0: ssc@fffd0000 {
411 compatible = "atmel,at91rm9200-ssc";
412 reg = <0xfffd0000 0x4000>;
5e8b3bc3 413 interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>;
883a07f6
JE		 414 pinctrl-names = "default";
415 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
68580013
AB		 416 clocks = <&ssc0_clk>;
417 clock-names = "pclk";
883a07f6
JE		 418 status = "disable";
419 };
420
421 ssc1: ssc@fffd4000 {
422 compatible = "atmel,at91rm9200-ssc";
423 reg = <0xfffd4000 0x4000>;
5e8b3bc3 424 interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>;
883a07f6
JE		 425 pinctrl-names = "default";
426 pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
68580013
AB		 427 clocks = <&ssc1_clk>;
428 clock-names = "pclk";
883a07f6
JE		 429 status = "disable";
430 };
431
432 ssc2: ssc@fffd8000 {
433 compatible = "atmel,at91rm9200-ssc";
434 reg = <0xfffd8000 0x4000>;
5e8b3bc3 435 interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>;
883a07f6
JE		 436 pinctrl-names = "default";
437 pinctrl-0 = <&pinctrl_ssc2_tx &pinctrl_ssc2_rx>;
68580013
AB		 438 clocks = <&ssc2_clk>;
439 clock-names = "pclk";
883a07f6
JE		 440 status = "disable";
441 };
442
ce3b2630
JE		 443 macb0: ethernet@fffbc000 {
444 compatible = "cdns,at91rm9200-emac", "cdns,emac";
445 reg = <0xfffbc000 0x4000>;
5e8b3bc3 446 interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>;
ce3b2630
JE		 447 phy-mode = "rmii";
448 pinctrl-names = "default";
449 pinctrl-0 = <&pinctrl_macb_rmii>;
68580013
AB		 450 clocks = <&macb0_clk>;
451 clock-names = "ether_clk";
ce3b2630
JE		 452 status = "disabled";
453 };
454
fe975cf6
JE		 455 pinctrl@fffff400 {
456 #address-cells = <1>;
457 #size-cells = <1>;
458 compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
459 ranges = <0xfffff400 0xfffff400 0x800>;
460
461 atmel,mux-mask = <
462 /* A B */
463 0xffffffff 0xffffffff /* pioA */
464 0xffffffff 0x083fffff /* pioB */
465 0xffff3fff 0x00000000 /* pioC */
466 0x03ff87ff 0x0fffff80 /* pioD */
467 >;
468
469 /* shared pinctrl settings */
470 dbgu {
471 pinctrl_dbgu: dbgu-0 {
472 atmel,pins =
c9d0f317
JCPV		 473 <AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA30 periph A */
474 AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA31 periph with pullup */
fe975cf6
JE		 475 };
476 };
477
478 uart0 {
479 pinctrl_uart0: uart0-0 {
480 atmel,pins =
c9d0f317
JCPV		 481 <AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA17 periph A */
482 AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA18 periph A */
fe975cf6
JE		 483 };
484
5cffba20 485 pinctrl_uart0_cts: uart0_cts-0 {
fe975cf6 486 atmel,pins =
c9d0f317 487 <AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA20 periph A */
fe975cf6
JE		 488 };
489
5cffba20 490 pinctrl_uart0_rts: uart0_rts-0 {
fe975cf6 491 atmel,pins =
c9d0f317 492 <AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA21 periph A */
fe975cf6
JE		 493 };
494 };
495
496 uart1 {
497 pinctrl_uart1: uart1-0 {
498 atmel,pins =
c9d0f317
JCPV		 499 <AT91_PIOB 20 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB20 periph A with pullup */
500 AT91_PIOB 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB21 periph A */
fe975cf6
JE		 501 };
502
503 pinctrl_uart1_rts: uart1_rts-0 {
504 atmel,pins =
c9d0f317 505 <AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB24 periph A */
fe975cf6
JE		 506 };
507
508 pinctrl_uart1_cts: uart1_cts-0 {
509 atmel,pins =
c9d0f317 510 <AT91_PIOB 26 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB26 periph A */
fe975cf6
JE		 511 };
512
513 pinctrl_uart1_dtr_dsr: uart1_dtr_dsr-0 {
514 atmel,pins =
c9d0f317
JCPV		 515 <AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB19 periph A */
516 AT91_PIOB 25 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB25 periph A */
fe975cf6
JE		 517 };
518
519 pinctrl_uart1_dcd: uart1_dcd-0 {
520 atmel,pins =
c9d0f317 521 <AT91_PIOB 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB23 periph A */
fe975cf6
JE		 522 };
523
524 pinctrl_uart1_ri: uart1_ri-0 {
525 atmel,pins =
c9d0f317 526 <AT91_PIOB 18 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB18 periph A */
fe975cf6
JE		 527 };
528 };
529
530 uart2 {
531 pinctrl_uart2: uart2-0 {
532 atmel,pins =
c9d0f317
JCPV		 533 <AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA22 periph A */
534 AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA23 periph A with pullup */
fe975cf6
JE		 535 };
536
537 pinctrl_uart2_rts: uart2_rts-0 {
538 atmel,pins =
c9d0f317 539 <AT91_PIOA 30 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA30 periph B */
fe975cf6
JE		 540 };
541
542 pinctrl_uart2_cts: uart2_cts-0 {
543 atmel,pins =
c9d0f317 544 <AT91_PIOA 31 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA31 periph B */
fe975cf6
JE		 545 };
546 };
547
548 uart3 {
549 pinctrl_uart3: uart3-0 {
550 atmel,pins =
c9d0f317
JCPV		 551 <AT91_PIOA 5 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA5 periph B with pullup */
552 AT91_PIOA 6 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA6 periph B */
fe975cf6
JE		 553 };
554
555 pinctrl_uart3_rts: uart3_rts-0 {
556 atmel,pins =
c9d0f317 557 <AT91_PIOB 0 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB0 periph B */
fe975cf6
JE		 558 };
559
560 pinctrl_uart3_cts: uart3_cts-0 {
561 atmel,pins =
c9d0f317 562 <AT91_PIOB 1 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB1 periph B */
fe975cf6
JE		 563 };
564 };
565
566 nand {
567 pinctrl_nand: nand-0 {
568 atmel,pins =
c9d0f317
JCPV		 569 <AT91_PIOC 2 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP /* PC2 gpio RDY pin pull_up */
570 AT91_PIOB 1 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>; /* PB1 gpio CD pin pull_up */
fe975cf6
JE		 571 };
572 };
573
ce3b2630
JE		 574 macb {
575 pinctrl_macb_rmii: macb_rmii-0 {
576 atmel,pins =
c9d0f317
JCPV		 577 <AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA7 periph A */
578 AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA8 periph A */
579 AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA9 periph A */
580 AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA10 periph A */
581 AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA11 periph A */
582 AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA12 periph A */
583 AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA13 periph A */
584 AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA14 periph A */
585 AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA15 periph A */
586 AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA16 periph A */
ce3b2630
JE		 587 };
588
589 pinctrl_macb_rmii_mii: macb_rmii_mii-0 {
590 atmel,pins =
c9d0f317
JCPV		 591 <AT91_PIOB 12 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB12 periph B */
592 AT91_PIOB 13 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB13 periph B */
593 AT91_PIOB 14 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB14 periph B */
594 AT91_PIOB 15 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB15 periph B */
595 AT91_PIOB 16 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB16 periph B */
596 AT91_PIOB 17 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB17 periph B */
597 AT91_PIOB 18 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB18 periph B */
598 AT91_PIOB 19 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB19 periph B */
ce3b2630
JE		 599 };
600 };
601
4e4c963e
JE		 602 mmc0 {
603 pinctrl_mmc0_clk: mmc0_clk-0 {
604 atmel,pins =
c9d0f317 605 <AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA27 periph A */
4e4c963e
JE		 606 };
607
608 pinctrl_mmc0_slot0_cmd_dat0: mmc0_slot0_cmd_dat0-0 {
609 atmel,pins =
c9d0f317
JCPV		 610 <AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA28 periph A with pullup */
611 AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA29 periph A with pullup */
4e4c963e
JE		 612 };
613
614 pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
615 atmel,pins =
c9d0f317
JCPV		 616 <AT91_PIOB 3 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PB3 periph B with pullup */
617 AT91_PIOB 4 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PB4 periph B with pullup */
618 AT91_PIOB 5 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PB5 periph B with pullup */
4e4c963e
JE		 619 };
620
621 pinctrl_mmc0_slot1_cmd_dat0: mmc0_slot1_cmd_dat0-0 {
622 atmel,pins =
c9d0f317
JCPV		 623 <AT91_PIOA 8 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA8 periph B with pullup */
624 AT91_PIOA 9 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PA9 periph B with pullup */
4e4c963e
JE		 625 };
626
627 pinctrl_mmc0_slot1_dat1_3: mmc0_slot1_dat1_3-0 {
628 atmel,pins =
c9d0f317
JCPV		 629 <AT91_PIOA 10 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA10 periph B with pullup */
630 AT91_PIOA 11 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA11 periph B with pullup */
631 AT91_PIOA 12 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PA12 periph B with pullup */
4e4c963e
JE		 632 };
633 };
634
883a07f6
JE		 635 ssc0 {
636 pinctrl_ssc0_tx: ssc0_tx-0 {
637 atmel,pins =
c9d0f317
JCPV		 638 <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB0 periph A */
639 AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB1 periph A */
640 AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB2 periph A */
883a07f6
JE		 641 };
642
643 pinctrl_ssc0_rx: ssc0_rx-0 {
644 atmel,pins =
c9d0f317
JCPV		 645 <AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB3 periph A */
646 AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB4 periph A */
647 AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB5 periph A */
883a07f6
JE		 648 };
649 };
650
651 ssc1 {
652 pinctrl_ssc1_tx: ssc1_tx-0 {
653 atmel,pins =
c9d0f317
JCPV		 654 <AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB6 periph A */
655 AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB7 periph A */
656 AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB8 periph A */
883a07f6
JE		 657 };
658
659 pinctrl_ssc1_rx: ssc1_rx-0 {
660 atmel,pins =
c9d0f317
JCPV		 661 <AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB9 periph A */
662 AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB10 periph A */
663 AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB11 periph A */
883a07f6
JE		 664 };
665 };
666
667 ssc2 {
668 pinctrl_ssc2_tx: ssc2_tx-0 {
669 atmel,pins =
c9d0f317
JCPV		 670 <AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB12 periph A */
671 AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB13 periph A */
672 AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB14 periph A */
883a07f6
JE		 673 };
674
675 pinctrl_ssc2_rx: ssc2_rx-0 {
676 atmel,pins =
c9d0f317
JCPV		 677 <AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB15 periph A */
678 AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB16 periph A */
679 AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB17 periph A */
883a07f6
JE		 680 };
681 };
682
2d25210d
JE		 683 twi {
684 pinctrl_twi: twi-0 {
685 atmel,pins =
c9d0f317
JCPV		 686 <AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_MULTI_DRIVE /* PA25 periph A with multi drive */
687 AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_MULTI_DRIVE>; /* PA26 periph A with multi drive */
2d25210d 688 };
83960c82
JE		 689
690 pinctrl_twi_gpio: twi_gpio-0 {
691 atmel,pins =
c9d0f317
JCPV		 692 <AT91_PIOA 25 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE /* PA25 GPIO with multi drive */
693 AT91_PIOA 26 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE>; /* PA26 GPIO with multi drive */
83960c82 694 };
2d25210d
JE		 695 };
696
028633c2
BB		 697 tcb0 {
698 pinctrl_tcb0_tclk0: tcb0_tclk0-0 {
699 atmel,pins = <AT91_PIOA 13 AT91_PERIPH_B AT91_PINCTRL_NONE>;
700 };
701
702 pinctrl_tcb0_tclk1: tcb0_tclk1-0 {
703 atmel,pins = <AT91_PIOA 14 AT91_PERIPH_B AT91_PINCTRL_NONE>;
704 };
705
706 pinctrl_tcb0_tclk2: tcb0_tclk2-0 {
707 atmel,pins = <AT91_PIOA 15 AT91_PERIPH_B AT91_PINCTRL_NONE>;
708 };
709
710 pinctrl_tcb0_tioa0: tcb0_tioa0-0 {
711 atmel,pins = <AT91_PIOA 17 AT91_PERIPH_B AT91_PINCTRL_NONE>;
712 };
713
714 pinctrl_tcb0_tioa1: tcb0_tioa1-0 {
715 atmel,pins = <AT91_PIOA 19 AT91_PERIPH_B AT91_PINCTRL_NONE>;
716 };
717
718 pinctrl_tcb0_tioa2: tcb0_tioa2-0 {
719 atmel,pins = <AT91_PIOA 21 AT91_PERIPH_B AT91_PINCTRL_NONE>;
720 };
721
722 pinctrl_tcb0_tiob0: tcb0_tiob0-0 {
723 atmel,pins = <AT91_PIOA 18 AT91_PERIPH_B AT91_PINCTRL_NONE>;
724 };
725
726 pinctrl_tcb0_tiob1: tcb0_tiob1-0 {
727 atmel,pins = <AT91_PIOA 20 AT91_PERIPH_B AT91_PINCTRL_NONE>;
728 };
729
730 pinctrl_tcb0_tiob2: tcb0_tiob2-0 {
731 atmel,pins = <AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE>;
732 };
733 };
734
735 tcb1 {
736 pinctrl_tcb1_tclk0: tcb1_tclk0-0 {
737 atmel,pins = <AT91_PIOA 27 AT91_PERIPH_B AT91_PINCTRL_NONE>;
738 };
739
740 pinctrl_tcb1_tclk1: tcb1_tclk1-0 {
741 atmel,pins = <AT91_PIOA 28 AT91_PERIPH_B AT91_PINCTRL_NONE>;
742 };
743
744 pinctrl_tcb1_tclk2: tcb1_tclk2-0 {
745 atmel,pins = <AT91_PIOA 29 AT91_PERIPH_B AT91_PINCTRL_NONE>;
746 };
747
748 pinctrl_tcb1_tioa0: tcb1_tioa0-0 {
749 atmel,pins = <AT91_PIOB 6 AT91_PERIPH_B AT91_PINCTRL_NONE>;
750 };
751
752 pinctrl_tcb1_tioa1: tcb1_tioa1-0 {
753 atmel,pins = <AT91_PIOB 8 AT91_PERIPH_B AT91_PINCTRL_NONE>;
754 };
755
756 pinctrl_tcb1_tioa2: tcb1_tioa2-0 {
757 atmel,pins = <AT91_PIOB 10 AT91_PERIPH_B AT91_PINCTRL_NONE>;
758 };
759
760 pinctrl_tcb1_tiob0: tcb1_tiob0-0 {
761 atmel,pins = <AT91_PIOB 7 AT91_PERIPH_B AT91_PINCTRL_NONE>;
762 };
763
764 pinctrl_tcb1_tiob1: tcb1_tiob1-0 {
765 atmel,pins = <AT91_PIOB 9 AT91_PERIPH_B AT91_PINCTRL_NONE>;
766 };
767
768 pinctrl_tcb1_tiob2: tcb1_tiob2-0 {
769 atmel,pins = <AT91_PIOB 11 AT91_PERIPH_B AT91_PINCTRL_NONE>;
770 };
771 };
772
32a86877
JCPV		 773 spi0 {
774 pinctrl_spi0: spi0-0 {
775 atmel,pins =
776 <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA0 periph A SPI0_MISO pin */
777 AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA1 periph A SPI0_MOSI pin */
778 AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA2 periph A SPI0_SPCK pin */
779 };
780 };
781
fe975cf6
JE		 782 pioA: gpio@fffff400 {
783 compatible = "atmel,at91rm9200-gpio";
784 reg = <0xfffff400 0x200>;
5e8b3bc3 785 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
fe975cf6
JE		 786 #gpio-cells = <2>;
787 gpio-controller;
788 interrupt-controller;
789 #interrupt-cells = <2>;
68580013 790 clocks = <&pioA_clk>;
fe975cf6
JE		 791 };
792
793 pioB: gpio@fffff600 {
794 compatible = "atmel,at91rm9200-gpio";
795 reg = <0xfffff600 0x200>;
5e8b3bc3 796 interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
fe975cf6
JE		 797 #gpio-cells = <2>;
798 gpio-controller;
799 interrupt-controller;
800 #interrupt-cells = <2>;
68580013 801 clocks = <&pioB_clk>;
fe975cf6
JE		 802 };
803
804 pioC: gpio@fffff800 {
805 compatible = "atmel,at91rm9200-gpio";
806 reg = <0xfffff800 0x200>;
5e8b3bc3 807 interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
fe975cf6
JE		 808 #gpio-cells = <2>;
809 gpio-controller;
810 interrupt-controller;
811 #interrupt-cells = <2>;
68580013 812 clocks = <&pioC_clk>;
fe975cf6
JE		 813 };
814
815 pioD: gpio@fffffa00 {
816 compatible = "atmel,at91rm9200-gpio";
817 reg = <0xfffffa00 0x200>;
5e8b3bc3 818 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>;
fe975cf6
JE		 819 #gpio-cells = <2>;
820 gpio-controller;
821 interrupt-controller;
822 #interrupt-cells = <2>;
68580013 823 clocks = <&pioD_clk>;
fe975cf6
JE		 824 };
825 };
826
827 dbgu: serial@fffff200 {
828 compatible = "atmel,at91rm9200-usart";
829 reg = <0xfffff200 0x200>;
5e8b3bc3 830 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
fe975cf6
JE		 831 pinctrl-names = "default";
832 pinctrl-0 = <&pinctrl_dbgu>;
68580013
AB		 833 clocks = <&mck>;
834 clock-names = "usart";
fe975cf6
JE		 835 status = "disabled";
836 };
837
838 usart0: serial@fffc0000 {
839 compatible = "atmel,at91rm9200-usart";
840 reg = <0xfffc0000 0x200>;
5e8b3bc3 841 interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>;
fe975cf6
JE		 842 atmel,use-dma-rx;
843 atmel,use-dma-tx;
844 pinctrl-names = "default";
845 pinctrl-0 = <&pinctrl_uart0>;
68580013
AB		 846 clocks = <&usart0_clk>;
847 clock-names = "usart";
fe975cf6
JE		 848 status = "disabled";
849 };
850
851 usart1: serial@fffc4000 {
852 compatible = "atmel,at91rm9200-usart";
853 reg = <0xfffc4000 0x200>;
5e8b3bc3 854 interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>;
fe975cf6
JE		 855 atmel,use-dma-rx;
856 atmel,use-dma-tx;
857 pinctrl-names = "default";
858 pinctrl-0 = <&pinctrl_uart1>;
68580013
AB		 859 clocks = <&usart1_clk>;
860 clock-names = "usart";
fe975cf6
JE		 861 status = "disabled";
862 };
863
864 usart2: serial@fffc8000 {
865 compatible = "atmel,at91rm9200-usart";
866 reg = <0xfffc8000 0x200>;
5e8b3bc3 867 interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>;
fe975cf6
JE		 868 atmel,use-dma-rx;
869 atmel,use-dma-tx;
870 pinctrl-names = "default";
871 pinctrl-0 = <&pinctrl_uart2>;
68580013
AB		 872 clocks = <&usart2_clk>;
873 clock-names = "usart";
fe975cf6
JE		 874 status = "disabled";
875 };
876
877 usart3: serial@fffcc000 {
878 compatible = "atmel,at91rm9200-usart";
879 reg = <0xfffcc000 0x200>;
5e8b3bc3 880 interrupts = <23 IRQ_TYPE_LEVEL_HIGH 5>;
fe975cf6
JE		 881 atmel,use-dma-rx;
882 atmel,use-dma-tx;
883 pinctrl-names = "default";
884 pinctrl-0 = <&pinctrl_uart3>;
68580013
AB		 885 clocks = <&usart3_clk>;
886 clock-names = "usart";
fe975cf6
JE		 887 status = "disabled";
888 };
889
890 usb1: gadget@fffb0000 {
891 compatible = "atmel,at91rm9200-udc";
892 reg = <0xfffb0000 0x4000>;
5e8b3bc3 893 interrupts = <11 IRQ_TYPE_LEVEL_HIGH 2>;
68580013
AB		 894 clocks = <&udc_clk>, <&udpck>;
895 clock-names = "pclk", "hclk";
fe975cf6
JE		 896 status = "disabled";
897 };
32a86877
JCPV		 898
899 spi0: spi@fffe0000 {
900 #address-cells = <1>;
901 #size-cells = <0>;
902 compatible = "atmel,at91rm9200-spi";
903 reg = <0xfffe0000 0x200>;
904 interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>;
905 pinctrl-names = "default";
906 pinctrl-0 = <&pinctrl_spi0>;
68580013
AB		 907 clocks = <&spi0_clk>;
908 clock-names = "spi_clk";
32a86877
JCPV		 909 status = "disabled";
910 };
fe975cf6
JE		 911 };
912
913 nand0: nand@40000000 {
914 compatible = "atmel,at91rm9200-nand";
915 #address-cells = <1>;
916 #size-cells = <1>;
917 reg = <0x40000000 0x10000000>;
918 atmel,nand-addr-offset = <21>;
919 atmel,nand-cmd-offset = <22>;
920 pinctrl-names = "default";
921 pinctrl-0 = <&pinctrl_nand>;
922 nand-ecc-mode = "soft";
92f8629b 923 gpios = <&pioC 2 GPIO_ACTIVE_HIGH
fe975cf6 924 0
92f8629b 925 &pioB 1 GPIO_ACTIVE_HIGH
fe975cf6
JE		 926 >;
927 status = "disabled";
928 };
929
930 usb0: ohci@00300000 {
931 compatible = "atmel,at91rm9200-ohci", "usb-ohci";
932 reg = <0x00300000 0x100000>;
5e8b3bc3 933 interrupts = <23 IRQ_TYPE_LEVEL_HIGH 2>;
68580013
AB		 934 clocks = <&usb>, <&ohci_clk>, <&ohci_clk>, <&uhpck>;
935 clock-names = "usb_clk", "ohci_clk", "hclk", "uhpck";
fe975cf6
JE		 936 status = "disabled";
937 };
938 };
939
940 i2c@0 {
941 compatible = "i2c-gpio";
92f8629b
JCPV		 942 gpios = <&pioA 25 GPIO_ACTIVE_HIGH /* sda */
943 &pioA 26 GPIO_ACTIVE_HIGH /* scl */
fe975cf6
JE		 944 >;
945 i2c-gpio,sda-open-drain;
946 i2c-gpio,scl-open-drain;
947 i2c-gpio,delay-us = <2>; /* ~100 kHz */
83960c82
JE		 948 pinctrl-names = "default";
949 pinctrl-0 = <&pinctrl_twi_gpio>;
fe975cf6
JE		 950 #address-cells = <1>;
951 #size-cells = <0>;
952 status = "disabled";
953 };
954};
Linux kernel - Deliverables
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