projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| cce783c6 HX |
1 | /* |
| 2 | * at91sam9n12.dtsi - Device Tree include file for AT91SAM9N12 SoC | |
| 3 | * | |
| 4 | * Copyright (C) 2012 Atmel, | |
| 5 | * 2012 Hong Xu <hong.xu@atmel.com> | |
| 6 | * | |
| 7 | * Licensed under GPLv2 or later. | |
| 8 | */ | |
| 9 | ||
| 6db64d29 | 10 | #include "skeleton.dtsi" |
| d4ae89c8 | 11 | #include <dt-bindings/dma/at91.h> |
| c9d0f317 | 12 | #include <dt-bindings/pinctrl/at91.h> |
| 5e8b3bc3 | 13 | #include <dt-bindings/interrupt-controller/irq.h> |
| 92f8629b | 14 | #include <dt-bindings/gpio/gpio.h> |
| 68f1938e | 15 | #include <dt-bindings/clock/at91.h> |
| cce783c6 HX |
16 | |
| 17 | / { | |
| 18 | model = "Atmel AT91SAM9N12 SoC"; | |
| 19 | compatible = "atmel,at91sam9n12"; | |
| 20 | interrupt-parent = <&aic>; | |
| 21 | ||
| 22 | aliases { | |
| 23 | serial0 = &dbgu; | |
| 24 | serial1 = &usart0; | |
| 25 | serial2 = &usart1; | |
| 26 | serial3 = &usart2; | |
| 27 | serial4 = &usart3; | |
| 28 | gpio0 = &pioA; | |
| 29 | gpio1 = &pioB; | |
| 30 | gpio2 = &pioC; | |
| 31 | gpio3 = &pioD; | |
| 32 | tcb0 = &tcb0; | |
| 33 | tcb1 = &tcb1; | |
| 05dcd361 LD |
34 | i2c0 = &i2c0; |
| 35 | i2c1 = &i2c1; | |
| 544ae6b2 | 36 | ssc0 = &ssc0; |
| f3ab0527 | 37 | pwm0 = &pwm0; |
| cce783c6 HX |
38 | }; |
| 39 | cpus { | |
| e757a6ee LP |
40 | #address-cells = <0>; |
| 41 | #size-cells = <0>; | |
| 42 | ||
| 43 | cpu { | |
| 44 | compatible = "arm,arm926ej-s"; | |
| 45 | device_type = "cpu"; | |
| cce783c6 HX |
46 | }; |
| 47 | }; | |
| 48 | ||
| 49 | memory { | |
| 50 | reg = <0x20000000 0x10000000>; | |
| 51 | }; | |
| 52 | ||
| 68f1938e BB |
53 | slow_xtal: slow_xtal { |
| 54 | compatible = "fixed-clock"; | |
| 55 | #clock-cells = <0>; | |
| 56 | clock-frequency = <0>; | |
| 57 | }; | |
| 58 | ||
| 59 | main_xtal: main_xtal { | |
| 60 | compatible = "fixed-clock"; | |
| 61 | #clock-cells = <0>; | |
| 62 | clock-frequency = <0>; | |
| 63 | }; | |
| 64 | ||
| cce783c6 HX |
65 | ahb { |
| 66 | compatible = "simple-bus"; | |
| 67 | #address-cells = <1>; | |
| 68 | #size-cells = <1>; | |
| 69 | ranges; | |
| 70 | ||
| 71 | apb { | |
| 72 | compatible = "simple-bus"; | |
| 73 | #address-cells = <1>; | |
| 74 | #size-cells = <1>; | |
| 75 | ranges; | |
| 76 | ||
| 77 | aic: interrupt-controller@fffff000 { | |
| f8a073ee | 78 | #interrupt-cells = <3>; |
| cce783c6 HX |
79 | compatible = "atmel,at91rm9200-aic"; |
| 80 | interrupt-controller; | |
| 81 | reg = <0xfffff000 0x200>; | |
| 029efdda | 82 | atmel,external-irqs = <31>; |
| cce783c6 HX |
83 | }; |
| 84 | ||
| 85 | ramc0: ramc@ffffe800 { | |
| 86 | compatible = "atmel,at91sam9g45-ddramc"; | |
| 87 | reg = <0xffffe800 0x200>; | |
| 88 | }; | |
| 89 | ||
| 90 | pmc: pmc@fffffc00 { | |
| 68f1938e BB |
91 | compatible = "atmel,at91sam9n12-pmc"; |
| 92 | reg = <0xfffffc00 0x200>; | |
| 93 | interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; | |
| 94 | interrupt-controller; | |
| 95 | #address-cells = <1>; | |
| 96 | #size-cells = <0>; | |
| 97 | #interrupt-cells = <1>; | |
| 98 | ||
| 99 | main_rc_osc: main_rc_osc { | |
| 100 | compatible = "atmel,at91sam9x5-clk-main-rc-osc"; | |
| 101 | #clock-cells = <0>; | |
| 102 | interrupts-extended = <&pmc AT91_PMC_MOSCRCS>; | |
| 103 | clock-frequency = <12000000>; | |
| 104 | clock-accuracy = <50000000>; | |
| 105 | }; | |
| 106 | ||
| 107 | main_osc: main_osc { | |
| 108 | compatible = "atmel,at91rm9200-clk-main-osc"; | |
| 109 | #clock-cells = <0>; | |
| 110 | interrupts-extended = <&pmc AT91_PMC_MOSCS>; | |
| 111 | clocks = <&main_xtal>; | |
| 112 | }; | |
| 113 | ||
| 114 | main: mainck { | |
| 115 | compatible = "atmel,at91sam9x5-clk-main"; | |
| 116 | #clock-cells = <0>; | |
| 117 | interrupts-extended = <&pmc AT91_PMC_MOSCSELS>; | |
| 118 | clocks = <&main_rc_osc>, <&main_osc>; | |
| 119 | }; | |
| 120 | ||
| 121 | plla: pllack { | |
| 122 | compatible = "atmel,at91rm9200-clk-pll"; | |
| 123 | #clock-cells = <0>; | |
| 124 | interrupts-extended = <&pmc AT91_PMC_LOCKA>; | |
| 125 | clocks = <&main>; | |
| 126 | reg = <0>; | |
| 127 | atmel,clk-input-range = <2000000 32000000>; | |
| 128 | #atmel,pll-clk-output-range-cells = <4>; | |
| 129 | atmel,pll-clk-output-ranges = <745000000 800000000 0 0>, | |
| 130 | <695000000 750000000 1 0>, | |
| 131 | <645000000 700000000 2 0>, | |
| 132 | <595000000 650000000 3 0>, | |
| 133 | <545000000 600000000 0 1>, | |
| 134 | <495000000 555000000 1 1>, | |
| 135 | <445000000 500000000 1 2>, | |
| 136 | <400000000 450000000 1 3>; | |
| 137 | }; | |
| 138 | ||
| 139 | plladiv: plladivck { | |
| 140 | compatible = "atmel,at91sam9x5-clk-plldiv"; | |
| 141 | #clock-cells = <0>; | |
| 142 | clocks = <&plla>; | |
| 143 | }; | |
| 144 | ||
| 145 | pllb: pllbck { | |
| 146 | compatible = "atmel,at91rm9200-clk-pll"; | |
| 147 | #clock-cells = <0>; | |
| 148 | interrupts-extended = <&pmc AT91_PMC_LOCKB>; | |
| 149 | clocks = <&main>; | |
| 150 | reg = <1>; | |
| 151 | atmel,clk-input-range = <2000000 32000000>; | |
| 152 | #atmel,pll-clk-output-range-cells = <3>; | |
| 153 | atmel,pll-clk-output-ranges = <30000000 100000000 0>; | |
| 154 | }; | |
| 155 | ||
| 156 | mck: masterck { | |
| 157 | compatible = "atmel,at91sam9x5-clk-master"; | |
| 158 | #clock-cells = <0>; | |
| 159 | interrupts-extended = <&pmc AT91_PMC_MCKRDY>; | |
| 160 | clocks = <&clk32k>, <&main>, <&plladiv>, <&pllb>; | |
| 161 | atmel,clk-output-range = <0 133333333>; | |
| 162 | atmel,clk-divisors = <1 2 4 3>; | |
| 163 | atmel,master-clk-have-div3-pres; | |
| 164 | }; | |
| 165 | ||
| 166 | usb: usbck { | |
| 167 | compatible = "atmel,at91sam9n12-clk-usb"; | |
| 168 | #clock-cells = <0>; | |
| 169 | clocks = <&pllb>; | |
| 170 | }; | |
| 171 | ||
| 172 | prog: progck { | |
| 173 | compatible = "atmel,at91sam9x5-clk-programmable"; | |
| 174 | #address-cells = <1>; | |
| 175 | #size-cells = <0>; | |
| 176 | interrupt-parent = <&pmc>; | |
| 177 | clocks = <&clk32k>, <&main>, <&plladiv>, <&pllb>, <&mck>; | |
| 178 | ||
| 179 | prog0: prog0 { | |
| 180 | #clock-cells = <0>; | |
| 181 | reg = <0>; | |
| 182 | interrupts = <AT91_PMC_PCKRDY(0)>; | |
| 183 | }; | |
| 184 | ||
| 185 | prog1: prog1 { | |
| 186 | #clock-cells = <0>; | |
| 187 | reg = <1>; | |
| 188 | interrupts = <AT91_PMC_PCKRDY(1)>; | |
| 189 | }; | |
| 190 | }; | |
| 191 | ||
| 192 | systemck { | |
| 193 | compatible = "atmel,at91rm9200-clk-system"; | |
| 194 | #address-cells = <1>; | |
| 195 | #size-cells = <0>; | |
| 196 | ||
| 197 | ddrck: ddrck { | |
| 198 | #clock-cells = <0>; | |
| 199 | reg = <2>; | |
| 200 | clocks = <&mck>; | |
| 201 | }; | |
| 202 | ||
| 203 | lcdck: lcdck { | |
| 204 | #clock-cells = <0>; | |
| 205 | reg = <3>; | |
| 206 | clocks = <&mck>; | |
| 207 | }; | |
| 208 | ||
| 209 | uhpck: uhpck { | |
| 210 | #clock-cells = <0>; | |
| 211 | reg = <6>; | |
| 212 | clocks = <&usb>; | |
| 213 | }; | |
| 214 | ||
| 215 | udpck: udpck { | |
| 216 | #clock-cells = <0>; | |
| 217 | reg = <7>; | |
| 218 | clocks = <&usb>; | |
| 219 | }; | |
| 220 | ||
| 221 | pck0: pck0 { | |
| 222 | #clock-cells = <0>; | |
| 223 | reg = <8>; | |
| 224 | clocks = <&prog0>; | |
| 225 | }; | |
| 226 | ||
| 227 | pck1: pck1 { | |
| 228 | #clock-cells = <0>; | |
| 229 | reg = <9>; | |
| 230 | clocks = <&prog1>; | |
| 231 | }; | |
| 232 | }; | |
| 233 | ||
| 234 | periphck { | |
| 235 | compatible = "atmel,at91sam9x5-clk-peripheral"; | |
| 236 | #address-cells = <1>; | |
| 237 | #size-cells = <0>; | |
| 238 | clocks = <&mck>; | |
| 239 | ||
| 240 | pioAB_clk: pioAB_clk { | |
| 241 | #clock-cells = <0>; | |
| 242 | reg = <2>; | |
| 243 | }; | |
| 244 | ||
| 245 | pioCD_clk: pioCD_clk { | |
| 246 | #clock-cells = <0>; | |
| 247 | reg = <3>; | |
| 248 | }; | |
| 249 | ||
| 250 | fuse_clk: fuse_clk { | |
| 251 | #clock-cells = <0>; | |
| 252 | reg = <4>; | |
| 253 | }; | |
| 254 | ||
| 255 | usart0_clk: usart0_clk { | |
| 256 | #clock-cells = <0>; | |
| 257 | reg = <5>; | |
| 258 | }; | |
| 259 | ||
| 260 | usart1_clk: usart1_clk { | |
| 261 | #clock-cells = <0>; | |
| 262 | reg = <6>; | |
| 263 | }; | |
| 264 | ||
| 265 | usart2_clk: usart2_clk { | |
| 266 | #clock-cells = <0>; | |
| 267 | reg = <7>; | |
| 268 | }; | |
| 269 | ||
| 270 | usart3_clk: usart3_clk { | |
| 271 | #clock-cells = <0>; | |
| 272 | reg = <8>; | |
| 273 | }; | |
| 274 | ||
| 275 | twi0_clk: twi0_clk { | |
| 276 | reg = <9>; | |
| 277 | #clock-cells = <0>; | |
| 278 | }; | |
| 279 | ||
| 280 | twi1_clk: twi1_clk { | |
| 281 | #clock-cells = <0>; | |
| 282 | reg = <10>; | |
| 283 | }; | |
| 284 | ||
| 285 | mci0_clk: mci0_clk { | |
| 286 | #clock-cells = <0>; | |
| 287 | reg = <12>; | |
| 288 | }; | |
| 289 | ||
| 290 | spi0_clk: spi0_clk { | |
| 291 | #clock-cells = <0>; | |
| 292 | reg = <13>; | |
| 293 | }; | |
| 294 | ||
| 295 | spi1_clk: spi1_clk { | |
| 296 | #clock-cells = <0>; | |
| 297 | reg = <14>; | |
| 298 | }; | |
| 299 | ||
| 300 | uart0_clk: uart0_clk { | |
| 301 | #clock-cells = <0>; | |
| 302 | reg = <15>; | |
| 303 | }; | |
| 304 | ||
| 305 | uart1_clk: uart1_clk { | |
| 306 | #clock-cells = <0>; | |
| 307 | reg = <16>; | |
| 308 | }; | |
| 309 | ||
| 310 | tcb_clk: tcb_clk { | |
| 311 | #clock-cells = <0>; | |
| 312 | reg = <17>; | |
| 313 | }; | |
| 314 | ||
| 315 | pwm_clk: pwm_clk { | |
| 316 | #clock-cells = <0>; | |
| 317 | reg = <18>; | |
| 318 | }; | |
| 319 | ||
| 320 | adc_clk: adc_clk { | |
| 321 | #clock-cells = <0>; | |
| 322 | reg = <19>; | |
| 323 | }; | |
| 324 | ||
| 325 | dma0_clk: dma0_clk { | |
| 326 | #clock-cells = <0>; | |
| 327 | reg = <20>; | |
| 328 | }; | |
| 329 | ||
| 330 | uhphs_clk: uhphs_clk { | |
| 331 | #clock-cells = <0>; | |
| 332 | reg = <22>; | |
| 333 | }; | |
| 334 | ||
| 335 | udphs_clk: udphs_clk { | |
| 336 | #clock-cells = <0>; | |
| 337 | reg = <23>; | |
| 338 | }; | |
| 339 | ||
| 340 | lcdc_clk: lcdc_clk { | |
| 341 | #clock-cells = <0>; | |
| 342 | reg = <25>; | |
| 343 | }; | |
| 344 | ||
| 345 | sha_clk: sha_clk { | |
| 346 | #clock-cells = <0>; | |
| 347 | reg = <27>; | |
| 348 | }; | |
| 349 | ||
| 350 | ssc0_clk: ssc0_clk { | |
| 351 | #clock-cells = <0>; | |
| 352 | reg = <28>; | |
| 353 | }; | |
| 354 | ||
| 355 | aes_clk: aes_clk { | |
| 356 | #clock-cells = <0>; | |
| 357 | reg = <29>; | |
| 358 | }; | |
| 359 | ||
| 360 | trng_clk: trng_clk { | |
| 361 | #clock-cells = <0>; | |
| 362 | reg = <30>; | |
| 363 | }; | |
| 364 | }; | |
| cce783c6 HX |
365 | }; |
| 366 | ||
| 367 | rstc@fffffe00 { | |
| 368 | compatible = "atmel,at91sam9g45-rstc"; | |
| 369 | reg = <0xfffffe00 0x10>; | |
| 370 | }; | |
| 371 | ||
| 372 | pit: timer@fffffe30 { | |
| 373 | compatible = "atmel,at91sam9260-pit"; | |
| 374 | reg = <0xfffffe30 0xf>; | |
| 5e8b3bc3 | 375 | interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; |
| 68f1938e | 376 | clocks = <&mck>; |
| cce783c6 HX |
377 | }; |
| 378 | ||
| 379 | shdwc@fffffe10 { | |
| 380 | compatible = "atmel,at91sam9x5-shdwc"; | |
| 381 | reg = <0xfffffe10 0x10>; | |
| 382 | }; | |
| 383 | ||
| 68f1938e BB |
384 | sckc@fffffe50 { |
| 385 | compatible = "atmel,at91sam9x5-sckc"; | |
| 386 | reg = <0xfffffe50 0x4>; | |
| 387 | ||
| 388 | slow_osc: slow_osc { | |
| 389 | compatible = "atmel,at91sam9x5-clk-slow-osc"; | |
| 390 | #clock-cells = <0>; | |
| 391 | clocks = <&slow_xtal>; | |
| 392 | }; | |
| 393 | ||
| 394 | slow_rc_osc: slow_rc_osc { | |
| 395 | compatible = "atmel,at91sam9x5-clk-slow-rc-osc"; | |
| 396 | #clock-cells = <0>; | |
| 397 | clock-frequency = <32768>; | |
| 398 | clock-accuracy = <50000000>; | |
| 399 | }; | |
| 400 | ||
| 401 | clk32k: slck { | |
| 402 | compatible = "atmel,at91sam9x5-clk-slow"; | |
| 403 | #clock-cells = <0>; | |
| 404 | clocks = <&slow_rc_osc>, <&slow_osc>; | |
| 405 | }; | |
| 406 | }; | |
| 407 | ||
| 9873137a LD |
408 | mmc0: mmc@f0008000 { |
| 409 | compatible = "atmel,hsmci"; | |
| 410 | reg = <0xf0008000 0x600>; | |
| 5e8b3bc3 | 411 | interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>; |
| d4ae89c8 | 412 | dmas = <&dma 1 AT91_DMA_CFG_PER_ID(0)>; |
| 05c1bc97 | 413 | dma-names = "rxtx"; |
| 68f1938e BB |
414 | clocks = <&mci0_clk>; |
| 415 | clock-names = "mci_clk"; | |
| 9873137a LD |
416 | #address-cells = <1>; |
| 417 | #size-cells = <0>; | |
| 418 | status = "disabled"; | |
| 419 | }; | |
| 420 | ||
| cce783c6 HX |
421 | tcb0: timer@f8008000 { |
| 422 | compatible = "atmel,at91sam9x5-tcb"; | |
| 423 | reg = <0xf8008000 0x100>; | |
| 5e8b3bc3 | 424 | interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>; |
| 68f1938e BB |
425 | clocks = <&tcb_clk>; |
| 426 | clock-names = "t0_clk"; | |
| cce783c6 HX |
427 | }; |
| 428 | ||
| 429 | tcb1: timer@f800c000 { | |
| 430 | compatible = "atmel,at91sam9x5-tcb"; | |
| 431 | reg = <0xf800c000 0x100>; | |
| 5e8b3bc3 | 432 | interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>; |
| 68f1938e BB |
433 | clocks = <&tcb_clk>; |
| 434 | clock-names = "t0_clk"; | |
| cce783c6 HX |
435 | }; |
| 436 | ||
| 437 | dma: dma-controller@ffffec00 { | |
| 438 | compatible = "atmel,at91sam9g45-dma"; | |
| 439 | reg = <0xffffec00 0x200>; | |
| 5e8b3bc3 | 440 | interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>; |
| 980ce7d9 | 441 | #dma-cells = <2>; |
| 68f1938e BB |
442 | clocks = <&dma0_clk>; |
| 443 | clock-names = "dma_clk"; | |
| cce783c6 HX |
444 | }; |
| 445 | ||
| e4541ff2 JCPV |
446 | pinctrl@fffff400 { |
| 447 | #address-cells = <1>; | |
| 448 | #size-cells = <1>; | |
| 5314ec8e | 449 | compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus"; |
| e4541ff2 JCPV |
450 | ranges = <0xfffff400 0xfffff400 0x800>; |
| 451 | ||
| 5314ec8e JCPV |
452 | atmel,mux-mask = < |
| 453 | /* A B C */ | |
| 454 | 0xffffffff 0xffe07983 0x00000000 /* pioA */ | |
| 455 | 0x00040000 0x00047e0f 0x00000000 /* pioB */ | |
| 456 | 0xfdffffff 0x07c00000 0xb83fffff /* pioC */ | |
| 457 | 0x003fffff 0x003f8000 0x00000000 /* pioD */ | |
| 458 | >; | |
| 459 | ||
| 460 | /* shared pinctrl settings */ | |
| ec6754a7 JCPV |
461 | dbgu { |
| 462 | pinctrl_dbgu: dbgu-0 { | |
| 463 | atmel,pins = | |
| c9d0f317 JCPV |
464 | <AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA9 periph A */ |
| 465 | AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA10 periph with pullup */ | |
| ec6754a7 JCPV |
466 | }; |
| 467 | }; | |
| 468 | ||
| 9e3129e9 JCPV |
469 | usart0 { |
| 470 | pinctrl_usart0: usart0-0 { | |
| ec6754a7 | 471 | atmel,pins = |
| c9d0f317 JCPV |
472 | <AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA1 periph A with pullup */ |
| 473 | AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA0 periph A */ | |
| ec6754a7 JCPV |
474 | }; |
| 475 | ||
| c58c0c5a | 476 | pinctrl_usart0_rts: usart0_rts-0 { |
| ec6754a7 | 477 | atmel,pins = |
| c9d0f317 | 478 | <AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA2 periph A */ |
| c58c0c5a JCPV |
479 | }; |
| 480 | ||
| 481 | pinctrl_usart0_cts: usart0_cts-0 { | |
| 482 | atmel,pins = | |
| c9d0f317 | 483 | <AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA3 periph A */ |
| ec6754a7 JCPV |
484 | }; |
| 485 | }; | |
| 486 | ||
| 9e3129e9 JCPV |
487 | usart1 { |
| 488 | pinctrl_usart1: usart1-0 { | |
| ec6754a7 | 489 | atmel,pins = |
| c9d0f317 JCPV |
490 | <AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA6 periph A with pullup */ |
| 491 | AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA5 periph A */ | |
| ec6754a7 JCPV |
492 | }; |
| 493 | }; | |
| 494 | ||
| 9e3129e9 JCPV |
495 | usart2 { |
| 496 | pinctrl_usart2: usart2-0 { | |
| ec6754a7 | 497 | atmel,pins = |
| c9d0f317 JCPV |
498 | <AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA8 periph A with pullup */ |
| 499 | AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA7 periph A */ | |
| ec6754a7 JCPV |
500 | }; |
| 501 | ||
| c58c0c5a | 502 | pinctrl_usart2_rts: usart2_rts-0 { |
| ec6754a7 | 503 | atmel,pins = |
| c9d0f317 | 504 | <AT91_PIOB 0 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB0 periph B */ |
| c58c0c5a JCPV |
505 | }; |
| 506 | ||
| 507 | pinctrl_usart2_cts: usart2_cts-0 { | |
| 508 | atmel,pins = | |
| c9d0f317 | 509 | <AT91_PIOB 1 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB1 periph B */ |
| ec6754a7 JCPV |
510 | }; |
| 511 | }; | |
| 512 | ||
| 9e3129e9 JCPV |
513 | usart3 { |
| 514 | pinctrl_usart3: usart3-0 { | |
| ec6754a7 | 515 | atmel,pins = |
| c9d0f317 JCPV |
516 | <AT91_PIOC 23 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PC23 periph B with pullup */ |
| 517 | AT91_PIOC 22 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC22 periph B */ | |
| ec6754a7 JCPV |
518 | }; |
| 519 | ||
| c58c0c5a JCPV |
520 | pinctrl_usart3_rts: usart3_rts-0 { |
| 521 | atmel,pins = | |
| c9d0f317 | 522 | <AT91_PIOC 24 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC24 periph B */ |
| c58c0c5a JCPV |
523 | }; |
| 524 | ||
| 525 | pinctrl_usart3_cts: usart3_cts-0 { | |
| ec6754a7 | 526 | atmel,pins = |
| c9d0f317 | 527 | <AT91_PIOC 25 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC25 periph B */ |
| ec6754a7 JCPV |
528 | }; |
| 529 | }; | |
| 530 | ||
| 9e3129e9 JCPV |
531 | uart0 { |
| 532 | pinctrl_uart0: uart0-0 { | |
| ec6754a7 | 533 | atmel,pins = |
| c9d0f317 JCPV |
534 | <AT91_PIOC 9 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* PC9 periph C with pullup */ |
| 535 | AT91_PIOC 8 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC8 periph C */ | |
| ec6754a7 JCPV |
536 | }; |
| 537 | }; | |
| 538 | ||
| 9e3129e9 JCPV |
539 | uart1 { |
| 540 | pinctrl_uart1: uart1-0 { | |
| ec6754a7 | 541 | atmel,pins = |
| c9d0f317 JCPV |
542 | <AT91_PIOC 16 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* PC17 periph C with pullup */ |
| 543 | AT91_PIOC 17 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC16 periph C */ | |
| ec6754a7 JCPV |
544 | }; |
| 545 | }; | |
| 5314ec8e | 546 | |
| 7a38d450 JCPV |
547 | nand { |
| 548 | pinctrl_nand: nand-0 { | |
| 549 | atmel,pins = | |
| c9d0f317 JCPV |
550 | <AT91_PIOD 5 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP /* PD5 gpio RDY pin pull_up*/ |
| 551 | AT91_PIOD 4 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>; /* PD4 gpio enable pin pull_up */ | |
| 7a38d450 JCPV |
552 | }; |
| 553 | }; | |
| 554 | ||
| d4fe9ac7 JCPV |
555 | mmc0 { |
| 556 | pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 { | |
| 557 | atmel,pins = | |
| c9d0f317 JCPV |
558 | <AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA17 periph A */ |
| 559 | AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA16 periph A with pullup */ | |
| 560 | AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA15 periph A with pullup */ | |
| d4fe9ac7 JCPV |
561 | }; |
| 562 | ||
| 563 | pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 { | |
| 564 | atmel,pins = | |
| c9d0f317 JCPV |
565 | <AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA18 periph A with pullup */ |
| 566 | AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA19 periph A with pullup */ | |
| 567 | AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA20 periph A with pullup */ | |
| d4fe9ac7 JCPV |
568 | }; |
| 569 | ||
| 570 | pinctrl_mmc0_slot0_dat4_7: mmc0_slot0_dat4_7-0 { | |
| 571 | atmel,pins = | |
| c9d0f317 JCPV |
572 | <AT91_PIOA 11 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA11 periph B with pullup */ |
| 573 | AT91_PIOA 12 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA12 periph B with pullup */ | |
| 574 | AT91_PIOA 13 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA13 periph B with pullup */ | |
| 575 | AT91_PIOA 14 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PA14 periph B with pullup */ | |
| d4fe9ac7 JCPV |
576 | }; |
| 577 | }; | |
| 578 | ||
| 544ae6b2 BS |
579 | ssc0 { |
| 580 | pinctrl_ssc0_tx: ssc0_tx-0 { | |
| 581 | atmel,pins = | |
| c9d0f317 JCPV |
582 | <AT91_PIOA 24 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA24 periph B */ |
| 583 | AT91_PIOA 25 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA25 periph B */ | |
| 584 | AT91_PIOA 26 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA26 periph B */ | |
| 544ae6b2 BS |
585 | }; |
| 586 | ||
| 587 | pinctrl_ssc0_rx: ssc0_rx-0 { | |
| 588 | atmel,pins = | |
| c9d0f317 JCPV |
589 | <AT91_PIOA 27 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA27 periph B */ |
| 590 | AT91_PIOA 28 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA28 periph B */ | |
| 591 | AT91_PIOA 29 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA29 periph B */ | |
| 544ae6b2 BS |
592 | }; |
| 593 | }; | |
| 594 | ||
| a68b728f WY |
595 | spi0 { |
| 596 | pinctrl_spi0: spi0-0 { | |
| 597 | atmel,pins = | |
| c9d0f317 JCPV |
598 | <AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA11 periph A SPI0_MISO pin */ |
| 599 | AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA12 periph A SPI0_MOSI pin */ | |
| 600 | AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA13 periph A SPI0_SPCK pin */ | |
| a68b728f WY |
601 | }; |
| 602 | }; | |
| 603 | ||
| 604 | spi1 { | |
| 605 | pinctrl_spi1: spi1-0 { | |
| 606 | atmel,pins = | |
| c9d0f317 JCPV |
607 | <AT91_PIOA 21 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA21 periph B SPI1_MISO pin */ |
| 608 | AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA22 periph B SPI1_MOSI pin */ | |
| 609 | AT91_PIOA 23 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA23 periph B SPI1_SPCK pin */ | |
| a68b728f WY |
610 | }; |
| 611 | }; | |
| 612 | ||
| 1f84d27b | 613 | i2c0 { |
| 614 | pinctrl_i2c0: i2c0-0 { | |
| 615 | atmel,pins = | |
| 616 | <AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_NONE | |
| 617 | AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; | |
| 618 | }; | |
| 619 | }; | |
| 620 | ||
| 621 | i2c1 { | |
| 622 | pinctrl_i2c1: i2c1-0 { | |
| 623 | atmel,pins = | |
| 624 | <AT91_PIOC 0 AT91_PERIPH_C AT91_PINCTRL_NONE | |
| 625 | AT91_PIOC 1 AT91_PERIPH_C AT91_PINCTRL_NONE>; | |
| 626 | }; | |
| 627 | }; | |
| 628 | ||
| 028633c2 BB |
629 | tcb0 { |
| 630 | pinctrl_tcb0_tclk0: tcb0_tclk0-0 { | |
| 631 | atmel,pins = <AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_NONE>; | |
| 632 | }; | |
| 633 | ||
| 634 | pinctrl_tcb0_tclk1: tcb0_tclk1-0 { | |
| 635 | atmel,pins = <AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_NONE>; | |
| 636 | }; | |
| 637 | ||
| 638 | pinctrl_tcb0_tclk2: tcb0_tclk2-0 { | |
| 639 | atmel,pins = <AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_NONE>; | |
| 640 | }; | |
| 641 | ||
| 642 | pinctrl_tcb0_tioa0: tcb0_tioa0-0 { | |
| 643 | atmel,pins = <AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; | |
| 644 | }; | |
| 645 | ||
| 646 | pinctrl_tcb0_tioa1: tcb0_tioa1-0 { | |
| 647 | atmel,pins = <AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_NONE>; | |
| 648 | }; | |
| 649 | ||
| 650 | pinctrl_tcb0_tioa2: tcb0_tioa2-0 { | |
| 651 | atmel,pins = <AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; | |
| 652 | }; | |
| 653 | ||
| 654 | pinctrl_tcb0_tiob0: tcb0_tiob0-0 { | |
| 655 | atmel,pins = <AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; | |
| 656 | }; | |
| 657 | ||
| 658 | pinctrl_tcb0_tiob1: tcb0_tiob1-0 { | |
| 659 | atmel,pins = <AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_NONE>; | |
| 660 | }; | |
| 661 | ||
| 662 | pinctrl_tcb0_tiob2: tcb0_tiob2-0 { | |
| 663 | atmel,pins = <AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_NONE>; | |
| 664 | }; | |
| 665 | }; | |
| 666 | ||
| 667 | tcb1 { | |
| 668 | pinctrl_tcb1_tclk0: tcb1_tclk0-0 { | |
| 669 | atmel,pins = <AT91_PIOC 4 AT91_PERIPH_C AT91_PINCTRL_NONE>; | |
| 670 | }; | |
| 671 | ||
| 672 | pinctrl_tcb1_tclk1: tcb1_tclk1-0 { | |
| 673 | atmel,pins = <AT91_PIOC 7 AT91_PERIPH_C AT91_PINCTRL_NONE>; | |
| 674 | }; | |
| 675 | ||
| 676 | pinctrl_tcb1_tclk2: tcb1_tclk2-0 { | |
| 677 | atmel,pins = <AT91_PIOC 14 AT91_PERIPH_C AT91_PINCTRL_NONE>; | |
| 678 | }; | |
| 679 | ||
| 680 | pinctrl_tcb1_tioa0: tcb1_tioa0-0 { | |
| 681 | atmel,pins = <AT91_PIOC 2 AT91_PERIPH_C AT91_PINCTRL_NONE>; | |
| 682 | }; | |
| 683 | ||
| 684 | pinctrl_tcb1_tioa1: tcb1_tioa1-0 { | |
| 685 | atmel,pins = <AT91_PIOC 5 AT91_PERIPH_C AT91_PINCTRL_NONE>; | |
| 686 | }; | |
| 687 | ||
| 688 | pinctrl_tcb1_tioa2: tcb1_tioa2-0 { | |
| 689 | atmel,pins = <AT91_PIOC 12 AT91_PERIPH_C AT91_PINCTRL_NONE>; | |
| 690 | }; | |
| 691 | ||
| 692 | pinctrl_tcb1_tiob0: tcb1_tiob0-0 { | |
| 693 | atmel,pins = <AT91_PIOC 3 AT91_PERIPH_C AT91_PINCTRL_NONE>; | |
| 694 | }; | |
| 695 | ||
| 696 | pinctrl_tcb1_tiob1: tcb1_tiob1-0 { | |
| 697 | atmel,pins = <AT91_PIOC 6 AT91_PERIPH_C AT91_PINCTRL_NONE>; | |
| 698 | }; | |
| 699 | ||
| 700 | pinctrl_tcb1_tiob2: tcb1_tiob2-0 { | |
| 701 | atmel,pins = <AT91_PIOC 13 AT91_PERIPH_C AT91_PINCTRL_NONE>; | |
| a68b728f WY |
702 | }; |
| 703 | }; | |
| 704 | ||
| e4541ff2 JCPV |
705 | pioA: gpio@fffff400 { |
| 706 | compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; | |
| 707 | reg = <0xfffff400 0x200>; | |
| 5e8b3bc3 | 708 | interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; |
| e4541ff2 JCPV |
709 | #gpio-cells = <2>; |
| 710 | gpio-controller; | |
| 711 | interrupt-controller; | |
| 712 | #interrupt-cells = <2>; | |
| 68f1938e | 713 | clocks = <&pioAB_clk>; |
| e4541ff2 JCPV |
714 | }; |
| 715 | ||
| 716 | pioB: gpio@fffff600 { | |
| 717 | compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; | |
| 718 | reg = <0xfffff600 0x200>; | |
| 5e8b3bc3 | 719 | interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; |
| e4541ff2 JCPV |
720 | #gpio-cells = <2>; |
| 721 | gpio-controller; | |
| 722 | interrupt-controller; | |
| 723 | #interrupt-cells = <2>; | |
| 68f1938e | 724 | clocks = <&pioAB_clk>; |
| e4541ff2 JCPV |
725 | }; |
| 726 | ||
| 727 | pioC: gpio@fffff800 { | |
| 728 | compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; | |
| 729 | reg = <0xfffff800 0x200>; | |
| 5e8b3bc3 | 730 | interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; |
| e4541ff2 JCPV |
731 | #gpio-cells = <2>; |
| 732 | gpio-controller; | |
| 733 | interrupt-controller; | |
| 734 | #interrupt-cells = <2>; | |
| 68f1938e | 735 | clocks = <&pioCD_clk>; |
| e4541ff2 JCPV |
736 | }; |
| 737 | ||
| 738 | pioD: gpio@fffffa00 { | |
| 739 | compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; | |
| 740 | reg = <0xfffffa00 0x200>; | |
| 5e8b3bc3 | 741 | interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; |
| e4541ff2 JCPV |
742 | #gpio-cells = <2>; |
| 743 | gpio-controller; | |
| 744 | interrupt-controller; | |
| 745 | #interrupt-cells = <2>; | |
| 68f1938e | 746 | clocks = <&pioCD_clk>; |
| e4541ff2 | 747 | }; |
| cce783c6 HX |
748 | }; |
| 749 | ||
| 750 | dbgu: serial@fffff200 { | |
| 751 | compatible = "atmel,at91sam9260-usart"; | |
| 752 | reg = <0xfffff200 0x200>; | |
| 5e8b3bc3 | 753 | interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; |
| ec6754a7 JCPV |
754 | pinctrl-names = "default"; |
| 755 | pinctrl-0 = <&pinctrl_dbgu>; | |
| 68f1938e BB |
756 | clocks = <&mck>; |
| 757 | clock-names = "usart"; | |
| cce783c6 HX |
758 | status = "disabled"; |
| 759 | }; | |
| 760 | ||
| 544ae6b2 BS |
761 | ssc0: ssc@f0010000 { |
| 762 | compatible = "atmel,at91sam9g45-ssc"; | |
| 763 | reg = <0xf0010000 0x4000>; | |
| 5e8b3bc3 | 764 | interrupts = <28 IRQ_TYPE_LEVEL_HIGH 5>; |
| ffcd77e2 BS |
765 | dmas = <&dma 0 AT91_DMA_CFG_PER_ID(21)>, |
| 766 | <&dma 0 AT91_DMA_CFG_PER_ID(22)>; | |
| 767 | dma-names = "tx", "rx"; | |
| 544ae6b2 BS |
768 | pinctrl-names = "default"; |
| 769 | pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; | |
| 68f1938e BB |
770 | clocks = <&ssc0_clk>; |
| 771 | clock-names = "pclk"; | |
| 544ae6b2 BS |
772 | status = "disabled"; |
| 773 | }; | |
| 774 | ||
| cce783c6 HX |
775 | usart0: serial@f801c000 { |
| 776 | compatible = "atmel,at91sam9260-usart"; | |
| 777 | reg = <0xf801c000 0x4000>; | |
| 5e8b3bc3 | 778 | interrupts = <5 IRQ_TYPE_LEVEL_HIGH 5>; |
| ec6754a7 | 779 | pinctrl-names = "default"; |
| 9e3129e9 | 780 | pinctrl-0 = <&pinctrl_usart0>; |
| 68f1938e BB |
781 | clocks = <&usart0_clk>; |
| 782 | clock-names = "usart"; | |
| cce783c6 HX |
783 | status = "disabled"; |
| 784 | }; | |
| 785 | ||
| 786 | usart1: serial@f8020000 { | |
| 787 | compatible = "atmel,at91sam9260-usart"; | |
| 788 | reg = <0xf8020000 0x4000>; | |
| 5e8b3bc3 | 789 | interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>; |
| ec6754a7 | 790 | pinctrl-names = "default"; |
| 9e3129e9 | 791 | pinctrl-0 = <&pinctrl_usart1>; |
| 68f1938e BB |
792 | clocks = <&usart1_clk>; |
| 793 | clock-names = "usart"; | |
| cce783c6 HX |
794 | status = "disabled"; |
| 795 | }; | |
| 796 | ||
| 797 | usart2: serial@f8024000 { | |
| 798 | compatible = "atmel,at91sam9260-usart"; | |
| 799 | reg = <0xf8024000 0x4000>; | |
| 5e8b3bc3 | 800 | interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>; |
| ec6754a7 | 801 | pinctrl-names = "default"; |
| 9e3129e9 | 802 | pinctrl-0 = <&pinctrl_usart2>; |
| 68f1938e BB |
803 | clocks = <&usart2_clk>; |
| 804 | clock-names = "usart"; | |
| cce783c6 HX |
805 | status = "disabled"; |
| 806 | }; | |
| 807 | ||
| 808 | usart3: serial@f8028000 { | |
| 809 | compatible = "atmel,at91sam9260-usart"; | |
| 810 | reg = <0xf8028000 0x4000>; | |
| 5e8b3bc3 | 811 | interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>; |
| ec6754a7 | 812 | pinctrl-names = "default"; |
| 9e3129e9 | 813 | pinctrl-0 = <&pinctrl_usart3>; |
| 68f1938e BB |
814 | clocks = <&usart3_clk>; |
| 815 | clock-names = "usart"; | |
| cce783c6 HX |
816 | status = "disabled"; |
| 817 | }; | |
| 05dcd361 LD |
818 | |
| 819 | i2c0: i2c@f8010000 { | |
| 820 | compatible = "atmel,at91sam9x5-i2c"; | |
| 821 | reg = <0xf8010000 0x100>; | |
| 5e8b3bc3 | 822 | interrupts = <9 IRQ_TYPE_LEVEL_HIGH 6>; |
| d4ae89c8 LD |
823 | dmas = <&dma 1 AT91_DMA_CFG_PER_ID(13)>, |
| 824 | <&dma 1 AT91_DMA_CFG_PER_ID(14)>; | |
| d9a63a45 | 825 | dma-names = "tx", "rx"; |
| 05dcd361 LD |
826 | #address-cells = <1>; |
| 827 | #size-cells = <0>; | |
| 1f84d27b | 828 | pinctrl-names = "default"; |
| 829 | pinctrl-0 = <&pinctrl_i2c0>; | |
| 68f1938e | 830 | clocks = <&twi0_clk>; |
| 05dcd361 LD |
831 | status = "disabled"; |
| 832 | }; | |
| 833 | ||
| 834 | i2c1: i2c@f8014000 { | |
| 835 | compatible = "atmel,at91sam9x5-i2c"; | |
| 836 | reg = <0xf8014000 0x100>; | |
| 5e8b3bc3 | 837 | interrupts = <10 IRQ_TYPE_LEVEL_HIGH 6>; |
| d4ae89c8 LD |
838 | dmas = <&dma 1 AT91_DMA_CFG_PER_ID(15)>, |
| 839 | <&dma 1 AT91_DMA_CFG_PER_ID(16)>; | |
| d9a63a45 | 840 | dma-names = "tx", "rx"; |
| 05dcd361 LD |
841 | #address-cells = <1>; |
| 842 | #size-cells = <0>; | |
| 1f84d27b | 843 | pinctrl-names = "default"; |
| 844 | pinctrl-0 = <&pinctrl_i2c1>; | |
| 68f1938e | 845 | clocks = <&twi1_clk>; |
| 05dcd361 LD |
846 | status = "disabled"; |
| 847 | }; | |
| d50f88a0 RG |
848 | |
| 849 | spi0: spi@f0000000 { | |
| 850 | #address-cells = <1>; | |
| 851 | #size-cells = <0>; | |
| 852 | compatible = "atmel,at91rm9200-spi"; | |
| 853 | reg = <0xf0000000 0x100>; | |
| 5e8b3bc3 | 854 | interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>; |
| c07b000f NF |
855 | dmas = <&dma 1 AT91_DMA_CFG_PER_ID(1)>, |
| 856 | <&dma 1 AT91_DMA_CFG_PER_ID(2)>; | |
| 857 | dma-names = "tx", "rx"; | |
| a68b728f WY |
858 | pinctrl-names = "default"; |
| 859 | pinctrl-0 = <&pinctrl_spi0>; | |
| 68f1938e BB |
860 | clocks = <&spi0_clk>; |
| 861 | clock-names = "spi_clk"; | |
| d50f88a0 RG |
862 | status = "disabled"; |
| 863 | }; | |
| 864 | ||
| 865 | spi1: spi@f0004000 { | |
| 866 | #address-cells = <1>; | |
| 867 | #size-cells = <0>; | |
| 868 | compatible = "atmel,at91rm9200-spi"; | |
| 869 | reg = <0xf0004000 0x100>; | |
| 5e8b3bc3 | 870 | interrupts = <14 IRQ_TYPE_LEVEL_HIGH 3>; |
| c07b000f NF |
871 | dmas = <&dma 1 AT91_DMA_CFG_PER_ID(3)>, |
| 872 | <&dma 1 AT91_DMA_CFG_PER_ID(4)>; | |
| 873 | dma-names = "tx", "rx"; | |
| a68b728f WY |
874 | pinctrl-names = "default"; |
| 875 | pinctrl-0 = <&pinctrl_spi1>; | |
| 68f1938e BB |
876 | clocks = <&spi1_clk>; |
| 877 | clock-names = "spi_clk"; | |
| d50f88a0 RG |
878 | status = "disabled"; |
| 879 | }; | |
| 136d3556 WY |
880 | |
| 881 | watchdog@fffffe40 { | |
| 882 | compatible = "atmel,at91sam9260-wdt"; | |
| 883 | reg = <0xfffffe40 0x10>; | |
| fe46aa67 BB |
884 | interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; |
| 885 | atmel,watchdog-type = "hardware"; | |
| 886 | atmel,reset-type = "all"; | |
| 887 | atmel,dbg-halt; | |
| 888 | atmel,idle-halt; | |
| 136d3556 WY |
889 | status = "disabled"; |
| 890 | }; | |
| f3ab0527 BS |
891 | |
| 892 | pwm0: pwm@f8034000 { | |
| 893 | compatible = "atmel,at91sam9rl-pwm"; | |
| 894 | reg = <0xf8034000 0x300>; | |
| 895 | interrupts = <18 IRQ_TYPE_LEVEL_HIGH 4>; | |
| 896 | #pwm-cells = <3>; | |
| 68f1938e | 897 | clocks = <&pwm_clk>; |
| f3ab0527 BS |
898 | status = "disabled"; |
| 899 | }; | |
| cce783c6 HX |
900 | }; |
| 901 | ||
| 902 | nand0: nand@40000000 { | |
| 903 | compatible = "atmel,at91rm9200-nand"; | |
| 904 | #address-cells = <1>; | |
| 905 | #size-cells = <1>; | |
| 906 | reg = < 0x40000000 0x10000000 | |
| 907 | 0xffffe000 0x00000600 | |
| 908 | 0xffffe600 0x00000200 | |
| c18c6b29 | 909 | 0x00108000 0x00018000 |
| cce783c6 | 910 | >; |
| c18c6b29 | 911 | atmel,pmecc-lookup-table-offset = <0x0 0x8000>; |
| cce783c6 HX |
912 | atmel,nand-addr-offset = <21>; |
| 913 | atmel,nand-cmd-offset = <22>; | |
| e8b2da6e | 914 | atmel,nand-has-dma; |
| 7a38d450 JCPV |
915 | pinctrl-names = "default"; |
| 916 | pinctrl-0 = <&pinctrl_nand>; | |
| 92f8629b JCPV |
917 | gpios = <&pioD 5 GPIO_ACTIVE_HIGH |
| 918 | &pioD 4 GPIO_ACTIVE_HIGH | |
| cce783c6 HX |
919 | 0 |
| 920 | >; | |
| 921 | status = "disabled"; | |
| 922 | }; | |
| 923 | ||
| 924 | usb0: ohci@00500000 { | |
| 925 | compatible = "atmel,at91rm9200-ohci", "usb-ohci"; | |
| 926 | reg = <0x00500000 0x00100000>; | |
| 5e8b3bc3 | 927 | interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; |
| 68f1938e BB |
928 | clocks = <&usb>, <&uhphs_clk>, <&udphs_clk>, |
| 929 | <&uhpck>; | |
| 930 | clock-names = "usb_clk", "ohci_clk", "hclk", "uhpck"; | |
| cce783c6 HX |
931 | status = "disabled"; |
| 932 | }; | |
| 933 | }; | |
| 934 | ||
| 935 | i2c@0 { | |
| 936 | compatible = "i2c-gpio"; | |
| 92f8629b JCPV |
937 | gpios = <&pioA 30 GPIO_ACTIVE_HIGH /* sda */ |
| 938 | &pioA 31 GPIO_ACTIVE_HIGH /* scl */ | |
| cce783c6 HX |
939 | >; |
| 940 | i2c-gpio,sda-open-drain; | |
| 941 | i2c-gpio,scl-open-drain; | |
| 942 | i2c-gpio,delay-us = <2>; /* ~100 kHz */ | |
| 943 | #address-cells = <1>; | |
| 944 | #size-cells = <0>; | |
| 945 | status = "disabled"; | |
| 946 | }; | |
| 947 | }; |