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ARM: at91/dt: at91rm9200ek: enable RTC
[deliverable/linux.git] / arch / arm / boot / dts / at91sam9n12.dtsi
CommitLineData
cce783c6
HX		 1/*
2 * at91sam9n12.dtsi - Device Tree include file for AT91SAM9N12 SoC
3 *
4 * Copyright (C) 2012 Atmel,
5 * 2012 Hong Xu <hong.xu@atmel.com>
6 *
7 * Licensed under GPLv2 or later.
8 */
9
6db64d29 10#include "skeleton.dtsi"
d4ae89c8 11#include <dt-bindings/dma/at91.h>
c9d0f317 12#include <dt-bindings/pinctrl/at91.h>
5e8b3bc3 13#include <dt-bindings/interrupt-controller/irq.h>
92f8629b 14#include <dt-bindings/gpio/gpio.h>
68f1938e 15#include <dt-bindings/clock/at91.h>
cce783c6
HX		 16
17/ {
18 model = "Atmel AT91SAM9N12 SoC";
19 compatible = "atmel,at91sam9n12";
20 interrupt-parent = <&aic>;
21
22 aliases {
23 serial0 = &dbgu;
24 serial1 = &usart0;
25 serial2 = &usart1;
26 serial3 = &usart2;
27 serial4 = &usart3;
28 gpio0 = &pioA;
29 gpio1 = &pioB;
30 gpio2 = &pioC;
31 gpio3 = &pioD;
32 tcb0 = &tcb0;
33 tcb1 = &tcb1;
05dcd361
LD		 34 i2c0 = &i2c0;
35 i2c1 = &i2c1;
544ae6b2 36 ssc0 = &ssc0;
f3ab0527 37 pwm0 = &pwm0;
cce783c6
HX		 38 };
39 cpus {
e757a6ee
LP		 40 #address-cells = <0>;
41 #size-cells = <0>;
42
43 cpu {
44 compatible = "arm,arm926ej-s";
45 device_type = "cpu";
cce783c6
HX		 46 };
47 };
48
49 memory {
50 reg = <0x20000000 0x10000000>;
51 };
52
6503ab5f
AB		 53 clocks {
54 slow_xtal: slow_xtal {
55 compatible = "fixed-clock";
56 #clock-cells = <0>;
57 clock-frequency = <0>;
58 };
68f1938e 59
6503ab5f
AB		 60 main_xtal: main_xtal {
61 compatible = "fixed-clock";
62 #clock-cells = <0>;
63 clock-frequency = <0>;
64 };
68f1938e
BB		 65 };
66
cce783c6
HX		 67 ahb {
68 compatible = "simple-bus";
69 #address-cells = <1>;
70 #size-cells = <1>;
71 ranges;
72
73 apb {
74 compatible = "simple-bus";
75 #address-cells = <1>;
76 #size-cells = <1>;
77 ranges;
78
79 aic: interrupt-controller@fffff000 {
f8a073ee 80 #interrupt-cells = <3>;
cce783c6
HX		 81 compatible = "atmel,at91rm9200-aic";
82 interrupt-controller;
83 reg = <0xfffff000 0x200>;
029efdda 84 atmel,external-irqs = <31>;
cce783c6
HX		 85 };
86
87 ramc0: ramc@ffffe800 {
88 compatible = "atmel,at91sam9g45-ddramc";
89 reg = <0xffffe800 0x200>;
7e948346
AB		 90 clocks = <&ddrck>;
91 clock-names = "ddrck";
cce783c6
HX		 92 };
93
94 pmc: pmc@fffffc00 {
68f1938e
BB		 95 compatible = "atmel,at91sam9n12-pmc";
96 reg = <0xfffffc00 0x200>;
97 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
98 interrupt-controller;
99 #address-cells = <1>;
100 #size-cells = <0>;
101 #interrupt-cells = <1>;
102
103 main_rc_osc: main_rc_osc {
104 compatible = "atmel,at91sam9x5-clk-main-rc-osc";
105 #clock-cells = <0>;
106 interrupts-extended = <&pmc AT91_PMC_MOSCRCS>;
107 clock-frequency = <12000000>;
108 clock-accuracy = <50000000>;
109 };
110
111 main_osc: main_osc {
112 compatible = "atmel,at91rm9200-clk-main-osc";
113 #clock-cells = <0>;
114 interrupts-extended = <&pmc AT91_PMC_MOSCS>;
115 clocks = <&main_xtal>;
116 };
117
118 main: mainck {
119 compatible = "atmel,at91sam9x5-clk-main";
120 #clock-cells = <0>;
121 interrupts-extended = <&pmc AT91_PMC_MOSCSELS>;
122 clocks = <&main_rc_osc>, <&main_osc>;
123 };
124
125 plla: pllack {
126 compatible = "atmel,at91rm9200-clk-pll";
127 #clock-cells = <0>;
128 interrupts-extended = <&pmc AT91_PMC_LOCKA>;
129 clocks = <&main>;
130 reg = <0>;
131 atmel,clk-input-range = <2000000 32000000>;
132 #atmel,pll-clk-output-range-cells = <4>;
133 atmel,pll-clk-output-ranges = <745000000 800000000 0 0>,
134 <695000000 750000000 1 0>,
135 <645000000 700000000 2 0>,
136 <595000000 650000000 3 0>,
137 <545000000 600000000 0 1>,
138 <495000000 555000000 1 1>,
8cbff69c
AB		 139 <445000000 500000000 2 1>,
140 <400000000 450000000 3 1>;
68f1938e
BB		 141 };
142
143 plladiv: plladivck {
144 compatible = "atmel,at91sam9x5-clk-plldiv";
145 #clock-cells = <0>;
146 clocks = <&plla>;
147 };
148
149 pllb: pllbck {
150 compatible = "atmel,at91rm9200-clk-pll";
151 #clock-cells = <0>;
152 interrupts-extended = <&pmc AT91_PMC_LOCKB>;
153 clocks = <&main>;
154 reg = <1>;
155 atmel,clk-input-range = <2000000 32000000>;
156 #atmel,pll-clk-output-range-cells = <3>;
157 atmel,pll-clk-output-ranges = <30000000 100000000 0>;
158 };
159
160 mck: masterck {
161 compatible = "atmel,at91sam9x5-clk-master";
162 #clock-cells = <0>;
163 interrupts-extended = <&pmc AT91_PMC_MCKRDY>;
164 clocks = <&clk32k>, <&main>, <&plladiv>, <&pllb>;
165 atmel,clk-output-range = <0 133333333>;
166 atmel,clk-divisors = <1 2 4 3>;
167 atmel,master-clk-have-div3-pres;
168 };
169
170 usb: usbck {
171 compatible = "atmel,at91sam9n12-clk-usb";
172 #clock-cells = <0>;
173 clocks = <&pllb>;
174 };
175
176 prog: progck {
177 compatible = "atmel,at91sam9x5-clk-programmable";
178 #address-cells = <1>;
179 #size-cells = <0>;
180 interrupt-parent = <&pmc>;
181 clocks = <&clk32k>, <&main>, <&plladiv>, <&pllb>, <&mck>;
182
183 prog0: prog0 {
184 #clock-cells = <0>;
185 reg = <0>;
186 interrupts = <AT91_PMC_PCKRDY(0)>;
187 };
188
189 prog1: prog1 {
190 #clock-cells = <0>;
191 reg = <1>;
192 interrupts = <AT91_PMC_PCKRDY(1)>;
193 };
194 };
195
196 systemck {
197 compatible = "atmel,at91rm9200-clk-system";
198 #address-cells = <1>;
199 #size-cells = <0>;
200
201 ddrck: ddrck {
202 #clock-cells = <0>;
203 reg = <2>;
204 clocks = <&mck>;
205 };
206
207 lcdck: lcdck {
208 #clock-cells = <0>;
209 reg = <3>;
210 clocks = <&mck>;
211 };
212
213 uhpck: uhpck {
214 #clock-cells = <0>;
215 reg = <6>;
216 clocks = <&usb>;
217 };
218
219 udpck: udpck {
220 #clock-cells = <0>;
221 reg = <7>;
222 clocks = <&usb>;
223 };
224
225 pck0: pck0 {
226 #clock-cells = <0>;
227 reg = <8>;
228 clocks = <&prog0>;
229 };
230
231 pck1: pck1 {
232 #clock-cells = <0>;
233 reg = <9>;
234 clocks = <&prog1>;
235 };
236 };
237
238 periphck {
239 compatible = "atmel,at91sam9x5-clk-peripheral";
240 #address-cells = <1>;
241 #size-cells = <0>;
242 clocks = <&mck>;
243
244 pioAB_clk: pioAB_clk {
245 #clock-cells = <0>;
246 reg = <2>;
247 };
248
249 pioCD_clk: pioCD_clk {
250 #clock-cells = <0>;
251 reg = <3>;
252 };
253
254 fuse_clk: fuse_clk {
255 #clock-cells = <0>;
256 reg = <4>;
257 };
258
259 usart0_clk: usart0_clk {
260 #clock-cells = <0>;
261 reg = <5>;
262 };
263
264 usart1_clk: usart1_clk {
265 #clock-cells = <0>;
266 reg = <6>;
267 };
268
269 usart2_clk: usart2_clk {
270 #clock-cells = <0>;
271 reg = <7>;
272 };
273
274 usart3_clk: usart3_clk {
275 #clock-cells = <0>;
276 reg = <8>;
277 };
278
279 twi0_clk: twi0_clk {
280 reg = <9>;
281 #clock-cells = <0>;
282 };
283
284 twi1_clk: twi1_clk {
285 #clock-cells = <0>;
286 reg = <10>;
287 };
288
289 mci0_clk: mci0_clk {
290 #clock-cells = <0>;
291 reg = <12>;
292 };
293
294 spi0_clk: spi0_clk {
295 #clock-cells = <0>;
296 reg = <13>;
297 };
298
299 spi1_clk: spi1_clk {
300 #clock-cells = <0>;
301 reg = <14>;
302 };
303
304 uart0_clk: uart0_clk {
305 #clock-cells = <0>;
306 reg = <15>;
307 };
308
309 uart1_clk: uart1_clk {
310 #clock-cells = <0>;
311 reg = <16>;
312 };
313
314 tcb_clk: tcb_clk {
315 #clock-cells = <0>;
316 reg = <17>;
317 };
318
319 pwm_clk: pwm_clk {
320 #clock-cells = <0>;
321 reg = <18>;
322 };
323
324 adc_clk: adc_clk {
325 #clock-cells = <0>;
326 reg = <19>;
327 };
328
329 dma0_clk: dma0_clk {
330 #clock-cells = <0>;
331 reg = <20>;
332 };
333
334 uhphs_clk: uhphs_clk {
335 #clock-cells = <0>;
336 reg = <22>;
337 };
338
339 udphs_clk: udphs_clk {
340 #clock-cells = <0>;
341 reg = <23>;
342 };
343
344 lcdc_clk: lcdc_clk {
345 #clock-cells = <0>;
346 reg = <25>;
347 };
348
349 sha_clk: sha_clk {
350 #clock-cells = <0>;
351 reg = <27>;
352 };
353
354 ssc0_clk: ssc0_clk {
355 #clock-cells = <0>;
356 reg = <28>;
357 };
358
359 aes_clk: aes_clk {
360 #clock-cells = <0>;
361 reg = <29>;
362 };
363
364 trng_clk: trng_clk {
365 #clock-cells = <0>;
366 reg = <30>;
367 };
368 };
cce783c6
HX		 369 };
370
371 rstc@fffffe00 {
372 compatible = "atmel,at91sam9g45-rstc";
373 reg = <0xfffffe00 0x10>;
374 };
375
376 pit: timer@fffffe30 {
377 compatible = "atmel,at91sam9260-pit";
378 reg = <0xfffffe30 0xf>;
5e8b3bc3 379 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
68f1938e 380 clocks = <&mck>;
cce783c6
HX		 381 };
382
383 shdwc@fffffe10 {
384 compatible = "atmel,at91sam9x5-shdwc";
385 reg = <0xfffffe10 0x10>;
386 };
387
68f1938e
BB		 388 sckc@fffffe50 {
389 compatible = "atmel,at91sam9x5-sckc";
390 reg = <0xfffffe50 0x4>;
391
392 slow_osc: slow_osc {
393 compatible = "atmel,at91sam9x5-clk-slow-osc";
394 #clock-cells = <0>;
395 clocks = <&slow_xtal>;
396 };
397
398 slow_rc_osc: slow_rc_osc {
399 compatible = "atmel,at91sam9x5-clk-slow-rc-osc";
400 #clock-cells = <0>;
401 clock-frequency = <32768>;
402 clock-accuracy = <50000000>;
403 };
404
405 clk32k: slck {
406 compatible = "atmel,at91sam9x5-clk-slow";
407 #clock-cells = <0>;
408 clocks = <&slow_rc_osc>, <&slow_osc>;
409 };
410 };
411
9873137a
LD		 412 mmc0: mmc@f0008000 {
413 compatible = "atmel,hsmci";
414 reg = <0xf0008000 0x600>;
5e8b3bc3 415 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>;
d4ae89c8 416 dmas = <&dma 1 AT91_DMA_CFG_PER_ID(0)>;
05c1bc97 417 dma-names = "rxtx";
68f1938e
BB		 418 clocks = <&mci0_clk>;
419 clock-names = "mci_clk";
9873137a
LD		 420 #address-cells = <1>;
421 #size-cells = <0>;
422 status = "disabled";
423 };
424
cce783c6
HX		 425 tcb0: timer@f8008000 {
426 compatible = "atmel,at91sam9x5-tcb";
427 reg = <0xf8008000 0x100>;
5e8b3bc3 428 interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;
68f1938e
BB		 429 clocks = <&tcb_clk>;
430 clock-names = "t0_clk";
cce783c6
HX		 431 };
432
433 tcb1: timer@f800c000 {
434 compatible = "atmel,at91sam9x5-tcb";
435 reg = <0xf800c000 0x100>;
5e8b3bc3 436 interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;
68f1938e
BB		 437 clocks = <&tcb_clk>;
438 clock-names = "t0_clk";
cce783c6
HX		 439 };
440
441 dma: dma-controller@ffffec00 {
442 compatible = "atmel,at91sam9g45-dma";
443 reg = <0xffffec00 0x200>;
5e8b3bc3 444 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>;
980ce7d9 445 #dma-cells = <2>;
68f1938e
BB		 446 clocks = <&dma0_clk>;
447 clock-names = "dma_clk";
cce783c6
HX		 448 };
449
e4541ff2
JCPV		 450 pinctrl@fffff400 {
451 #address-cells = <1>;
452 #size-cells = <1>;
5314ec8e 453 compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus";
e4541ff2
JCPV		 454 ranges = <0xfffff400 0xfffff400 0x800>;
455
5314ec8e
JCPV		 456 atmel,mux-mask = <
457 /* A B C */
458 0xffffffff 0xffe07983 0x00000000 /* pioA */
459 0x00040000 0x00047e0f 0x00000000 /* pioB */
460 0xfdffffff 0x07c00000 0xb83fffff /* pioC */
461 0x003fffff 0x003f8000 0x00000000 /* pioD */
462 >;
463
464 /* shared pinctrl settings */
ec6754a7
JCPV		 465 dbgu {
466 pinctrl_dbgu: dbgu-0 {
467 atmel,pins =
c9d0f317
JCPV		 468 <AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA9 periph A */
469 AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA10 periph with pullup */
ec6754a7
JCPV		 470 };
471 };
472
9e3129e9
JCPV		 473 usart0 {
474 pinctrl_usart0: usart0-0 {
ec6754a7 475 atmel,pins =
c9d0f317
JCPV		 476 <AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA1 periph A with pullup */
477 AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA0 periph A */
ec6754a7
JCPV		 478 };
479
c58c0c5a 480 pinctrl_usart0_rts: usart0_rts-0 {
ec6754a7 481 atmel,pins =
c9d0f317 482 <AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA2 periph A */
c58c0c5a
JCPV		 483 };
484
485 pinctrl_usart0_cts: usart0_cts-0 {
486 atmel,pins =
c9d0f317 487 <AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA3 periph A */
ec6754a7
JCPV		 488 };
489 };
490
9e3129e9
JCPV		 491 usart1 {
492 pinctrl_usart1: usart1-0 {
ec6754a7 493 atmel,pins =
c9d0f317
JCPV		 494 <AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA6 periph A with pullup */
495 AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA5 periph A */
ec6754a7
JCPV		 496 };
497 };
498
9e3129e9
JCPV		 499 usart2 {
500 pinctrl_usart2: usart2-0 {
ec6754a7 501 atmel,pins =
c9d0f317
JCPV		 502 <AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA8 periph A with pullup */
503 AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA7 periph A */
ec6754a7
JCPV		 504 };
505
c58c0c5a 506 pinctrl_usart2_rts: usart2_rts-0 {
ec6754a7 507 atmel,pins =
c9d0f317 508 <AT91_PIOB 0 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB0 periph B */
c58c0c5a
JCPV		 509 };
510
511 pinctrl_usart2_cts: usart2_cts-0 {
512 atmel,pins =
c9d0f317 513 <AT91_PIOB 1 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB1 periph B */
ec6754a7
JCPV		 514 };
515 };
516
9e3129e9
JCPV		 517 usart3 {
518 pinctrl_usart3: usart3-0 {
ec6754a7 519 atmel,pins =
c9d0f317
JCPV		 520 <AT91_PIOC 23 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PC23 periph B with pullup */
521 AT91_PIOC 22 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC22 periph B */
ec6754a7
JCPV		 522 };
523
c58c0c5a
JCPV		 524 pinctrl_usart3_rts: usart3_rts-0 {
525 atmel,pins =
c9d0f317 526 <AT91_PIOC 24 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC24 periph B */
c58c0c5a
JCPV		 527 };
528
529 pinctrl_usart3_cts: usart3_cts-0 {
ec6754a7 530 atmel,pins =
c9d0f317 531 <AT91_PIOC 25 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC25 periph B */
ec6754a7
JCPV		 532 };
533 };
534
9e3129e9
JCPV		 535 uart0 {
536 pinctrl_uart0: uart0-0 {
ec6754a7 537 atmel,pins =
c9d0f317
JCPV		 538 <AT91_PIOC 9 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* PC9 periph C with pullup */
539 AT91_PIOC 8 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC8 periph C */
ec6754a7
JCPV		 540 };
541 };
542
9e3129e9
JCPV		 543 uart1 {
544 pinctrl_uart1: uart1-0 {
ec6754a7 545 atmel,pins =
c9d0f317
JCPV		 546 <AT91_PIOC 16 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* PC17 periph C with pullup */
547 AT91_PIOC 17 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC16 periph C */
ec6754a7
JCPV		 548 };
549 };
5314ec8e 550
7a38d450
JCPV		 551 nand {
552 pinctrl_nand: nand-0 {
553 atmel,pins =
c9d0f317
JCPV		 554 <AT91_PIOD 5 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP /* PD5 gpio RDY pin pull_up*/
555 AT91_PIOD 4 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>; /* PD4 gpio enable pin pull_up */
7a38d450
JCPV		 556 };
557 };
558
d4fe9ac7
JCPV		 559 mmc0 {
560 pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 {
561 atmel,pins =
c9d0f317
JCPV		 562 <AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA17 periph A */
563 AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA16 periph A with pullup */
564 AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA15 periph A with pullup */
d4fe9ac7
JCPV		 565 };
566
567 pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
568 atmel,pins =
c9d0f317
JCPV		 569 <AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA18 periph A with pullup */
570 AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA19 periph A with pullup */
571 AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA20 periph A with pullup */
d4fe9ac7
JCPV		 572 };
573
574 pinctrl_mmc0_slot0_dat4_7: mmc0_slot0_dat4_7-0 {
575 atmel,pins =
c9d0f317
JCPV		 576 <AT91_PIOA 11 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA11 periph B with pullup */
577 AT91_PIOA 12 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA12 periph B with pullup */
578 AT91_PIOA 13 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA13 periph B with pullup */
579 AT91_PIOA 14 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PA14 periph B with pullup */
d4fe9ac7
JCPV		 580 };
581 };
582
544ae6b2
BS		 583 ssc0 {
584 pinctrl_ssc0_tx: ssc0_tx-0 {
585 atmel,pins =
c9d0f317
JCPV		 586 <AT91_PIOA 24 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA24 periph B */
587 AT91_PIOA 25 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA25 periph B */
588 AT91_PIOA 26 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA26 periph B */
544ae6b2
BS		 589 };
590
591 pinctrl_ssc0_rx: ssc0_rx-0 {
592 atmel,pins =
c9d0f317
JCPV		 593 <AT91_PIOA 27 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA27 periph B */
594 AT91_PIOA 28 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA28 periph B */
595 AT91_PIOA 29 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA29 periph B */
544ae6b2
BS		 596 };
597 };
598
a68b728f
WY		 599 spi0 {
600 pinctrl_spi0: spi0-0 {
601 atmel,pins =
c9d0f317
JCPV		 602 <AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA11 periph A SPI0_MISO pin */
603 AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA12 periph A SPI0_MOSI pin */
604 AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA13 periph A SPI0_SPCK pin */
a68b728f
WY		 605 };
606 };
607
608 spi1 {
609 pinctrl_spi1: spi1-0 {
610 atmel,pins =
c9d0f317
JCPV		 611 <AT91_PIOA 21 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA21 periph B SPI1_MISO pin */
612 AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA22 periph B SPI1_MOSI pin */
613 AT91_PIOA 23 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA23 periph B SPI1_SPCK pin */
a68b728f
WY		 614 };
615 };
616
1f84d27b 617 i2c0 {
618 pinctrl_i2c0: i2c0-0 {
619 atmel,pins =
620 <AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_NONE
621 AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_NONE>;
622 };
623 };
624
625 i2c1 {
626 pinctrl_i2c1: i2c1-0 {
627 atmel,pins =
628 <AT91_PIOC 0 AT91_PERIPH_C AT91_PINCTRL_NONE
629 AT91_PIOC 1 AT91_PERIPH_C AT91_PINCTRL_NONE>;
630 };
631 };
632
028633c2
BB		 633 tcb0 {
634 pinctrl_tcb0_tclk0: tcb0_tclk0-0 {
635 atmel,pins = <AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_NONE>;
636 };
637
638 pinctrl_tcb0_tclk1: tcb0_tclk1-0 {
639 atmel,pins = <AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_NONE>;
640 };
641
642 pinctrl_tcb0_tclk2: tcb0_tclk2-0 {
643 atmel,pins = <AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_NONE>;
644 };
645
646 pinctrl_tcb0_tioa0: tcb0_tioa0-0 {
647 atmel,pins = <AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE>;
648 };
649
650 pinctrl_tcb0_tioa1: tcb0_tioa1-0 {
651 atmel,pins = <AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_NONE>;
652 };
653
654 pinctrl_tcb0_tioa2: tcb0_tioa2-0 {
655 atmel,pins = <AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_NONE>;
656 };
657
658 pinctrl_tcb0_tiob0: tcb0_tiob0-0 {
659 atmel,pins = <AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE>;
660 };
661
662 pinctrl_tcb0_tiob1: tcb0_tiob1-0 {
663 atmel,pins = <AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_NONE>;
664 };
665
666 pinctrl_tcb0_tiob2: tcb0_tiob2-0 {
667 atmel,pins = <AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_NONE>;
668 };
669 };
670
671 tcb1 {
672 pinctrl_tcb1_tclk0: tcb1_tclk0-0 {
673 atmel,pins = <AT91_PIOC 4 AT91_PERIPH_C AT91_PINCTRL_NONE>;
674 };
675
676 pinctrl_tcb1_tclk1: tcb1_tclk1-0 {
677 atmel,pins = <AT91_PIOC 7 AT91_PERIPH_C AT91_PINCTRL_NONE>;
678 };
679
680 pinctrl_tcb1_tclk2: tcb1_tclk2-0 {
681 atmel,pins = <AT91_PIOC 14 AT91_PERIPH_C AT91_PINCTRL_NONE>;
682 };
683
684 pinctrl_tcb1_tioa0: tcb1_tioa0-0 {
685 atmel,pins = <AT91_PIOC 2 AT91_PERIPH_C AT91_PINCTRL_NONE>;
686 };
687
688 pinctrl_tcb1_tioa1: tcb1_tioa1-0 {
689 atmel,pins = <AT91_PIOC 5 AT91_PERIPH_C AT91_PINCTRL_NONE>;
690 };
691
692 pinctrl_tcb1_tioa2: tcb1_tioa2-0 {
693 atmel,pins = <AT91_PIOC 12 AT91_PERIPH_C AT91_PINCTRL_NONE>;
694 };
695
696 pinctrl_tcb1_tiob0: tcb1_tiob0-0 {
697 atmel,pins = <AT91_PIOC 3 AT91_PERIPH_C AT91_PINCTRL_NONE>;
698 };
699
700 pinctrl_tcb1_tiob1: tcb1_tiob1-0 {
701 atmel,pins = <AT91_PIOC 6 AT91_PERIPH_C AT91_PINCTRL_NONE>;
702 };
703
704 pinctrl_tcb1_tiob2: tcb1_tiob2-0 {
705 atmel,pins = <AT91_PIOC 13 AT91_PERIPH_C AT91_PINCTRL_NONE>;
a68b728f
WY		 706 };
707 };
708
e4541ff2
JCPV		 709 pioA: gpio@fffff400 {
710 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
711 reg = <0xfffff400 0x200>;
5e8b3bc3 712 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
e4541ff2
JCPV		 713 #gpio-cells = <2>;
714 gpio-controller;
715 interrupt-controller;
716 #interrupt-cells = <2>;
68f1938e 717 clocks = <&pioAB_clk>;
e4541ff2
JCPV		 718 };
719
720 pioB: gpio@fffff600 {
721 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
722 reg = <0xfffff600 0x200>;
5e8b3bc3 723 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
e4541ff2
JCPV		 724 #gpio-cells = <2>;
725 gpio-controller;
726 interrupt-controller;
727 #interrupt-cells = <2>;
68f1938e 728 clocks = <&pioAB_clk>;
e4541ff2
JCPV		 729 };
730
731 pioC: gpio@fffff800 {
732 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
733 reg = <0xfffff800 0x200>;
5e8b3bc3 734 interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
e4541ff2
JCPV		 735 #gpio-cells = <2>;
736 gpio-controller;
737 interrupt-controller;
738 #interrupt-cells = <2>;
68f1938e 739 clocks = <&pioCD_clk>;
e4541ff2
JCPV		 740 };
741
742 pioD: gpio@fffffa00 {
743 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
744 reg = <0xfffffa00 0x200>;
5e8b3bc3 745 interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
e4541ff2
JCPV		 746 #gpio-cells = <2>;
747 gpio-controller;
748 interrupt-controller;
749 #interrupt-cells = <2>;
68f1938e 750 clocks = <&pioCD_clk>;
e4541ff2 751 };
cce783c6
HX		 752 };
753
754 dbgu: serial@fffff200 {
755 compatible = "atmel,at91sam9260-usart";
756 reg = <0xfffff200 0x200>;
5e8b3bc3 757 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
ec6754a7
JCPV		 758 pinctrl-names = "default";
759 pinctrl-0 = <&pinctrl_dbgu>;
68f1938e
BB		 760 clocks = <&mck>;
761 clock-names = "usart";
cce783c6
HX		 762 status = "disabled";
763 };
764
544ae6b2
BS		 765 ssc0: ssc@f0010000 {
766 compatible = "atmel,at91sam9g45-ssc";
767 reg = <0xf0010000 0x4000>;
5e8b3bc3 768 interrupts = <28 IRQ_TYPE_LEVEL_HIGH 5>;
ffcd77e2
BS		 769 dmas = <&dma 0 AT91_DMA_CFG_PER_ID(21)>,
770 <&dma 0 AT91_DMA_CFG_PER_ID(22)>;
771 dma-names = "tx", "rx";
544ae6b2
BS		 772 pinctrl-names = "default";
773 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
68f1938e
BB		 774 clocks = <&ssc0_clk>;
775 clock-names = "pclk";
544ae6b2
BS		 776 status = "disabled";
777 };
778
cce783c6
HX		 779 usart0: serial@f801c000 {
780 compatible = "atmel,at91sam9260-usart";
781 reg = <0xf801c000 0x4000>;
5e8b3bc3 782 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 5>;
ec6754a7 783 pinctrl-names = "default";
9e3129e9 784 pinctrl-0 = <&pinctrl_usart0>;
68f1938e
BB		 785 clocks = <&usart0_clk>;
786 clock-names = "usart";
cce783c6
HX		 787 status = "disabled";
788 };
789
790 usart1: serial@f8020000 {
791 compatible = "atmel,at91sam9260-usart";
792 reg = <0xf8020000 0x4000>;
5e8b3bc3 793 interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>;
ec6754a7 794 pinctrl-names = "default";
9e3129e9 795 pinctrl-0 = <&pinctrl_usart1>;
68f1938e
BB		 796 clocks = <&usart1_clk>;
797 clock-names = "usart";
cce783c6
HX		 798 status = "disabled";
799 };
800
801 usart2: serial@f8024000 {
802 compatible = "atmel,at91sam9260-usart";
803 reg = <0xf8024000 0x4000>;
5e8b3bc3 804 interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>;
ec6754a7 805 pinctrl-names = "default";
9e3129e9 806 pinctrl-0 = <&pinctrl_usart2>;
68f1938e
BB		 807 clocks = <&usart2_clk>;
808 clock-names = "usart";
cce783c6
HX		 809 status = "disabled";
810 };
811
812 usart3: serial@f8028000 {
813 compatible = "atmel,at91sam9260-usart";
814 reg = <0xf8028000 0x4000>;
5e8b3bc3 815 interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>;
ec6754a7 816 pinctrl-names = "default";
9e3129e9 817 pinctrl-0 = <&pinctrl_usart3>;
68f1938e
BB		 818 clocks = <&usart3_clk>;
819 clock-names = "usart";
cce783c6
HX		 820 status = "disabled";
821 };
05dcd361
LD		 822
823 i2c0: i2c@f8010000 {
824 compatible = "atmel,at91sam9x5-i2c";
825 reg = <0xf8010000 0x100>;
5e8b3bc3 826 interrupts = <9 IRQ_TYPE_LEVEL_HIGH 6>;
d4ae89c8
LD		 827 dmas = <&dma 1 AT91_DMA_CFG_PER_ID(13)>,
828 <&dma 1 AT91_DMA_CFG_PER_ID(14)>;
d9a63a45 829 dma-names = "tx", "rx";
05dcd361
LD		 830 #address-cells = <1>;
831 #size-cells = <0>;
1f84d27b 832 pinctrl-names = "default";
833 pinctrl-0 = <&pinctrl_i2c0>;
68f1938e 834 clocks = <&twi0_clk>;
05dcd361
LD		 835 status = "disabled";
836 };
837
838 i2c1: i2c@f8014000 {
839 compatible = "atmel,at91sam9x5-i2c";
840 reg = <0xf8014000 0x100>;
5e8b3bc3 841 interrupts = <10 IRQ_TYPE_LEVEL_HIGH 6>;
d4ae89c8
LD		 842 dmas = <&dma 1 AT91_DMA_CFG_PER_ID(15)>,
843 <&dma 1 AT91_DMA_CFG_PER_ID(16)>;
d9a63a45 844 dma-names = "tx", "rx";
05dcd361
LD		 845 #address-cells = <1>;
846 #size-cells = <0>;
1f84d27b 847 pinctrl-names = "default";
848 pinctrl-0 = <&pinctrl_i2c1>;
68f1938e 849 clocks = <&twi1_clk>;
05dcd361
LD		 850 status = "disabled";
851 };
d50f88a0
RG		 852
853 spi0: spi@f0000000 {
854 #address-cells = <1>;
855 #size-cells = <0>;
856 compatible = "atmel,at91rm9200-spi";
857 reg = <0xf0000000 0x100>;
5e8b3bc3 858 interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>;
c07b000f
NF		 859 dmas = <&dma 1 AT91_DMA_CFG_PER_ID(1)>,
860 <&dma 1 AT91_DMA_CFG_PER_ID(2)>;
861 dma-names = "tx", "rx";
a68b728f
WY		 862 pinctrl-names = "default";
863 pinctrl-0 = <&pinctrl_spi0>;
68f1938e
BB		 864 clocks = <&spi0_clk>;
865 clock-names = "spi_clk";
d50f88a0
RG		 866 status = "disabled";
867 };
868
869 spi1: spi@f0004000 {
870 #address-cells = <1>;
871 #size-cells = <0>;
872 compatible = "atmel,at91rm9200-spi";
873 reg = <0xf0004000 0x100>;
5e8b3bc3 874 interrupts = <14 IRQ_TYPE_LEVEL_HIGH 3>;
c07b000f
NF		 875 dmas = <&dma 1 AT91_DMA_CFG_PER_ID(3)>,
876 <&dma 1 AT91_DMA_CFG_PER_ID(4)>;
877 dma-names = "tx", "rx";
a68b728f
WY		 878 pinctrl-names = "default";
879 pinctrl-0 = <&pinctrl_spi1>;
68f1938e
BB		 880 clocks = <&spi1_clk>;
881 clock-names = "spi_clk";
d50f88a0
RG		 882 status = "disabled";
883 };
136d3556
WY		 884
885 watchdog@fffffe40 {
886 compatible = "atmel,at91sam9260-wdt";
887 reg = <0xfffffe40 0x10>;
fe46aa67
BB		 888 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
889 atmel,watchdog-type = "hardware";
890 atmel,reset-type = "all";
891 atmel,dbg-halt;
892 atmel,idle-halt;
136d3556
WY		 893 status = "disabled";
894 };
f3ab0527 895
52820d26
AB		 896 rtc@fffffeb0 {
897 compatible = "atmel,at91rm9200-rtc";
898 reg = <0xfffffeb0 0x40>;
899 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
900 status = "disabled";
901 };
902
f3ab0527
BS		 903 pwm0: pwm@f8034000 {
904 compatible = "atmel,at91sam9rl-pwm";
905 reg = <0xf8034000 0x300>;
906 interrupts = <18 IRQ_TYPE_LEVEL_HIGH 4>;
907 #pwm-cells = <3>;
68f1938e 908 clocks = <&pwm_clk>;
f3ab0527
BS		 909 status = "disabled";
910 };
cce783c6
HX		 911 };
912
913 nand0: nand@40000000 {
914 compatible = "atmel,at91rm9200-nand";
915 #address-cells = <1>;
916 #size-cells = <1>;
917 reg = < 0x40000000 0x10000000
918 0xffffe000 0x00000600
919 0xffffe600 0x00000200
c18c6b29 920 0x00108000 0x00018000
cce783c6 921 >;
c18c6b29 922 atmel,pmecc-lookup-table-offset = <0x0 0x8000>;
cce783c6
HX		 923 atmel,nand-addr-offset = <21>;
924 atmel,nand-cmd-offset = <22>;
e8b2da6e 925 atmel,nand-has-dma;
7a38d450
JCPV		 926 pinctrl-names = "default";
927 pinctrl-0 = <&pinctrl_nand>;
92f8629b
JCPV		 928 gpios = <&pioD 5 GPIO_ACTIVE_HIGH
929 &pioD 4 GPIO_ACTIVE_HIGH
cce783c6
HX		 930 0
931 >;
932 status = "disabled";
933 };
934
935 usb0: ohci@00500000 {
936 compatible = "atmel,at91rm9200-ohci", "usb-ohci";
937 reg = <0x00500000 0x00100000>;
5e8b3bc3 938 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
043dfc1b 939 clocks = <&usb>, <&uhphs_clk>, <&uhphs_clk>,
68f1938e
BB		 940 <&uhpck>;
941 clock-names = "usb_clk", "ohci_clk", "hclk", "uhpck";
cce783c6
HX		 942 status = "disabled";
943 };
944 };
945
946 i2c@0 {
947 compatible = "i2c-gpio";
92f8629b
JCPV		 948 gpios = <&pioA 30 GPIO_ACTIVE_HIGH /* sda */
949 &pioA 31 GPIO_ACTIVE_HIGH /* scl */
cce783c6
HX		 950 >;
951 i2c-gpio,sda-open-drain;
952 i2c-gpio,scl-open-drain;
953 i2c-gpio,delay-us = <2>; /* ~100 kHz */
954 #address-cells = <1>;
955 #size-cells = <0>;
956 status = "disabled";
957 };
958};
Linux kernel - Deliverables
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