[deliverable/linux.git] / arch / arm / boot / dts / at91sam9n12.dtsi

/*
 * at91sam9n12.dtsi - Device Tree include file for AT91SAM9N12 SoC
 *
 *  Copyright (C) 2012 Atmel,
 *                2012 Hong Xu <hong.xu@atmel.com>
 *
 * Licensed under GPLv2 or later.
 */

#include "skeleton.dtsi"
#include <dt-bindings/pinctrl/at91.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/gpio/gpio.h>

/ {
	model = "Atmel AT91SAM9N12 SoC";
	compatible = "atmel,at91sam9n12";
	interrupt-parent = <&aic>;

	aliases {
		serial0 = &dbgu;
		serial1 = &usart0;
		serial2 = &usart1;
		serial3 = &usart2;
		serial4 = &usart3;
		gpio0 = &pioA;
		gpio1 = &pioB;
		gpio2 = &pioC;
		gpio3 = &pioD;
		tcb0 = &tcb0;
		tcb1 = &tcb1;
		i2c0 = &i2c0;
		i2c1 = &i2c1;
		ssc0 = &ssc0;
	};
	cpus {
		cpu@0 {
			compatible = "arm,arm926ejs";
		};
	};

	memory {
		reg = <0x20000000 0x10000000>;
	};

	ahb {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		apb {
			compatible = "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

			aic: interrupt-controller@fffff000 {
				#interrupt-cells = <3>;
				compatible = "atmel,at91rm9200-aic";
				interrupt-controller;
				reg = <0xfffff000 0x200>;
			};

			ramc0: ramc@ffffe800 {
				compatible = "atmel,at91sam9g45-ddramc";
				reg = <0xffffe800 0x200>;
			};

			pmc: pmc@fffffc00 {
				compatible = "atmel,at91rm9200-pmc";
				reg = <0xfffffc00 0x100>;
			};

			rstc@fffffe00 {
				compatible = "atmel,at91sam9g45-rstc";
				reg = <0xfffffe00 0x10>;
			};

			pit: timer@fffffe30 {
				compatible = "atmel,at91sam9260-pit";
				reg = <0xfffffe30 0xf>;
				interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
			};

			shdwc@fffffe10 {
				compatible = "atmel,at91sam9x5-shdwc";
				reg = <0xfffffe10 0x10>;
			};

			mmc0: mmc@f0008000 {
				compatible = "atmel,hsmci";
				reg = <0xf0008000 0x600>;
				interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>;
				dmas = <&dma 1 0>;
				dma-names = "rxtx";
				#address-cells = <1>;
				#size-cells = <0>;
				status = "disabled";
			};

			tcb0: timer@f8008000 {
				compatible = "atmel,at91sam9x5-tcb";
				reg = <0xf8008000 0x100>;
				interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;
			};

			tcb1: timer@f800c000 {
				compatible = "atmel,at91sam9x5-tcb";
				reg = <0xf800c000 0x100>;
				interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;
			};

			dma: dma-controller@ffffec00 {
				compatible = "atmel,at91sam9g45-dma";
				reg = <0xffffec00 0x200>;
				interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>;
				#dma-cells = <2>;
			};

			pinctrl@fffff400 {
				#address-cells = <1>;
				#size-cells = <1>;
				compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus";
				ranges = <0xfffff400 0xfffff400 0x800>;

				atmel,mux-mask = <
				      /*    A         B          C     */
				       0xffffffff 0xffe07983 0x00000000  /* pioA */
				       0x00040000 0x00047e0f 0x00000000  /* pioB */
				       0xfdffffff 0x07c00000 0xb83fffff  /* pioC */
				       0x003fffff 0x003f8000 0x00000000  /* pioD */
				      >;

				/* shared pinctrl settings */
				dbgu {
					pinctrl_dbgu: dbgu-0 {
						atmel,pins =
							<AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PA9 periph A */
							 AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;	/* PA10 periph with pullup */
					};
				};

				usart0 {
					pinctrl_usart0: usart0-0 {
						atmel,pins =
							<AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_PULL_UP	/* PA1 periph A with pullup */
							 AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PA0 periph A */
					};

					pinctrl_usart0_rts: usart0_rts-0 {
						atmel,pins =
							<AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PA2 periph A */
					};

					pinctrl_usart0_cts: usart0_cts-0 {
						atmel,pins =
							<AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PA3 periph A */
					};
				};

				usart1 {
					pinctrl_usart1: usart1-0 {
						atmel,pins =
							<AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP	/* PA6 periph A with pullup */
							 AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PA5 periph A */
					};
				};

				usart2 {
					pinctrl_usart2: usart2-0 {
						atmel,pins =
							<AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP	/* PA8 periph A with pullup */
							 AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PA7 periph A */
					};

					pinctrl_usart2_rts: usart2_rts-0 {
						atmel,pins =
							<AT91_PIOB 0 AT91_PERIPH_B AT91_PINCTRL_NONE>;	/* PB0 periph B */
					};

					pinctrl_usart2_cts: usart2_cts-0 {
						atmel,pins =
							<AT91_PIOB 1 AT91_PERIPH_B AT91_PINCTRL_NONE>;	/* PB1 periph B */
					};
				};

				usart3 {
					pinctrl_usart3: usart3-0 {
						atmel,pins =
							<AT91_PIOC 23 AT91_PERIPH_B AT91_PINCTRL_PULL_UP	/* PC23 periph B with pullup */
							 AT91_PIOC 22 AT91_PERIPH_B AT91_PINCTRL_NONE>;	/* PC22 periph B */
					};

					pinctrl_usart3_rts: usart3_rts-0 {
						atmel,pins =
							<AT91_PIOC 24 AT91_PERIPH_B AT91_PINCTRL_NONE>;	/* PC24 periph B */
					};

					pinctrl_usart3_cts: usart3_cts-0 {
						atmel,pins =
							<AT91_PIOC 25 AT91_PERIPH_B AT91_PINCTRL_NONE>;	/* PC25 periph B */
					};
				};

				uart0 {
					pinctrl_uart0: uart0-0 {
						atmel,pins =
							<AT91_PIOC 9 AT91_PERIPH_C AT91_PINCTRL_PULL_UP	/* PC9 periph C with pullup */
							 AT91_PIOC 8 AT91_PERIPH_C AT91_PINCTRL_NONE>;	/* PC8 periph C */
					};
				};

				uart1 {
					pinctrl_uart1: uart1-0 {
						atmel,pins =
							<AT91_PIOC 16 AT91_PERIPH_C AT91_PINCTRL_PULL_UP	/* PC17 periph C with pullup */
							 AT91_PIOC 17 AT91_PERIPH_C AT91_PINCTRL_NONE>;	/* PC16 periph C */
					};
				};

				nand {
					pinctrl_nand: nand-0 {
						atmel,pins =
							<AT91_PIOD 5 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP	/* PD5 gpio RDY pin pull_up*/
							 AT91_PIOD 4 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>;	/* PD4 gpio enable pin pull_up */
					};
				};

				mmc0 {
					pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 {
						atmel,pins =
							<AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PA17 periph A */
							 AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_PULL_UP	/* PA16 periph A with pullup */
							 AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;	/* PA15 periph A with pullup */
					};

					pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
						atmel,pins =
							<AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP	/* PA18 periph A with pullup */
							 AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_PULL_UP	/* PA19 periph A with pullup */
							 AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;	/* PA20 periph A with pullup */
					};

					pinctrl_mmc0_slot0_dat4_7: mmc0_slot0_dat4_7-0 {
						atmel,pins =
							<AT91_PIOA 11 AT91_PERIPH_B AT91_PINCTRL_PULL_UP	/* PA11 periph B with pullup */
							 AT91_PIOA 12 AT91_PERIPH_B AT91_PINCTRL_PULL_UP	/* PA12 periph B with pullup */
							 AT91_PIOA 13 AT91_PERIPH_B AT91_PINCTRL_PULL_UP	/* PA13 periph B with pullup */
							 AT91_PIOA 14 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>;	/* PA14 periph B with pullup */
					};
				};

				ssc0 {
					pinctrl_ssc0_tx: ssc0_tx-0 {
						atmel,pins =
							<AT91_PIOA 24 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PA24 periph B */
							 AT91_PIOA 25 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PA25 periph B */
							 AT91_PIOA 26 AT91_PERIPH_B AT91_PINCTRL_NONE>;	/* PA26 periph B */
					};

					pinctrl_ssc0_rx: ssc0_rx-0 {
						atmel,pins =
							<AT91_PIOA 27 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PA27 periph B */
							 AT91_PIOA 28 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PA28 periph B */
							 AT91_PIOA 29 AT91_PERIPH_B AT91_PINCTRL_NONE>;	/* PA29 periph B */
					};
				};

				spi0 {
					pinctrl_spi0: spi0-0 {
						atmel,pins =
							<AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PA11 periph A SPI0_MISO pin */
							 AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PA12 periph A SPI0_MOSI pin */
							 AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PA13 periph A SPI0_SPCK pin */
					};
				};

				spi1 {
					pinctrl_spi1: spi1-0 {
						atmel,pins =
							<AT91_PIOA 21 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PA21 periph B SPI1_MISO pin */
							 AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PA22 periph B SPI1_MOSI pin */
							 AT91_PIOA 23 AT91_PERIPH_B AT91_PINCTRL_NONE>;	/* PA23 periph B SPI1_SPCK pin */
					};
				};

				tcb0 {
					pinctrl_tcb0_tclk0: tcb0_tclk0-0 {
						atmel,pins = <AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_NONE>;
					};

					pinctrl_tcb0_tclk1: tcb0_tclk1-0 {
						atmel,pins = <AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_NONE>;
					};

					pinctrl_tcb0_tclk2: tcb0_tclk2-0 {
						atmel,pins = <AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_NONE>;
					};

					pinctrl_tcb0_tioa0: tcb0_tioa0-0 {
						atmel,pins = <AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE>;
					};

					pinctrl_tcb0_tioa1: tcb0_tioa1-0 {
						atmel,pins = <AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_NONE>;
					};

					pinctrl_tcb0_tioa2: tcb0_tioa2-0 {
						atmel,pins = <AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_NONE>;
					};

					pinctrl_tcb0_tiob0: tcb0_tiob0-0 {
						atmel,pins = <AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE>;
					};

					pinctrl_tcb0_tiob1: tcb0_tiob1-0 {
						atmel,pins = <AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_NONE>;
					};

					pinctrl_tcb0_tiob2: tcb0_tiob2-0 {
						atmel,pins = <AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_NONE>;
					};
				};

				tcb1 {
					pinctrl_tcb1_tclk0: tcb1_tclk0-0 {
						atmel,pins = <AT91_PIOC 4 AT91_PERIPH_C AT91_PINCTRL_NONE>;
					};

					pinctrl_tcb1_tclk1: tcb1_tclk1-0 {
						atmel,pins = <AT91_PIOC 7 AT91_PERIPH_C AT91_PINCTRL_NONE>;
					};

					pinctrl_tcb1_tclk2: tcb1_tclk2-0 {
						atmel,pins = <AT91_PIOC 14 AT91_PERIPH_C AT91_PINCTRL_NONE>;
					};

					pinctrl_tcb1_tioa0: tcb1_tioa0-0 {
						atmel,pins = <AT91_PIOC 2 AT91_PERIPH_C AT91_PINCTRL_NONE>;
					};

					pinctrl_tcb1_tioa1: tcb1_tioa1-0 {
						atmel,pins = <AT91_PIOC 5 AT91_PERIPH_C AT91_PINCTRL_NONE>;
					};

					pinctrl_tcb1_tioa2: tcb1_tioa2-0 {
						atmel,pins = <AT91_PIOC 12 AT91_PERIPH_C AT91_PINCTRL_NONE>;
					};

					pinctrl_tcb1_tiob0: tcb1_tiob0-0 {
						atmel,pins = <AT91_PIOC 3 AT91_PERIPH_C AT91_PINCTRL_NONE>;
					};

					pinctrl_tcb1_tiob1: tcb1_tiob1-0 {
						atmel,pins = <AT91_PIOC 6 AT91_PERIPH_C AT91_PINCTRL_NONE>;
					};

					pinctrl_tcb1_tiob2: tcb1_tiob2-0 {
						atmel,pins = <AT91_PIOC 13 AT91_PERIPH_C AT91_PINCTRL_NONE>;
					};
				};

				pioA: gpio@fffff400 {
					compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
					reg = <0xfffff400 0x200>;
					interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
					#gpio-cells = <2>;
					gpio-controller;
					interrupt-controller;
					#interrupt-cells = <2>;
				};

				pioB: gpio@fffff600 {
					compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
					reg = <0xfffff600 0x200>;
					interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
					#gpio-cells = <2>;
					gpio-controller;
					interrupt-controller;
					#interrupt-cells = <2>;
				};

				pioC: gpio@fffff800 {
					compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
					reg = <0xfffff800 0x200>;
					interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
					#gpio-cells = <2>;
					gpio-controller;
					interrupt-controller;
					#interrupt-cells = <2>;
				};

				pioD: gpio@fffffa00 {
					compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
					reg = <0xfffffa00 0x200>;
					interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
					#gpio-cells = <2>;
					gpio-controller;
					interrupt-controller;
					#interrupt-cells = <2>;
				};
			};

			dbgu: serial@fffff200 {
				compatible = "atmel,at91sam9260-usart";
				reg = <0xfffff200 0x200>;
				interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
				pinctrl-names = "default";
				pinctrl-0 = <&pinctrl_dbgu>;
				status = "disabled";
			};

			ssc0: ssc@f0010000 {
				compatible = "atmel,at91sam9g45-ssc";
				reg = <0xf0010000 0x4000>;
				interrupts = <28 IRQ_TYPE_LEVEL_HIGH 5>;
				pinctrl-names = "default";
				pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
				status = "disabled";
			};

			usart0: serial@f801c000 {
				compatible = "atmel,at91sam9260-usart";
				reg = <0xf801c000 0x4000>;
				interrupts = <5 IRQ_TYPE_LEVEL_HIGH 5>;
				pinctrl-names = "default";
				pinctrl-0 = <&pinctrl_usart0>;
				status = "disabled";
			};

			usart1: serial@f8020000 {
				compatible = "atmel,at91sam9260-usart";
				reg = <0xf8020000 0x4000>;
				interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>;
				pinctrl-names = "default";
				pinctrl-0 = <&pinctrl_usart1>;
				status = "disabled";
			};

			usart2: serial@f8024000 {
				compatible = "atmel,at91sam9260-usart";
				reg = <0xf8024000 0x4000>;
				interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>;
				pinctrl-names = "default";
				pinctrl-0 = <&pinctrl_usart2>;
				status = "disabled";
			};

			usart3: serial@f8028000 {
				compatible = "atmel,at91sam9260-usart";
				reg = <0xf8028000 0x4000>;
				interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>;
				pinctrl-names = "default";
				pinctrl-0 = <&pinctrl_usart3>;
				status = "disabled";
			};

			i2c0: i2c@f8010000 {
				compatible = "atmel,at91sam9x5-i2c";
				reg = <0xf8010000 0x100>;
				interrupts = <9 IRQ_TYPE_LEVEL_HIGH 6>;
				dmas = <&dma 1 13>,
				       <&dma 1 14>;
				dma-names = "tx", "rx";
				#address-cells = <1>;
				#size-cells = <0>;
				status = "disabled";
			};

			i2c1: i2c@f8014000 {
				compatible = "atmel,at91sam9x5-i2c";
				reg = <0xf8014000 0x100>;
				interrupts = <10 IRQ_TYPE_LEVEL_HIGH 6>;
				dmas = <&dma 1 15>,
				       <&dma 1 16>;
				dma-names = "tx", "rx";
				#address-cells = <1>;
				#size-cells = <0>;
				status = "disabled";
			};

			spi0: spi@f0000000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "atmel,at91rm9200-spi";
				reg = <0xf0000000 0x100>;
				interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>;
				pinctrl-names = "default";
				pinctrl-0 = <&pinctrl_spi0>;
				status = "disabled";
			};

			spi1: spi@f0004000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "atmel,at91rm9200-spi";
				reg = <0xf0004000 0x100>;
				interrupts = <14 IRQ_TYPE_LEVEL_HIGH 3>;
				pinctrl-names = "default";
				pinctrl-0 = <&pinctrl_spi1>;
				status = "disabled";
			};

			watchdog@fffffe40 {
				compatible = "atmel,at91sam9260-wdt";
				reg = <0xfffffe40 0x10>;
				status = "disabled";
			};
		};

		nand0: nand@40000000 {
			compatible = "atmel,at91rm9200-nand";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = < 0x40000000 0x10000000
				0xffffe000 0x00000600
				0xffffe600 0x00000200
				0x00108000 0x00018000
			       >;
			atmel,pmecc-lookup-table-offset = <0x0 0x8000>;
			atmel,nand-addr-offset = <21>;
			atmel,nand-cmd-offset = <22>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_nand>;
			gpios = <&pioD 5 GPIO_ACTIVE_HIGH
				 &pioD 4 GPIO_ACTIVE_HIGH
				 0
				>;
			status = "disabled";
		};

		usb0: ohci@00500000 {
			compatible = "atmel,at91rm9200-ohci", "usb-ohci";
			reg = <0x00500000 0x00100000>;
			interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
			status = "disabled";
		};
	};

	i2c@0 {
		compatible = "i2c-gpio";
		gpios = <&pioA 30 GPIO_ACTIVE_HIGH /* sda */
			 &pioA 31 GPIO_ACTIVE_HIGH /* scl */
			>;
		i2c-gpio,sda-open-drain;
		i2c-gpio,scl-open-drain;
		i2c-gpio,delay-us = <2>;	/* ~100 kHz */
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
	};
};
Commit	Line	Data
cce783c6 HX	1	/*
	2	* at91sam9n12.dtsi - Device Tree include file for AT91SAM9N12 SoC
	3	*
	4	* Copyright (C) 2012 Atmel,
	5	* 2012 Hong Xu <hong.xu@atmel.com>
	6	*
	7	* Licensed under GPLv2 or later.
	8	*/
	9
6db64d29	10	#include "skeleton.dtsi"
c9d0f317	11	#include <dt-bindings/pinctrl/at91.h>
5e8b3bc3	12	#include <dt-bindings/interrupt-controller/irq.h>
92f8629b	13	#include <dt-bindings/gpio/gpio.h>
cce783c6 HX	14
	15	/ {
	16	model = "Atmel AT91SAM9N12 SoC";
	17	compatible = "atmel,at91sam9n12";
	18	interrupt-parent = <&aic>;
	19
	20	aliases {
	21	serial0 = &dbgu;
	22	serial1 = &usart0;
	23	serial2 = &usart1;
	24	serial3 = &usart2;
	25	serial4 = &usart3;
	26	gpio0 = &pioA;
	27	gpio1 = &pioB;
	28	gpio2 = &pioC;
	29	gpio3 = &pioD;
	30	tcb0 = &tcb0;
	31	tcb1 = &tcb1;
05dcd361 LD	32	i2c0 = &i2c0;
05dcd361 LD	33	i2c1 = &i2c1;
544ae6b2	34	ssc0 = &ssc0;
cce783c6 HX	35	};
	36	cpus {
	37	cpu@0 {
	38	compatible = "arm,arm926ejs";
	39	};
	40	};
	41
	42	memory {
	43	reg = <0x20000000 0x10000000>;
	44	};
	45
	46	ahb {
	47	compatible = "simple-bus";
	48	#address-cells = <1>;
	49	#size-cells = <1>;
	50	ranges;
	51
	52	apb {
	53	compatible = "simple-bus";
	54	#address-cells = <1>;
	55	#size-cells = <1>;
	56	ranges;
	57
	58	aic: interrupt-controller@fffff000 {
f8a073ee	59	#interrupt-cells = <3>;
cce783c6 HX	60	compatible = "atmel,at91rm9200-aic";
	61	interrupt-controller;
	62	reg = <0xfffff000 0x200>;
	63	};
	64
	65	ramc0: ramc@ffffe800 {
	66	compatible = "atmel,at91sam9g45-ddramc";
	67	reg = <0xffffe800 0x200>;
	68	};
	69
	70	pmc: pmc@fffffc00 {
	71	compatible = "atmel,at91rm9200-pmc";
	72	reg = <0xfffffc00 0x100>;
	73	};
	74
	75	rstc@fffffe00 {
	76	compatible = "atmel,at91sam9g45-rstc";
	77	reg = <0xfffffe00 0x10>;
	78	};
	79
	80	pit: timer@fffffe30 {
	81	compatible = "atmel,at91sam9260-pit";
	82	reg = <0xfffffe30 0xf>;
5e8b3bc3	83	interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
cce783c6 HX	84	};
	85
	86	shdwc@fffffe10 {
	87	compatible = "atmel,at91sam9x5-shdwc";
	88	reg = <0xfffffe10 0x10>;
	89	};
	90
9873137a LD	91	mmc0: mmc@f0008000 {
	92	compatible = "atmel,hsmci";
	93	reg = <0xf0008000 0x600>;
5e8b3bc3	94	interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>;
05c1bc97 LD	95	dmas = <&dma 1 0>;
05c1bc97 LD	96	dma-names = "rxtx";
9873137a LD	97	#address-cells = <1>;
	98	#size-cells = <0>;
	99	status = "disabled";
	100	};
	101
cce783c6 HX	102	tcb0: timer@f8008000 {
	103	compatible = "atmel,at91sam9x5-tcb";
	104	reg = <0xf8008000 0x100>;
5e8b3bc3	105	interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;
cce783c6 HX	106	};
	107
	108	tcb1: timer@f800c000 {
	109	compatible = "atmel,at91sam9x5-tcb";
	110	reg = <0xf800c000 0x100>;
5e8b3bc3	111	interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;
cce783c6 HX	112	};
	113
	114	dma: dma-controller@ffffec00 {
	115	compatible = "atmel,at91sam9g45-dma";
	116	reg = <0xffffec00 0x200>;
5e8b3bc3	117	interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>;
980ce7d9	118	#dma-cells = <2>;
cce783c6 HX	119	};
cce783c6 HX	120
e4541ff2 JCPV	121	pinctrl@fffff400 {
	122	#address-cells = <1>;
	123	#size-cells = <1>;
5314ec8e	124	compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus";
e4541ff2 JCPV	125	ranges = <0xfffff400 0xfffff400 0x800>;
e4541ff2 JCPV	126
5314ec8e JCPV	127	atmel,mux-mask = <
	128	/* A B C */
	129	0xffffffff 0xffe07983 0x00000000 /* pioA */
	130	0x00040000 0x00047e0f 0x00000000 /* pioB */
	131	0xfdffffff 0x07c00000 0xb83fffff /* pioC */
	132	0x003fffff 0x003f8000 0x00000000 /* pioD */
	133	>;
	134
	135	/* shared pinctrl settings */
ec6754a7 JCPV	136	dbgu {
	137	pinctrl_dbgu: dbgu-0 {
	138	atmel,pins =
c9d0f317 JCPV	139	<AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA9 periph A */
c9d0f317 JCPV	140	AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA10 periph with pullup */
ec6754a7 JCPV	141	};
	142	};
	143
9e3129e9 JCPV	144	usart0 {
9e3129e9 JCPV	145	pinctrl_usart0: usart0-0 {
ec6754a7	146	atmel,pins =
c9d0f317 JCPV	147	<AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA1 periph A with pullup */
c9d0f317 JCPV	148	AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA0 periph A */
ec6754a7 JCPV	149	};
ec6754a7 JCPV	150
c58c0c5a	151	pinctrl_usart0_rts: usart0_rts-0 {
ec6754a7	152	atmel,pins =
c9d0f317	153	<AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA2 periph A */
c58c0c5a JCPV	154	};
	155
	156	pinctrl_usart0_cts: usart0_cts-0 {
	157	atmel,pins =
c9d0f317	158	<AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA3 periph A */
ec6754a7 JCPV	159	};
	160	};
	161
9e3129e9 JCPV	162	usart1 {
9e3129e9 JCPV	163	pinctrl_usart1: usart1-0 {
ec6754a7	164	atmel,pins =
c9d0f317 JCPV	165	<AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA6 periph A with pullup */
c9d0f317 JCPV	166	AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA5 periph A */
ec6754a7 JCPV	167	};
	168	};
	169
9e3129e9 JCPV	170	usart2 {
9e3129e9 JCPV	171	pinctrl_usart2: usart2-0 {
ec6754a7	172	atmel,pins =
c9d0f317 JCPV	173	<AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA8 periph A with pullup */
c9d0f317 JCPV	174	AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA7 periph A */
ec6754a7 JCPV	175	};
ec6754a7 JCPV	176
c58c0c5a	177	pinctrl_usart2_rts: usart2_rts-0 {
ec6754a7	178	atmel,pins =
c9d0f317	179	<AT91_PIOB 0 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB0 periph B */
c58c0c5a JCPV	180	};
	181
	182	pinctrl_usart2_cts: usart2_cts-0 {
	183	atmel,pins =
c9d0f317	184	<AT91_PIOB 1 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB1 periph B */
ec6754a7 JCPV	185	};
	186	};
	187
9e3129e9 JCPV	188	usart3 {
9e3129e9 JCPV	189	pinctrl_usart3: usart3-0 {
ec6754a7	190	atmel,pins =
c9d0f317 JCPV	191	<AT91_PIOC 23 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PC23 periph B with pullup */
c9d0f317 JCPV	192	AT91_PIOC 22 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC22 periph B */
ec6754a7 JCPV	193	};
ec6754a7 JCPV	194
c58c0c5a JCPV	195	pinctrl_usart3_rts: usart3_rts-0 {
c58c0c5a JCPV	196	atmel,pins =
c9d0f317	197	<AT91_PIOC 24 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC24 periph B */
c58c0c5a JCPV	198	};
	199
	200	pinctrl_usart3_cts: usart3_cts-0 {
ec6754a7	201	atmel,pins =
c9d0f317	202	<AT91_PIOC 25 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC25 periph B */
ec6754a7 JCPV	203	};
	204	};
	205
9e3129e9 JCPV	206	uart0 {
9e3129e9 JCPV	207	pinctrl_uart0: uart0-0 {
ec6754a7	208	atmel,pins =
c9d0f317 JCPV	209	<AT91_PIOC 9 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* PC9 periph C with pullup */
c9d0f317 JCPV	210	AT91_PIOC 8 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC8 periph C */
ec6754a7 JCPV	211	};
	212	};
	213
9e3129e9 JCPV	214	uart1 {
9e3129e9 JCPV	215	pinctrl_uart1: uart1-0 {
ec6754a7	216	atmel,pins =
c9d0f317 JCPV	217	<AT91_PIOC 16 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* PC17 periph C with pullup */
c9d0f317 JCPV	218	AT91_PIOC 17 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC16 periph C */
ec6754a7 JCPV	219	};
ec6754a7 JCPV	220	};
5314ec8e	221
7a38d450 JCPV	222	nand {
	223	pinctrl_nand: nand-0 {
	224	atmel,pins =
c9d0f317 JCPV	225	<AT91_PIOD 5 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP /* PD5 gpio RDY pin pull_up*/
c9d0f317 JCPV	226	AT91_PIOD 4 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>; /* PD4 gpio enable pin pull_up */
7a38d450 JCPV	227	};
	228	};
	229
d4fe9ac7 JCPV	230	mmc0 {
	231	pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 {
	232	atmel,pins =
c9d0f317 JCPV	233	<AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA17 periph A */
	234	AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA16 periph A with pullup */
	235	AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA15 periph A with pullup */
d4fe9ac7 JCPV	236	};
	237
	238	pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
	239	atmel,pins =
c9d0f317 JCPV	240	<AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA18 periph A with pullup */
	241	AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA19 periph A with pullup */
	242	AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA20 periph A with pullup */
d4fe9ac7 JCPV	243	};
	244
	245	pinctrl_mmc0_slot0_dat4_7: mmc0_slot0_dat4_7-0 {
	246	atmel,pins =
c9d0f317 JCPV	247	<AT91_PIOA 11 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA11 periph B with pullup */
	248	AT91_PIOA 12 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA12 periph B with pullup */
	249	AT91_PIOA 13 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA13 periph B with pullup */
	250	AT91_PIOA 14 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PA14 periph B with pullup */
d4fe9ac7 JCPV	251	};
	252	};
	253
544ae6b2 BS	254	ssc0 {
	255	pinctrl_ssc0_tx: ssc0_tx-0 {
	256	atmel,pins =
c9d0f317 JCPV	257	<AT91_PIOA 24 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA24 periph B */
	258	AT91_PIOA 25 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA25 periph B */
	259	AT91_PIOA 26 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA26 periph B */
544ae6b2 BS	260	};
	261
	262	pinctrl_ssc0_rx: ssc0_rx-0 {
	263	atmel,pins =
c9d0f317 JCPV	264	<AT91_PIOA 27 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA27 periph B */
	265	AT91_PIOA 28 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA28 periph B */
	266	AT91_PIOA 29 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA29 periph B */
544ae6b2 BS	267	};
	268	};
	269
a68b728f WY	270	spi0 {
	271	pinctrl_spi0: spi0-0 {
	272	atmel,pins =
c9d0f317 JCPV	273	<AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA11 periph A SPI0_MISO pin */
	274	AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA12 periph A SPI0_MOSI pin */
	275	AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA13 periph A SPI0_SPCK pin */
a68b728f WY	276	};
	277	};
	278
	279	spi1 {
	280	pinctrl_spi1: spi1-0 {
	281	atmel,pins =
c9d0f317 JCPV	282	<AT91_PIOA 21 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA21 periph B SPI1_MISO pin */
	283	AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA22 periph B SPI1_MOSI pin */
	284	AT91_PIOA 23 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA23 periph B SPI1_SPCK pin */
a68b728f WY	285	};
	286	};
	287
028633c2 BB	288	tcb0 {
	289	pinctrl_tcb0_tclk0: tcb0_tclk0-0 {
	290	atmel,pins = <AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_NONE>;
	291	};
	292
	293	pinctrl_tcb0_tclk1: tcb0_tclk1-0 {
	294	atmel,pins = <AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_NONE>;
	295	};
	296
	297	pinctrl_tcb0_tclk2: tcb0_tclk2-0 {
	298	atmel,pins = <AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_NONE>;
	299	};
	300
	301	pinctrl_tcb0_tioa0: tcb0_tioa0-0 {
	302	atmel,pins = <AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE>;
	303	};
	304
	305	pinctrl_tcb0_tioa1: tcb0_tioa1-0 {
	306	atmel,pins = <AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_NONE>;
	307	};
	308
	309	pinctrl_tcb0_tioa2: tcb0_tioa2-0 {
	310	atmel,pins = <AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_NONE>;
	311	};
	312
	313	pinctrl_tcb0_tiob0: tcb0_tiob0-0 {
	314	atmel,pins = <AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE>;
	315	};
	316
	317	pinctrl_tcb0_tiob1: tcb0_tiob1-0 {
	318	atmel,pins = <AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_NONE>;
	319	};
	320
	321	pinctrl_tcb0_tiob2: tcb0_tiob2-0 {
	322	atmel,pins = <AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_NONE>;
	323	};
	324	};
	325
	326	tcb1 {
	327	pinctrl_tcb1_tclk0: tcb1_tclk0-0 {
	328	atmel,pins = <AT91_PIOC 4 AT91_PERIPH_C AT91_PINCTRL_NONE>;
	329	};
	330
	331	pinctrl_tcb1_tclk1: tcb1_tclk1-0 {
	332	atmel,pins = <AT91_PIOC 7 AT91_PERIPH_C AT91_PINCTRL_NONE>;
	333	};
	334
	335	pinctrl_tcb1_tclk2: tcb1_tclk2-0 {
	336	atmel,pins = <AT91_PIOC 14 AT91_PERIPH_C AT91_PINCTRL_NONE>;
	337	};
	338
	339	pinctrl_tcb1_tioa0: tcb1_tioa0-0 {
	340	atmel,pins = <AT91_PIOC 2 AT91_PERIPH_C AT91_PINCTRL_NONE>;
	341	};
	342
	343	pinctrl_tcb1_tioa1: tcb1_tioa1-0 {
	344	atmel,pins = <AT91_PIOC 5 AT91_PERIPH_C AT91_PINCTRL_NONE>;
	345	};
	346
	347	pinctrl_tcb1_tioa2: tcb1_tioa2-0 {
	348	atmel,pins = <AT91_PIOC 12 AT91_PERIPH_C AT91_PINCTRL_NONE>;
	349	};
	350
	351	pinctrl_tcb1_tiob0: tcb1_tiob0-0 {
352	atmel,pins = <AT91_PIOC 3 AT91_PERIPH_C AT91_PINCTRL_NONE>;
353	};
354
355	pinctrl_tcb1_tiob1: tcb1_tiob1-0 {
356	atmel,pins = <AT91_PIOC 6 AT91_PERIPH_C AT91_PINCTRL_NONE>;
357	};
358
359	pinctrl_tcb1_tiob2: tcb1_tiob2-0 {
360	atmel,pins = <AT91_PIOC 13 AT91_PERIPH_C AT91_PINCTRL_NONE>;
361	};
362	};
363
e4541ff2 JCPV	364	pioA: gpio@fffff400 {
	365	compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
	366	reg = <0xfffff400 0x200>;
5e8b3bc3	367	interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
e4541ff2 JCPV	368	#gpio-cells = <2>;
	369	gpio-controller;
	370	interrupt-controller;
	371	#interrupt-cells = <2>;
	372	};
	373
	374	pioB: gpio@fffff600 {
	375	compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
	376	reg = <0xfffff600 0x200>;
5e8b3bc3	377	interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
e4541ff2 JCPV	378	#gpio-cells = <2>;
	379	gpio-controller;
	380	interrupt-controller;
	381	#interrupt-cells = <2>;
	382	};
	383
	384	pioC: gpio@fffff800 {
	385	compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
	386	reg = <0xfffff800 0x200>;
5e8b3bc3	387	interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
e4541ff2 JCPV	388	#gpio-cells = <2>;
	389	gpio-controller;
	390	interrupt-controller;
	391	#interrupt-cells = <2>;
	392	};
	393
	394	pioD: gpio@fffffa00 {
	395	compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
	396	reg = <0xfffffa00 0x200>;
5e8b3bc3	397	interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
e4541ff2 JCPV	398	#gpio-cells = <2>;
	399	gpio-controller;
	400	interrupt-controller;
	401	#interrupt-cells = <2>;
	402	};
cce783c6 HX	403	};
	404
	405	dbgu: serial@fffff200 {
	406	compatible = "atmel,at91sam9260-usart";
	407	reg = <0xfffff200 0x200>;
5e8b3bc3	408	interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
ec6754a7 JCPV	409	pinctrl-names = "default";
ec6754a7 JCPV	410	pinctrl-0 = <&pinctrl_dbgu>;
cce783c6 HX	411	status = "disabled";
	412	};
	413
544ae6b2 BS	414	ssc0: ssc@f0010000 {
	415	compatible = "atmel,at91sam9g45-ssc";
	416	reg = <0xf0010000 0x4000>;
5e8b3bc3	417	interrupts = <28 IRQ_TYPE_LEVEL_HIGH 5>;
544ae6b2 BS	418	pinctrl-names = "default";
	419	pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
	420	status = "disabled";
	421	};
	422
cce783c6 HX	423	usart0: serial@f801c000 {
	424	compatible = "atmel,at91sam9260-usart";
	425	reg = <0xf801c000 0x4000>;
5e8b3bc3	426	interrupts = <5 IRQ_TYPE_LEVEL_HIGH 5>;
ec6754a7	427	pinctrl-names = "default";
9e3129e9	428	pinctrl-0 = <&pinctrl_usart0>;
cce783c6 HX	429	status = "disabled";
	430	};
	431
	432	usart1: serial@f8020000 {
	433	compatible = "atmel,at91sam9260-usart";
	434	reg = <0xf8020000 0x4000>;
5e8b3bc3	435	interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>;
ec6754a7	436	pinctrl-names = "default";
9e3129e9	437	pinctrl-0 = <&pinctrl_usart1>;
cce783c6 HX	438	status = "disabled";
	439	};
	440
	441	usart2: serial@f8024000 {
	442	compatible = "atmel,at91sam9260-usart";
	443	reg = <0xf8024000 0x4000>;
5e8b3bc3	444	interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>;
ec6754a7	445	pinctrl-names = "default";
9e3129e9	446	pinctrl-0 = <&pinctrl_usart2>;
cce783c6 HX	447	status = "disabled";
	448	};
	449
	450	usart3: serial@f8028000 {
	451	compatible = "atmel,at91sam9260-usart";
	452	reg = <0xf8028000 0x4000>;
5e8b3bc3	453	interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>;
ec6754a7	454	pinctrl-names = "default";
9e3129e9	455	pinctrl-0 = <&pinctrl_usart3>;
cce783c6 HX	456	status = "disabled";
cce783c6 HX	457	};
05dcd361 LD	458
	459	i2c0: i2c@f8010000 {
	460	compatible = "atmel,at91sam9x5-i2c";
	461	reg = <0xf8010000 0x100>;
5e8b3bc3	462	interrupts = <9 IRQ_TYPE_LEVEL_HIGH 6>;
d9a63a45 LD	463	dmas = <&dma 1 13>,
	464	<&dma 1 14>;
	465	dma-names = "tx", "rx";
05dcd361 LD	466	#address-cells = <1>;
	467	#size-cells = <0>;
	468	status = "disabled";
	469	};
	470
	471	i2c1: i2c@f8014000 {
	472	compatible = "atmel,at91sam9x5-i2c";
	473	reg = <0xf8014000 0x100>;
5e8b3bc3	474	interrupts = <10 IRQ_TYPE_LEVEL_HIGH 6>;
d9a63a45 LD	475	dmas = <&dma 1 15>,
	476	<&dma 1 16>;
	477	dma-names = "tx", "rx";
05dcd361 LD	478	#address-cells = <1>;
	479	#size-cells = <0>;
	480	status = "disabled";
	481	};
d50f88a0 RG	482
	483	spi0: spi@f0000000 {
	484	#address-cells = <1>;
	485	#size-cells = <0>;
	486	compatible = "atmel,at91rm9200-spi";
	487	reg = <0xf0000000 0x100>;
5e8b3bc3	488	interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>;
a68b728f WY	489	pinctrl-names = "default";
a68b728f WY	490	pinctrl-0 = <&pinctrl_spi0>;
d50f88a0 RG	491	status = "disabled";
	492	};
	493
	494	spi1: spi@f0004000 {
	495	#address-cells = <1>;
	496	#size-cells = <0>;
	497	compatible = "atmel,at91rm9200-spi";
	498	reg = <0xf0004000 0x100>;
5e8b3bc3	499	interrupts = <14 IRQ_TYPE_LEVEL_HIGH 3>;
a68b728f WY	500	pinctrl-names = "default";
a68b728f WY	501	pinctrl-0 = <&pinctrl_spi1>;
d50f88a0 RG	502	status = "disabled";
d50f88a0 RG	503	};
136d3556 WY	504
	505	watchdog@fffffe40 {
	506	compatible = "atmel,at91sam9260-wdt";
	507	reg = <0xfffffe40 0x10>;
	508	status = "disabled";
	509	};
cce783c6 HX	510	};
	511
	512	nand0: nand@40000000 {
	513	compatible = "atmel,at91rm9200-nand";
	514	#address-cells = <1>;
	515	#size-cells = <1>;
	516	reg = < 0x40000000 0x10000000
	517	0xffffe000 0x00000600
	518	0xffffe600 0x00000200
c18c6b29	519	0x00108000 0x00018000
cce783c6	520	>;
c18c6b29	521	atmel,pmecc-lookup-table-offset = <0x0 0x8000>;
cce783c6 HX	522	atmel,nand-addr-offset = <21>;
cce783c6 HX	523	atmel,nand-cmd-offset = <22>;
7a38d450 JCPV	524	pinctrl-names = "default";
7a38d450 JCPV	525	pinctrl-0 = <&pinctrl_nand>;
92f8629b JCPV	526	gpios = <&pioD 5 GPIO_ACTIVE_HIGH
92f8629b JCPV	527	&pioD 4 GPIO_ACTIVE_HIGH
cce783c6 HX	528	0
	529	>;
	530	status = "disabled";
	531	};
	532
	533	usb0: ohci@00500000 {
	534	compatible = "atmel,at91rm9200-ohci", "usb-ohci";
	535	reg = <0x00500000 0x00100000>;
5e8b3bc3	536	interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
cce783c6 HX	537	status = "disabled";
	538	};
	539	};
	540
	541	i2c@0 {
	542	compatible = "i2c-gpio";
92f8629b JCPV	543	gpios = <&pioA 30 GPIO_ACTIVE_HIGH /* sda */
92f8629b JCPV	544	&pioA 31 GPIO_ACTIVE_HIGH /* scl */
cce783c6 HX	545	>;
	546	i2c-gpio,sda-open-drain;
	547	i2c-gpio,scl-open-drain;
	548	i2c-gpio,delay-us = <2>; /* ~100 kHz */
	549	#address-cells = <1>;
	550	#size-cells = <0>;
	551	status = "disabled";
	552	};
	553	};