[deliverable/linux.git] / arch / arm / boot / dts / at91sam9x5.dtsi

/*
 * at91sam9x5.dtsi - Device Tree Include file for AT91SAM9x5 family SoC
 *                   applies to AT91SAM9G15, AT91SAM9G25, AT91SAM9G35,
 *                   AT91SAM9X25, AT91SAM9X35 SoC
 *
 *  Copyright (C) 2012 Atmel,
 *                2012 Nicolas Ferre <nicolas.ferre@atmel.com>
 *
 * Licensed under GPLv2 or later.
 */

/include/ "skeleton.dtsi"

/ {
	model = "Atmel AT91SAM9x5 family SoC";
	compatible = "atmel,at91sam9x5";
	interrupt-parent = <&aic>;

	aliases {
		serial0 = &dbgu;
		serial1 = &usart0;
		serial2 = &usart1;
		serial3 = &usart2;
		gpio0 = &pioA;
		gpio1 = &pioB;
		gpio2 = &pioC;
		gpio3 = &pioD;
		tcb0 = &tcb0;
		tcb1 = &tcb1;
		i2c0 = &i2c0;
		i2c1 = &i2c1;
		i2c2 = &i2c2;
	};
	cpus {
		cpu@0 {
			compatible = "arm,arm926ejs";
		};
	};

	memory {
		reg = <0x20000000 0x10000000>;
	};

	ahb {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		apb {
			compatible = "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

			aic: interrupt-controller@fffff000 {
				#interrupt-cells = <3>;
				compatible = "atmel,at91rm9200-aic";
				interrupt-controller;
				reg = <0xfffff000 0x200>;
				atmel,external-irqs = <31>;
			};

			ramc0: ramc@ffffe800 {
				compatible = "atmel,at91sam9g45-ddramc";
				reg = <0xffffe800 0x200>;
			};

			pmc: pmc@fffffc00 {
				compatible = "atmel,at91rm9200-pmc";
				reg = <0xfffffc00 0x100>;
			};

			rstc@fffffe00 {
				compatible = "atmel,at91sam9g45-rstc";
				reg = <0xfffffe00 0x10>;
			};

			shdwc@fffffe10 {
				compatible = "atmel,at91sam9x5-shdwc";
				reg = <0xfffffe10 0x10>;
			};

			pit: timer@fffffe30 {
				compatible = "atmel,at91sam9260-pit";
				reg = <0xfffffe30 0xf>;
				interrupts = <1 4 7>;
			};

			tcb0: timer@f8008000 {
				compatible = "atmel,at91sam9x5-tcb";
				reg = <0xf8008000 0x100>;
				interrupts = <17 4 0>;
			};

			tcb1: timer@f800c000 {
				compatible = "atmel,at91sam9x5-tcb";
				reg = <0xf800c000 0x100>;
				interrupts = <17 4 0>;
			};

			dma0: dma-controller@ffffec00 {
				compatible = "atmel,at91sam9g45-dma";
				reg = <0xffffec00 0x200>;
				interrupts = <20 4 0>;
			};

			dma1: dma-controller@ffffee00 {
				compatible = "atmel,at91sam9g45-dma";
				reg = <0xffffee00 0x200>;
				interrupts = <21 4 0>;
			};

			pinctrl@fffff200 {
				#address-cells = <1>;
				#size-cells = <1>;
				compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus";
				ranges = <0xfffff400 0xfffff400 0x800>;

				atmel,mux-mask = <
				      /*    A         B          C     */
				       0xffffffff 0xffe0399f 0xc000001c  /* pioA */
				       0xffffffff 0xffc003ff 0xffc003ff  /* pioB */
				       0xffffffff 0xffc003ff 0xffc003ff  /* pioC */
				       0xffffffff 0xffc003ff 0xffc003ff  /* pioD */
				      >;

				/* shared pinctrl settings */

				pioA: gpio@fffff400 {
					compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
					reg = <0xfffff400 0x200>;
					interrupts = <2 4 1>;
					#gpio-cells = <2>;
					gpio-controller;
					interrupt-controller;
					#interrupt-cells = <2>;
				};

				pioB: gpio@fffff600 {
					compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
					reg = <0xfffff600 0x200>;
					interrupts = <2 4 1>;
					#gpio-cells = <2>;
					gpio-controller;
					#gpio-lines = <19>;
					interrupt-controller;
					#interrupt-cells = <2>;
				};

				pioC: gpio@fffff800 {
					compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
					reg = <0xfffff800 0x200>;
					interrupts = <3 4 1>;
					#gpio-cells = <2>;
					gpio-controller;
					interrupt-controller;
					#interrupt-cells = <2>;
				};

				pioD: gpio@fffffa00 {
					compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
					reg = <0xfffffa00 0x200>;
					interrupts = <3 4 1>;
					#gpio-cells = <2>;
					gpio-controller;
					#gpio-lines = <22>;
					interrupt-controller;
					#interrupt-cells = <2>;
				};
			};

			dbgu: serial@fffff200 {
				compatible = "atmel,at91sam9260-usart";
				reg = <0xfffff200 0x200>;
				interrupts = <1 4 7>;
				status = "disabled";
			};

			usart0: serial@f801c000 {
				compatible = "atmel,at91sam9260-usart";
				reg = <0xf801c000 0x200>;
				interrupts = <5 4 5>;
				atmel,use-dma-rx;
				atmel,use-dma-tx;
				status = "disabled";
			};

			usart1: serial@f8020000 {
				compatible = "atmel,at91sam9260-usart";
				reg = <0xf8020000 0x200>;
				interrupts = <6 4 5>;
				atmel,use-dma-rx;
				atmel,use-dma-tx;
				status = "disabled";
			};

			usart2: serial@f8024000 {
				compatible = "atmel,at91sam9260-usart";
				reg = <0xf8024000 0x200>;
				interrupts = <7 4 5>;
				atmel,use-dma-rx;
				atmel,use-dma-tx;
				status = "disabled";
			};

			macb0: ethernet@f802c000 {
				compatible = "cdns,at32ap7000-macb", "cdns,macb";
				reg = <0xf802c000 0x100>;
				interrupts = <24 4 3>;
				status = "disabled";
			};

			macb1: ethernet@f8030000 {
				compatible = "cdns,at32ap7000-macb", "cdns,macb";
				reg = <0xf8030000 0x100>;
				interrupts = <27 4 3>;
				status = "disabled";
			};

			i2c0: i2c@f8010000 {
				compatible = "atmel,at91sam9x5-i2c";
				reg = <0xf8010000 0x100>;
				interrupts = <9 4 6>;
				#address-cells = <1>;
				#size-cells = <0>;
				status = "disabled";
			};

			i2c1: i2c@f8014000 {
				compatible = "atmel,at91sam9x5-i2c";
				reg = <0xf8014000 0x100>;
				interrupts = <10 4 6>;
				#address-cells = <1>;
				#size-cells = <0>;
				status = "disabled";
			};

			i2c2: i2c@f8018000 {
				compatible = "atmel,at91sam9x5-i2c";
				reg = <0xf8018000 0x100>;
				interrupts = <11 4 6>;
				#address-cells = <1>;
				#size-cells = <0>;
				status = "disabled";
			};

			adc0: adc@f804c000 {
				compatible = "atmel,at91sam9260-adc";
				reg = <0xf804c000 0x100>;
				interrupts = <19 4 0>;
				atmel,adc-use-external;
				atmel,adc-channels-used = <0xffff>;
				atmel,adc-vref = <3300>;
				atmel,adc-num-channels = <12>;
				atmel,adc-startup-time = <40>;
				atmel,adc-channel-base = <0x50>;
				atmel,adc-drdy-mask = <0x1000000>;
				atmel,adc-status-register = <0x30>;
				atmel,adc-trigger-register = <0xc0>;

				trigger@0 {
					trigger-name = "external-rising";
					trigger-value = <0x1>;
					trigger-external;
				};

				trigger@1 {
					trigger-name = "external-falling";
					trigger-value = <0x2>;
					trigger-external;
				};

				trigger@2 {
					trigger-name = "external-any";
					trigger-value = <0x3>;
					trigger-external;
				};

				trigger@3 {
					trigger-name = "continuous";
					trigger-value = <0x6>;
				};
			};
		};

		nand0: nand@40000000 {
			compatible = "atmel,at91rm9200-nand";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0x40000000 0x10000000
			      >;
			atmel,nand-addr-offset = <21>;
			atmel,nand-cmd-offset = <22>;
			gpios = <&pioD 5 0
				 &pioD 4 0
				 0
				>;
			status = "disabled";
		};

		usb0: ohci@00600000 {
			compatible = "atmel,at91rm9200-ohci", "usb-ohci";
			reg = <0x00600000 0x100000>;
			interrupts = <22 4 2>;
			status = "disabled";
		};

		usb1: ehci@00700000 {
			compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
			reg = <0x00700000 0x100000>;
			interrupts = <22 4 2>;
			status = "disabled";
		};
	};

	i2c@0 {
		compatible = "i2c-gpio";
		gpios = <&pioA 30 0 /* sda */
			 &pioA 31 0 /* scl */
			>;
		i2c-gpio,sda-open-drain;
		i2c-gpio,scl-open-drain;
		i2c-gpio,delay-us = <2>;	/* ~100 kHz */
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
	};

	i2c@1 {
		compatible = "i2c-gpio";
		gpios = <&pioC 0 0 /* sda */
			 &pioC 1 0 /* scl */
			>;
		i2c-gpio,sda-open-drain;
		i2c-gpio,scl-open-drain;
		i2c-gpio,delay-us = <2>;	/* ~100 kHz */
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
	};

	i2c@2 {
		compatible = "i2c-gpio";
		gpios = <&pioB 4 0 /* sda */
			 &pioB 5 0 /* scl */
			>;
		i2c-gpio,sda-open-drain;
		i2c-gpio,scl-open-drain;
		i2c-gpio,delay-us = <2>;	/* ~100 kHz */
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
	};
};
Commit	Line	Data
467f1cf5 NF	1	/*
	2	* at91sam9x5.dtsi - Device Tree Include file for AT91SAM9x5 family SoC
	3	* applies to AT91SAM9G15, AT91SAM9G25, AT91SAM9G35,
	4	* AT91SAM9X25, AT91SAM9X35 SoC
	5	*
	6	* Copyright (C) 2012 Atmel,
	7	* 2012 Nicolas Ferre <nicolas.ferre@atmel.com>
	8	*
	9	* Licensed under GPLv2 or later.
	10	*/
	11
	12	/include/ "skeleton.dtsi"
	13
	14	/ {
	15	model = "Atmel AT91SAM9x5 family SoC";
	16	compatible = "atmel,at91sam9x5";
	17	interrupt-parent = <&aic>;
	18
	19	aliases {
	20	serial0 = &dbgu;
	21	serial1 = &usart0;
	22	serial2 = &usart1;
	23	serial3 = &usart2;
	24	gpio0 = &pioA;
	25	gpio1 = &pioB;
	26	gpio2 = &pioC;
	27	gpio3 = &pioD;
	28	tcb0 = &tcb0;
	29	tcb1 = &tcb1;
05dcd361 LD	30	i2c0 = &i2c0;
	31	i2c1 = &i2c1;
	32	i2c2 = &i2c2;
467f1cf5 NF	33	};
	34	cpus {
	35	cpu@0 {
	36	compatible = "arm,arm926ejs";
	37	};
	38	};
	39
dcce6ce8	40	memory {
467f1cf5 NF	41	reg = <0x20000000 0x10000000>;
	42	};
	43
	44	ahb {
	45	compatible = "simple-bus";
	46	#address-cells = <1>;
	47	#size-cells = <1>;
	48	ranges;
	49
	50	apb {
	51	compatible = "simple-bus";
	52	#address-cells = <1>;
	53	#size-cells = <1>;
	54	ranges;
	55
	56	aic: interrupt-controller@fffff000 {
f8a073ee	57	#interrupt-cells = <3>;
467f1cf5 NF	58	compatible = "atmel,at91rm9200-aic";
467f1cf5 NF	59	interrupt-controller;
467f1cf5	60	reg = <0xfffff000 0x200>;
c6573943	61	atmel,external-irqs = <31>;
467f1cf5 NF	62	};
467f1cf5 NF	63
a7776ec6 JCPV	64	ramc0: ramc@ffffe800 {
	65	compatible = "atmel,at91sam9g45-ddramc";
	66	reg = <0xffffe800 0x200>;
	67	};
	68
eb5e76ff JCPV	69	pmc: pmc@fffffc00 {
	70	compatible = "atmel,at91rm9200-pmc";
	71	reg = <0xfffffc00 0x100>;
	72	};
	73
c8082d34 JCPV	74	rstc@fffffe00 {
	75	compatible = "atmel,at91sam9g45-rstc";
	76	reg = <0xfffffe00 0x10>;
	77	};
	78
82015c4e JCPV	79	shdwc@fffffe10 {
	80	compatible = "atmel,at91sam9x5-shdwc";
	81	reg = <0xfffffe10 0x10>;
	82	};
	83
467f1cf5 NF	84	pit: timer@fffffe30 {
	85	compatible = "atmel,at91sam9260-pit";
	86	reg = <0xfffffe30 0xf>;
f8a073ee	87	interrupts = <1 4 7>;
467f1cf5 NF	88	};
	89
	90	tcb0: timer@f8008000 {
	91	compatible = "atmel,at91sam9x5-tcb";
	92	reg = <0xf8008000 0x100>;
f8a073ee	93	interrupts = <17 4 0>;
467f1cf5 NF	94	};
	95
	96	tcb1: timer@f800c000 {
	97	compatible = "atmel,at91sam9x5-tcb";
	98	reg = <0xf800c000 0x100>;
f8a073ee	99	interrupts = <17 4 0>;
467f1cf5 NF	100	};
	101
	102	dma0: dma-controller@ffffec00 {
	103	compatible = "atmel,at91sam9g45-dma";
	104	reg = <0xffffec00 0x200>;
f8a073ee	105	interrupts = <20 4 0>;
467f1cf5 NF	106	};
	107
	108	dma1: dma-controller@ffffee00 {
	109	compatible = "atmel,at91sam9g45-dma";
	110	reg = <0xffffee00 0x200>;
f8a073ee	111	interrupts = <21 4 0>;
467f1cf5 NF	112	};
467f1cf5 NF	113
e4541ff2 JCPV	114	pinctrl@fffff200 {
	115	#address-cells = <1>;
	116	#size-cells = <1>;
5314ec8e	117	compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus";
e4541ff2 JCPV	118	ranges = <0xfffff400 0xfffff400 0x800>;
e4541ff2 JCPV	119
5314ec8e JCPV	120	atmel,mux-mask = <
	121	/* A B C */
	122	0xffffffff 0xffe0399f 0xc000001c /* pioA */
	123	0xffffffff 0xffc003ff 0xffc003ff /* pioB */
	124	0xffffffff 0xffc003ff 0xffc003ff /* pioC */
	125	0xffffffff 0xffc003ff 0xffc003ff /* pioD */
	126	>;
	127
	128	/* shared pinctrl settings */
	129
e4541ff2 JCPV	130	pioA: gpio@fffff400 {
	131	compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
	132	reg = <0xfffff400 0x200>;
	133	interrupts = <2 4 1>;
	134	#gpio-cells = <2>;
	135	gpio-controller;
	136	interrupt-controller;
	137	#interrupt-cells = <2>;
	138	};
	139
	140	pioB: gpio@fffff600 {
	141	compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
	142	reg = <0xfffff600 0x200>;
	143	interrupts = <2 4 1>;
	144	#gpio-cells = <2>;
	145	gpio-controller;
fc33ff43	146	#gpio-lines = <19>;
e4541ff2 JCPV	147	interrupt-controller;
	148	#interrupt-cells = <2>;
	149	};
	150
	151	pioC: gpio@fffff800 {
	152	compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
	153	reg = <0xfffff800 0x200>;
	154	interrupts = <3 4 1>;
	155	#gpio-cells = <2>;
	156	gpio-controller;
	157	interrupt-controller;
	158	#interrupt-cells = <2>;
	159	};
	160
	161	pioD: gpio@fffffa00 {
	162	compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
	163	reg = <0xfffffa00 0x200>;
	164	interrupts = <3 4 1>;
	165	#gpio-cells = <2>;
	166	gpio-controller;
fc33ff43	167	#gpio-lines = <22>;
e4541ff2 JCPV	168	interrupt-controller;
	169	#interrupt-cells = <2>;
	170	};
467f1cf5 NF	171	};
	172
	173	dbgu: serial@fffff200 {
	174	compatible = "atmel,at91sam9260-usart";
	175	reg = <0xfffff200 0x200>;
f8a073ee	176	interrupts = <1 4 7>;
467f1cf5 NF	177	status = "disabled";
	178	};
	179
	180	usart0: serial@f801c000 {
	181	compatible = "atmel,at91sam9260-usart";
	182	reg = <0xf801c000 0x200>;
f8a073ee	183	interrupts = <5 4 5>;
467f1cf5 NF	184	atmel,use-dma-rx;
	185	atmel,use-dma-tx;
	186	status = "disabled";
	187	};
	188
	189	usart1: serial@f8020000 {
	190	compatible = "atmel,at91sam9260-usart";
	191	reg = <0xf8020000 0x200>;
f8a073ee	192	interrupts = <6 4 5>;
467f1cf5 NF	193	atmel,use-dma-rx;
	194	atmel,use-dma-tx;
	195	status = "disabled";
	196	};
	197
	198	usart2: serial@f8024000 {
	199	compatible = "atmel,at91sam9260-usart";
	200	reg = <0xf8024000 0x200>;
f8a073ee	201	interrupts = <7 4 5>;
467f1cf5 NF	202	atmel,use-dma-rx;
	203	atmel,use-dma-tx;
	204	status = "disabled";
	205	};
	206
	207	macb0: ethernet@f802c000 {
	208	compatible = "cdns,at32ap7000-macb", "cdns,macb";
	209	reg = <0xf802c000 0x100>;
f8a073ee	210	interrupts = <24 4 3>;
467f1cf5 NF	211	status = "disabled";
	212	};
	213
	214	macb1: ethernet@f8030000 {
	215	compatible = "cdns,at32ap7000-macb", "cdns,macb";
	216	reg = <0xf8030000 0x100>;
f8a073ee	217	interrupts = <27 4 3>;
467f1cf5 NF	218	status = "disabled";
467f1cf5 NF	219	};
d029f371	220
05dcd361 LD	221	i2c0: i2c@f8010000 {
	222	compatible = "atmel,at91sam9x5-i2c";
	223	reg = <0xf8010000 0x100>;
	224	interrupts = <9 4 6>;
	225	#address-cells = <1>;
	226	#size-cells = <0>;
	227	status = "disabled";
	228	};
	229
	230	i2c1: i2c@f8014000 {
	231	compatible = "atmel,at91sam9x5-i2c";
	232	reg = <0xf8014000 0x100>;
	233	interrupts = <10 4 6>;
	234	#address-cells = <1>;
	235	#size-cells = <0>;
	236	status = "disabled";
	237	};
	238
	239	i2c2: i2c@f8018000 {
	240	compatible = "atmel,at91sam9x5-i2c";
	241	reg = <0xf8018000 0x100>;
	242	interrupts = <11 4 6>;
	243	#address-cells = <1>;
	244	#size-cells = <0>;
	245	status = "disabled";
	246	};
	247
d029f371 MR	248	adc0: adc@f804c000 {
	249	compatible = "atmel,at91sam9260-adc";
	250	reg = <0xf804c000 0x100>;
f8a073ee	251	interrupts = <19 4 0>;
d029f371 MR	252	atmel,adc-use-external;
	253	atmel,adc-channels-used = <0xffff>;
	254	atmel,adc-vref = <3300>;
	255	atmel,adc-num-channels = <12>;
	256	atmel,adc-startup-time = <40>;
	257	atmel,adc-channel-base = <0x50>;
	258	atmel,adc-drdy-mask = <0x1000000>;
	259	atmel,adc-status-register = <0x30>;
	260	atmel,adc-trigger-register = <0xc0>;
	261
	262	trigger@0 {
	263	trigger-name = "external-rising";
	264	trigger-value = <0x1>;
	265	trigger-external;
	266	};
	267
	268	trigger@1 {
	269	trigger-name = "external-falling";
	270	trigger-value = <0x2>;
	271	trigger-external;
	272	};
	273
	274	trigger@2 {
	275	trigger-name = "external-any";
	276	trigger-value = <0x3>;
	277	trigger-external;
	278	};
	279
	280	trigger@3 {
	281	trigger-name = "continuous";
	282	trigger-value = <0x6>;
	283	};
	284	};
467f1cf5	285	};
86a89f4f JCPV	286
	287	nand0: nand@40000000 {
	288	compatible = "atmel,at91rm9200-nand";
	289	#address-cells = <1>;
	290	#size-cells = <1>;
	291	reg = <0x40000000 0x10000000
	292	>;
	293	atmel,nand-addr-offset = <21>;
	294	atmel,nand-cmd-offset = <22>;
4352808c NF	295	gpios = <&pioD 5 0
4352808c NF	296	&pioD 4 0
86a89f4f JCPV	297	0
	298	>;
	299	status = "disabled";
	300	};
6a062459 JCPV	301
	302	usb0: ohci@00600000 {
	303	compatible = "atmel,at91rm9200-ohci", "usb-ohci";
	304	reg = <0x00600000 0x100000>;
f8a073ee	305	interrupts = <22 4 2>;
6a062459 JCPV	306	status = "disabled";
6a062459 JCPV	307	};
62c5553a JCPV	308
	309	usb1: ehci@00700000 {
	310	compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
	311	reg = <0x00700000 0x100000>;
f8a073ee	312	interrupts = <22 4 2>;
62c5553a JCPV	313	status = "disabled";
62c5553a JCPV	314	};
467f1cf5	315	};
10f71c28 JCPV	316
	317	i2c@0 {
	318	compatible = "i2c-gpio";
	319	gpios = <&pioA 30 0 /* sda */
	320	&pioA 31 0 /* scl */
	321	>;
	322	i2c-gpio,sda-open-drain;
	323	i2c-gpio,scl-open-drain;
	324	i2c-gpio,delay-us = <2>; /* ~100 kHz */
	325	#address-cells = <1>;
	326	#size-cells = <0>;
	327	status = "disabled";
	328	};
	329
	330	i2c@1 {
	331	compatible = "i2c-gpio";
	332	gpios = <&pioC 0 0 /* sda */
	333	&pioC 1 0 /* scl */
	334	>;
	335	i2c-gpio,sda-open-drain;
	336	i2c-gpio,scl-open-drain;
	337	i2c-gpio,delay-us = <2>; /* ~100 kHz */
	338	#address-cells = <1>;
	339	#size-cells = <0>;
	340	status = "disabled";
	341	};
	342
	343	i2c@2 {
	344	compatible = "i2c-gpio";
	345	gpios = <&pioB 4 0 /* sda */
	346	&pioB 5 0 /* scl */
	347	>;
	348	i2c-gpio,sda-open-drain;
	349	i2c-gpio,scl-open-drain;
	350	i2c-gpio,delay-us = <2>; /* ~100 kHz */
	351	#address-cells = <1>;
	352	#size-cells = <0>;
	353	status = "disabled";
	354	};
467f1cf5	355	};