Commit | Line | Data |
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467f1cf5 NF |
1 | /* |
2 | * at91sam9x5.dtsi - Device Tree Include file for AT91SAM9x5 family SoC | |
3 | * applies to AT91SAM9G15, AT91SAM9G25, AT91SAM9G35, | |
4 | * AT91SAM9X25, AT91SAM9X35 SoC | |
5 | * | |
6 | * Copyright (C) 2012 Atmel, | |
7 | * 2012 Nicolas Ferre <nicolas.ferre@atmel.com> | |
8 | * | |
9 | * Licensed under GPLv2 or later. | |
10 | */ | |
11 | ||
12 | /include/ "skeleton.dtsi" | |
13 | ||
14 | / { | |
15 | model = "Atmel AT91SAM9x5 family SoC"; | |
16 | compatible = "atmel,at91sam9x5"; | |
17 | interrupt-parent = <&aic>; | |
18 | ||
19 | aliases { | |
20 | serial0 = &dbgu; | |
21 | serial1 = &usart0; | |
22 | serial2 = &usart1; | |
23 | serial3 = &usart2; | |
24 | gpio0 = &pioA; | |
25 | gpio1 = &pioB; | |
26 | gpio2 = &pioC; | |
27 | gpio3 = &pioD; | |
28 | tcb0 = &tcb0; | |
29 | tcb1 = &tcb1; | |
05dcd361 LD |
30 | i2c0 = &i2c0; |
31 | i2c1 = &i2c1; | |
32 | i2c2 = &i2c2; | |
099343c6 | 33 | ssc0 = &ssc0; |
467f1cf5 NF |
34 | }; |
35 | cpus { | |
36 | cpu@0 { | |
37 | compatible = "arm,arm926ejs"; | |
38 | }; | |
39 | }; | |
40 | ||
dcce6ce8 | 41 | memory { |
467f1cf5 NF |
42 | reg = <0x20000000 0x10000000>; |
43 | }; | |
44 | ||
45 | ahb { | |
46 | compatible = "simple-bus"; | |
47 | #address-cells = <1>; | |
48 | #size-cells = <1>; | |
49 | ranges; | |
50 | ||
51 | apb { | |
52 | compatible = "simple-bus"; | |
53 | #address-cells = <1>; | |
54 | #size-cells = <1>; | |
55 | ranges; | |
56 | ||
57 | aic: interrupt-controller@fffff000 { | |
f8a073ee | 58 | #interrupt-cells = <3>; |
467f1cf5 NF |
59 | compatible = "atmel,at91rm9200-aic"; |
60 | interrupt-controller; | |
467f1cf5 | 61 | reg = <0xfffff000 0x200>; |
c6573943 | 62 | atmel,external-irqs = <31>; |
467f1cf5 NF |
63 | }; |
64 | ||
a7776ec6 JCPV |
65 | ramc0: ramc@ffffe800 { |
66 | compatible = "atmel,at91sam9g45-ddramc"; | |
67 | reg = <0xffffe800 0x200>; | |
68 | }; | |
69 | ||
eb5e76ff JCPV |
70 | pmc: pmc@fffffc00 { |
71 | compatible = "atmel,at91rm9200-pmc"; | |
72 | reg = <0xfffffc00 0x100>; | |
73 | }; | |
74 | ||
c8082d34 JCPV |
75 | rstc@fffffe00 { |
76 | compatible = "atmel,at91sam9g45-rstc"; | |
77 | reg = <0xfffffe00 0x10>; | |
78 | }; | |
79 | ||
82015c4e JCPV |
80 | shdwc@fffffe10 { |
81 | compatible = "atmel,at91sam9x5-shdwc"; | |
82 | reg = <0xfffffe10 0x10>; | |
83 | }; | |
84 | ||
467f1cf5 NF |
85 | pit: timer@fffffe30 { |
86 | compatible = "atmel,at91sam9260-pit"; | |
87 | reg = <0xfffffe30 0xf>; | |
f8a073ee | 88 | interrupts = <1 4 7>; |
467f1cf5 NF |
89 | }; |
90 | ||
91 | tcb0: timer@f8008000 { | |
92 | compatible = "atmel,at91sam9x5-tcb"; | |
93 | reg = <0xf8008000 0x100>; | |
f8a073ee | 94 | interrupts = <17 4 0>; |
467f1cf5 NF |
95 | }; |
96 | ||
97 | tcb1: timer@f800c000 { | |
98 | compatible = "atmel,at91sam9x5-tcb"; | |
99 | reg = <0xf800c000 0x100>; | |
f8a073ee | 100 | interrupts = <17 4 0>; |
467f1cf5 NF |
101 | }; |
102 | ||
103 | dma0: dma-controller@ffffec00 { | |
104 | compatible = "atmel,at91sam9g45-dma"; | |
105 | reg = <0xffffec00 0x200>; | |
f8a073ee | 106 | interrupts = <20 4 0>; |
467f1cf5 NF |
107 | }; |
108 | ||
109 | dma1: dma-controller@ffffee00 { | |
110 | compatible = "atmel,at91sam9g45-dma"; | |
111 | reg = <0xffffee00 0x200>; | |
f8a073ee | 112 | interrupts = <21 4 0>; |
467f1cf5 NF |
113 | }; |
114 | ||
ec6754a7 | 115 | pinctrl@fffff400 { |
e4541ff2 JCPV |
116 | #address-cells = <1>; |
117 | #size-cells = <1>; | |
5314ec8e | 118 | compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus"; |
e4541ff2 JCPV |
119 | ranges = <0xfffff400 0xfffff400 0x800>; |
120 | ||
5314ec8e | 121 | /* shared pinctrl settings */ |
ec6754a7 JCPV |
122 | dbgu { |
123 | pinctrl_dbgu: dbgu-0 { | |
124 | atmel,pins = | |
125 | <0 9 0x1 0x0 /* PA9 periph A */ | |
126 | 0 10 0x1 0x1>; /* PA10 periph A with pullup */ | |
127 | }; | |
128 | }; | |
129 | ||
9e3129e9 JCPV |
130 | usart0 { |
131 | pinctrl_usart0: usart0-0 { | |
ec6754a7 JCPV |
132 | atmel,pins = |
133 | <0 0 0x1 0x1 /* PA0 periph A with pullup */ | |
134 | 0 1 0x1 0x0>; /* PA1 periph A */ | |
135 | }; | |
136 | ||
c58c0c5a | 137 | pinctrl_usart0_rts: usart0_rts-0 { |
ec6754a7 | 138 | atmel,pins = |
c58c0c5a JCPV |
139 | <0 2 0x1 0x0>; /* PA2 periph A */ |
140 | }; | |
141 | ||
142 | pinctrl_usart0_cts: usart0_cts-0 { | |
143 | atmel,pins = | |
144 | <0 3 0x1 0x0>; /* PA3 periph A */ | |
ec6754a7 | 145 | }; |
1bab02ec RG |
146 | |
147 | pinctrl_usart0_sck: usart0_sck-0 { | |
148 | atmel,pins = | |
149 | <0 4 0x1 0x0>; /* PA4 periph A */ | |
150 | }; | |
ec6754a7 JCPV |
151 | }; |
152 | ||
9e3129e9 JCPV |
153 | usart1 { |
154 | pinctrl_usart1: usart1-0 { | |
ec6754a7 JCPV |
155 | atmel,pins = |
156 | <0 5 0x1 0x1 /* PA5 periph A with pullup */ | |
157 | 0 6 0x1 0x0>; /* PA6 periph A */ | |
158 | }; | |
159 | ||
c58c0c5a JCPV |
160 | pinctrl_usart1_rts: usart1_rts-0 { |
161 | atmel,pins = | |
c89cec3a | 162 | <2 27 0x3 0x0>; /* PC27 periph C */ |
c58c0c5a JCPV |
163 | }; |
164 | ||
165 | pinctrl_usart1_cts: usart1_cts-0 { | |
ec6754a7 | 166 | atmel,pins = |
c89cec3a | 167 | <2 28 0x3 0x0>; /* PC28 periph C */ |
ec6754a7 | 168 | }; |
1bab02ec RG |
169 | |
170 | pinctrl_usart1_sck: usart1_sck-0 { | |
171 | atmel,pins = | |
172 | <2 28 0x3 0x0>; /* PC29 periph C */ | |
173 | }; | |
ec6754a7 JCPV |
174 | }; |
175 | ||
9e3129e9 JCPV |
176 | usart2 { |
177 | pinctrl_usart2: usart2-0 { | |
ec6754a7 JCPV |
178 | atmel,pins = |
179 | <0 7 0x1 0x1 /* PA7 periph A with pullup */ | |
180 | 0 8 0x1 0x0>; /* PA8 periph A */ | |
181 | }; | |
182 | ||
c58c0c5a | 183 | pinctrl_uart2_rts: uart2_rts-0 { |
ec6754a7 | 184 | atmel,pins = |
c89cec3a | 185 | <1 0 0x2 0x0>; /* PB0 periph B */ |
c58c0c5a JCPV |
186 | }; |
187 | ||
188 | pinctrl_uart2_cts: uart2_cts-0 { | |
189 | atmel,pins = | |
c89cec3a | 190 | <1 1 0x2 0x0>; /* PB1 periph B */ |
ec6754a7 | 191 | }; |
1bab02ec RG |
192 | |
193 | pinctrl_usart2_sck: usart2_sck-0 { | |
194 | atmel,pins = | |
195 | <1 2 0x2 0x0>; /* PB2 periph B */ | |
196 | }; | |
ec6754a7 JCPV |
197 | }; |
198 | ||
9e3129e9 | 199 | usart3 { |
65a0fe04 | 200 | pinctrl_usart3: usart3-0 { |
ec6754a7 | 201 | atmel,pins = |
7d4cfece | 202 | <2 22 0x2 0x1 /* PC22 periph B with pullup */ |
c89cec3a | 203 | 2 23 0x2 0x0>; /* PC23 periph B */ |
ec6754a7 JCPV |
204 | }; |
205 | ||
c58c0c5a JCPV |
206 | pinctrl_usart3_rts: usart3_rts-0 { |
207 | atmel,pins = | |
c89cec3a | 208 | <2 24 0x2 0x0>; /* PC24 periph B */ |
c58c0c5a JCPV |
209 | }; |
210 | ||
211 | pinctrl_usart3_cts: usart3_cts-0 { | |
ec6754a7 | 212 | atmel,pins = |
c89cec3a | 213 | <2 25 0x2 0x0>; /* PC25 periph B */ |
ec6754a7 | 214 | }; |
1bab02ec RG |
215 | |
216 | pinctrl_usart3_sck: usart3_sck-0 { | |
217 | atmel,pins = | |
218 | <2 26 0x2 0x0>; /* PC26 periph B */ | |
219 | }; | |
ec6754a7 JCPV |
220 | }; |
221 | ||
9e3129e9 JCPV |
222 | uart0 { |
223 | pinctrl_uart0: uart0-0 { | |
ec6754a7 | 224 | atmel,pins = |
c89cec3a RG |
225 | <2 8 0x3 0x0 /* PC8 periph C */ |
226 | 2 9 0x3 0x1>; /* PC9 periph C with pullup */ | |
ec6754a7 JCPV |
227 | }; |
228 | }; | |
229 | ||
9e3129e9 JCPV |
230 | uart1 { |
231 | pinctrl_uart1: uart1-0 { | |
ec6754a7 | 232 | atmel,pins = |
c89cec3a RG |
233 | <2 16 0x3 0x0 /* PC16 periph C */ |
234 | 2 17 0x3 0x1>; /* PC17 periph C with pullup */ | |
ec6754a7 JCPV |
235 | }; |
236 | }; | |
5314ec8e | 237 | |
7a38d450 JCPV |
238 | nand { |
239 | pinctrl_nand: nand-0 { | |
240 | atmel,pins = | |
7f06472f RG |
241 | <3 0 0x1 0x0 /* PD0 periph A Read Enable */ |
242 | 3 1 0x1 0x0 /* PD1 periph A Write Enable */ | |
243 | 3 2 0x1 0x0 /* PD2 periph A Address Latch Enable */ | |
244 | 3 3 0x1 0x0 /* PD3 periph A Command Latch Enable */ | |
245 | 3 4 0x0 0x1 /* PD4 gpio Chip Enable pin pull_up */ | |
246 | 3 5 0x0 0x1 /* PD5 gpio RDY/BUSY pin pull_up */ | |
247 | 3 6 0x1 0x0 /* PD6 periph A Data bit 0 */ | |
248 | 3 7 0x1 0x0 /* PD7 periph A Data bit 1 */ | |
249 | 3 8 0x1 0x0 /* PD8 periph A Data bit 2 */ | |
250 | 3 9 0x1 0x0 /* PD9 periph A Data bit 3 */ | |
251 | 3 10 0x1 0x0 /* PD10 periph A Data bit 4 */ | |
252 | 3 11 0x1 0x0 /* PD11 periph A Data bit 5 */ | |
253 | 3 12 0x1 0x0 /* PD12 periph A Data bit 6 */ | |
254 | 3 13 0x1 0x0>; /* PD13 periph A Data bit 7 */ | |
255 | }; | |
256 | ||
257 | pinctrl_nand_16bits: nand_16bits-0 { | |
258 | atmel,pins = | |
259 | <3 14 0x1 0x0 /* PD14 periph A Data bit 8 */ | |
260 | 3 15 0x1 0x0 /* PD15 periph A Data bit 9 */ | |
261 | 3 16 0x1 0x0 /* PD16 periph A Data bit 10 */ | |
262 | 3 17 0x1 0x0 /* PD17 periph A Data bit 11 */ | |
263 | 3 18 0x1 0x0 /* PD18 periph A Data bit 12 */ | |
264 | 3 19 0x1 0x0 /* PD19 periph A Data bit 13 */ | |
265 | 3 20 0x1 0x0 /* PD20 periph A Data bit 14 */ | |
266 | 3 21 0x1 0x0>; /* PD21 periph A Data bit 15 */ | |
7a38d450 JCPV |
267 | }; |
268 | }; | |
269 | ||
d9b4fe83 JCPV |
270 | macb0 { |
271 | pinctrl_macb0_rmii: macb0_rmii-0 { | |
272 | atmel,pins = | |
273 | <1 0 0x1 0x0 /* PB0 periph A */ | |
274 | 1 1 0x1 0x0 /* PB1 periph A */ | |
275 | 1 2 0x1 0x0 /* PB2 periph A */ | |
276 | 1 3 0x1 0x0 /* PB3 periph A */ | |
277 | 1 4 0x1 0x0 /* PB4 periph A */ | |
278 | 1 5 0x1 0x0 /* PB5 periph A */ | |
279 | 1 6 0x1 0x0 /* PB6 periph A */ | |
280 | 1 7 0x1 0x0 /* PB7 periph A */ | |
281 | 1 9 0x1 0x0 /* PB9 periph A */ | |
282 | 1 10 0x1 0x0>; /* PB10 periph A */ | |
283 | }; | |
284 | ||
285 | pinctrl_macb0_rmii_mii: macb0_rmii_mii-0 { | |
286 | atmel,pins = | |
8461c2f6 DG |
287 | <1 8 0x1 0x0 /* PB8 periph A */ |
288 | 1 11 0x1 0x0 /* PB11 periph A */ | |
289 | 1 12 0x1 0x0 /* PB12 periph A */ | |
290 | 1 13 0x1 0x0 /* PB13 periph A */ | |
291 | 1 14 0x1 0x0 /* PB14 periph A */ | |
292 | 1 15 0x1 0x0 /* PB15 periph A */ | |
293 | 1 16 0x1 0x0 /* PB16 periph A */ | |
294 | 1 17 0x1 0x0>; /* PB17 periph A */ | |
d9b4fe83 JCPV |
295 | }; |
296 | }; | |
297 | ||
d4fe9ac7 JCPV |
298 | mmc0 { |
299 | pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 { | |
300 | atmel,pins = | |
301 | <0 17 0x1 0x0 /* PA17 periph A */ | |
302 | 0 16 0x1 0x1 /* PA16 periph A with pullup */ | |
303 | 0 15 0x1 0x1>; /* PA15 periph A with pullup */ | |
304 | }; | |
305 | ||
306 | pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 { | |
307 | atmel,pins = | |
308 | <0 18 0x1 0x1 /* PA18 periph A with pullup */ | |
309 | 0 19 0x1 0x1 /* PA19 periph A with pullup */ | |
310 | 0 20 0x1 0x1>; /* PA20 periph A with pullup */ | |
311 | }; | |
312 | }; | |
313 | ||
314 | mmc1 { | |
315 | pinctrl_mmc1_slot0_clk_cmd_dat0: mmc1_slot0_clk_cmd_dat0-0 { | |
316 | atmel,pins = | |
317 | <0 13 0x2 0x0 /* PA13 periph B */ | |
318 | 0 12 0x2 0x1 /* PA12 periph B with pullup */ | |
319 | 0 11 0x2 0x1>; /* PA11 periph B with pullup */ | |
320 | }; | |
321 | ||
322 | pinctrl_mmc1_slot0_dat1_3: mmc1_slot0_dat1_3-0 { | |
323 | atmel,pins = | |
324 | <0 2 0x2 0x1 /* PA2 periph B with pullup */ | |
325 | 0 3 0x2 0x1 /* PA3 periph B with pullup */ | |
326 | 0 4 0x2 0x1>; /* PA4 periph B with pullup */ | |
327 | }; | |
328 | }; | |
329 | ||
544ae6b2 BS |
330 | ssc0 { |
331 | pinctrl_ssc0_tx: ssc0_tx-0 { | |
332 | atmel,pins = | |
333 | <0 24 0x2 0x0 /* PA24 periph B */ | |
334 | 0 25 0x2 0x0 /* PA25 periph B */ | |
335 | 0 26 0x2 0x0>; /* PA26 periph B */ | |
336 | }; | |
337 | ||
338 | pinctrl_ssc0_rx: ssc0_rx-0 { | |
339 | atmel,pins = | |
340 | <0 27 0x2 0x0 /* PA27 periph B */ | |
341 | 0 28 0x2 0x0 /* PA28 periph B */ | |
342 | 0 29 0x2 0x0>; /* PA29 periph B */ | |
343 | }; | |
344 | }; | |
345 | ||
a68b728f WY |
346 | spi0 { |
347 | pinctrl_spi0: spi0-0 { | |
348 | atmel,pins = | |
349 | <0 11 0x1 0x0 /* PA11 periph A SPI0_MISO pin */ | |
350 | 0 12 0x1 0x0 /* PA12 periph A SPI0_MOSI pin */ | |
351 | 0 13 0x1 0x0>; /* PA13 periph A SPI0_SPCK pin */ | |
352 | }; | |
353 | }; | |
354 | ||
355 | spi1 { | |
356 | pinctrl_spi1: spi1-0 { | |
357 | atmel,pins = | |
358 | <0 21 0x2 0x0 /* PA21 periph B SPI1_MISO pin */ | |
359 | 0 22 0x2 0x0 /* PA22 periph B SPI1_MOSI pin */ | |
360 | 0 23 0x2 0x0>; /* PA23 periph B SPI1_SPCK pin */ | |
361 | }; | |
362 | }; | |
363 | ||
e4541ff2 JCPV |
364 | pioA: gpio@fffff400 { |
365 | compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; | |
366 | reg = <0xfffff400 0x200>; | |
367 | interrupts = <2 4 1>; | |
368 | #gpio-cells = <2>; | |
369 | gpio-controller; | |
370 | interrupt-controller; | |
371 | #interrupt-cells = <2>; | |
372 | }; | |
373 | ||
374 | pioB: gpio@fffff600 { | |
375 | compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; | |
376 | reg = <0xfffff600 0x200>; | |
377 | interrupts = <2 4 1>; | |
378 | #gpio-cells = <2>; | |
379 | gpio-controller; | |
fc33ff43 | 380 | #gpio-lines = <19>; |
e4541ff2 JCPV |
381 | interrupt-controller; |
382 | #interrupt-cells = <2>; | |
383 | }; | |
384 | ||
385 | pioC: gpio@fffff800 { | |
386 | compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; | |
387 | reg = <0xfffff800 0x200>; | |
388 | interrupts = <3 4 1>; | |
389 | #gpio-cells = <2>; | |
390 | gpio-controller; | |
391 | interrupt-controller; | |
392 | #interrupt-cells = <2>; | |
393 | }; | |
394 | ||
395 | pioD: gpio@fffffa00 { | |
396 | compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; | |
397 | reg = <0xfffffa00 0x200>; | |
398 | interrupts = <3 4 1>; | |
399 | #gpio-cells = <2>; | |
400 | gpio-controller; | |
fc33ff43 | 401 | #gpio-lines = <22>; |
e4541ff2 JCPV |
402 | interrupt-controller; |
403 | #interrupt-cells = <2>; | |
404 | }; | |
467f1cf5 NF |
405 | }; |
406 | ||
544ae6b2 BS |
407 | ssc0: ssc@f0010000 { |
408 | compatible = "atmel,at91sam9g45-ssc"; | |
409 | reg = <0xf0010000 0x4000>; | |
410 | interrupts = <28 4 5>; | |
411 | pinctrl-names = "default"; | |
412 | pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; | |
413 | status = "disabled"; | |
414 | }; | |
415 | ||
9873137a LD |
416 | mmc0: mmc@f0008000 { |
417 | compatible = "atmel,hsmci"; | |
418 | reg = <0xf0008000 0x600>; | |
419 | interrupts = <12 4 0>; | |
420 | #address-cells = <1>; | |
421 | #size-cells = <0>; | |
422 | status = "disabled"; | |
423 | }; | |
424 | ||
425 | mmc1: mmc@f000c000 { | |
426 | compatible = "atmel,hsmci"; | |
427 | reg = <0xf000c000 0x600>; | |
428 | interrupts = <26 4 0>; | |
429 | #address-cells = <1>; | |
430 | #size-cells = <0>; | |
431 | status = "disabled"; | |
432 | }; | |
433 | ||
467f1cf5 NF |
434 | dbgu: serial@fffff200 { |
435 | compatible = "atmel,at91sam9260-usart"; | |
436 | reg = <0xfffff200 0x200>; | |
f8a073ee | 437 | interrupts = <1 4 7>; |
ec6754a7 JCPV |
438 | pinctrl-names = "default"; |
439 | pinctrl-0 = <&pinctrl_dbgu>; | |
467f1cf5 NF |
440 | status = "disabled"; |
441 | }; | |
442 | ||
443 | usart0: serial@f801c000 { | |
444 | compatible = "atmel,at91sam9260-usart"; | |
445 | reg = <0xf801c000 0x200>; | |
f8a073ee | 446 | interrupts = <5 4 5>; |
ec6754a7 | 447 | pinctrl-names = "default"; |
9e3129e9 | 448 | pinctrl-0 = <&pinctrl_usart0>; |
467f1cf5 NF |
449 | status = "disabled"; |
450 | }; | |
451 | ||
452 | usart1: serial@f8020000 { | |
453 | compatible = "atmel,at91sam9260-usart"; | |
454 | reg = <0xf8020000 0x200>; | |
f8a073ee | 455 | interrupts = <6 4 5>; |
ec6754a7 | 456 | pinctrl-names = "default"; |
9e3129e9 | 457 | pinctrl-0 = <&pinctrl_usart1>; |
467f1cf5 NF |
458 | status = "disabled"; |
459 | }; | |
460 | ||
461 | usart2: serial@f8024000 { | |
462 | compatible = "atmel,at91sam9260-usart"; | |
463 | reg = <0xf8024000 0x200>; | |
f8a073ee | 464 | interrupts = <7 4 5>; |
ec6754a7 | 465 | pinctrl-names = "default"; |
9e3129e9 | 466 | pinctrl-0 = <&pinctrl_usart2>; |
467f1cf5 NF |
467 | status = "disabled"; |
468 | }; | |
469 | ||
470 | macb0: ethernet@f802c000 { | |
471 | compatible = "cdns,at32ap7000-macb", "cdns,macb"; | |
472 | reg = <0xf802c000 0x100>; | |
f8a073ee | 473 | interrupts = <24 4 3>; |
d9b4fe83 JCPV |
474 | pinctrl-names = "default"; |
475 | pinctrl-0 = <&pinctrl_macb0_rmii>; | |
467f1cf5 NF |
476 | status = "disabled"; |
477 | }; | |
478 | ||
479 | macb1: ethernet@f8030000 { | |
480 | compatible = "cdns,at32ap7000-macb", "cdns,macb"; | |
481 | reg = <0xf8030000 0x100>; | |
f8a073ee | 482 | interrupts = <27 4 3>; |
467f1cf5 NF |
483 | status = "disabled"; |
484 | }; | |
d029f371 | 485 | |
05dcd361 LD |
486 | i2c0: i2c@f8010000 { |
487 | compatible = "atmel,at91sam9x5-i2c"; | |
488 | reg = <0xf8010000 0x100>; | |
489 | interrupts = <9 4 6>; | |
490 | #address-cells = <1>; | |
491 | #size-cells = <0>; | |
492 | status = "disabled"; | |
493 | }; | |
494 | ||
495 | i2c1: i2c@f8014000 { | |
496 | compatible = "atmel,at91sam9x5-i2c"; | |
497 | reg = <0xf8014000 0x100>; | |
498 | interrupts = <10 4 6>; | |
499 | #address-cells = <1>; | |
500 | #size-cells = <0>; | |
501 | status = "disabled"; | |
502 | }; | |
503 | ||
504 | i2c2: i2c@f8018000 { | |
505 | compatible = "atmel,at91sam9x5-i2c"; | |
506 | reg = <0xf8018000 0x100>; | |
507 | interrupts = <11 4 6>; | |
508 | #address-cells = <1>; | |
509 | #size-cells = <0>; | |
510 | status = "disabled"; | |
511 | }; | |
512 | ||
d029f371 MR |
513 | adc0: adc@f804c000 { |
514 | compatible = "atmel,at91sam9260-adc"; | |
515 | reg = <0xf804c000 0x100>; | |
f8a073ee | 516 | interrupts = <19 4 0>; |
d029f371 MR |
517 | atmel,adc-use-external; |
518 | atmel,adc-channels-used = <0xffff>; | |
519 | atmel,adc-vref = <3300>; | |
520 | atmel,adc-num-channels = <12>; | |
521 | atmel,adc-startup-time = <40>; | |
522 | atmel,adc-channel-base = <0x50>; | |
523 | atmel,adc-drdy-mask = <0x1000000>; | |
524 | atmel,adc-status-register = <0x30>; | |
525 | atmel,adc-trigger-register = <0xc0>; | |
526 | ||
527 | trigger@0 { | |
528 | trigger-name = "external-rising"; | |
529 | trigger-value = <0x1>; | |
530 | trigger-external; | |
531 | }; | |
532 | ||
533 | trigger@1 { | |
534 | trigger-name = "external-falling"; | |
535 | trigger-value = <0x2>; | |
536 | trigger-external; | |
537 | }; | |
538 | ||
539 | trigger@2 { | |
540 | trigger-name = "external-any"; | |
541 | trigger-value = <0x3>; | |
542 | trigger-external; | |
543 | }; | |
544 | ||
545 | trigger@3 { | |
546 | trigger-name = "continuous"; | |
547 | trigger-value = <0x6>; | |
548 | }; | |
549 | }; | |
d50f88a0 RG |
550 | |
551 | spi0: spi@f0000000 { | |
552 | #address-cells = <1>; | |
553 | #size-cells = <0>; | |
554 | compatible = "atmel,at91rm9200-spi"; | |
555 | reg = <0xf0000000 0x100>; | |
556 | interrupts = <13 4 3>; | |
a68b728f WY |
557 | pinctrl-names = "default"; |
558 | pinctrl-0 = <&pinctrl_spi0>; | |
d50f88a0 RG |
559 | status = "disabled"; |
560 | }; | |
561 | ||
562 | spi1: spi@f0004000 { | |
563 | #address-cells = <1>; | |
564 | #size-cells = <0>; | |
565 | compatible = "atmel,at91rm9200-spi"; | |
566 | reg = <0xf0004000 0x100>; | |
567 | interrupts = <14 4 3>; | |
a68b728f WY |
568 | pinctrl-names = "default"; |
569 | pinctrl-0 = <&pinctrl_spi1>; | |
d50f88a0 RG |
570 | status = "disabled"; |
571 | }; | |
467f1cf5 | 572 | }; |
86a89f4f JCPV |
573 | |
574 | nand0: nand@40000000 { | |
575 | compatible = "atmel,at91rm9200-nand"; | |
576 | #address-cells = <1>; | |
577 | #size-cells = <1>; | |
578 | reg = <0x40000000 0x10000000 | |
5314bc2d JW |
579 | 0xffffe000 0x600 /* PMECC Registers */ |
580 | 0xffffe600 0x200 /* PMECC Error Location Registers */ | |
581 | 0x00108000 0x18000 /* PMECC looup table in ROM code */ | |
86a89f4f | 582 | >; |
5314bc2d | 583 | atmel,pmecc-lookup-table-offset = <0x0 0x8000>; |
86a89f4f JCPV |
584 | atmel,nand-addr-offset = <21>; |
585 | atmel,nand-cmd-offset = <22>; | |
7a38d450 JCPV |
586 | pinctrl-names = "default"; |
587 | pinctrl-0 = <&pinctrl_nand>; | |
4352808c NF |
588 | gpios = <&pioD 5 0 |
589 | &pioD 4 0 | |
86a89f4f JCPV |
590 | 0 |
591 | >; | |
592 | status = "disabled"; | |
593 | }; | |
6a062459 JCPV |
594 | |
595 | usb0: ohci@00600000 { | |
596 | compatible = "atmel,at91rm9200-ohci", "usb-ohci"; | |
597 | reg = <0x00600000 0x100000>; | |
f8a073ee | 598 | interrupts = <22 4 2>; |
6a062459 JCPV |
599 | status = "disabled"; |
600 | }; | |
62c5553a JCPV |
601 | |
602 | usb1: ehci@00700000 { | |
603 | compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; | |
604 | reg = <0x00700000 0x100000>; | |
f8a073ee | 605 | interrupts = <22 4 2>; |
62c5553a JCPV |
606 | status = "disabled"; |
607 | }; | |
467f1cf5 | 608 | }; |
10f71c28 JCPV |
609 | |
610 | i2c@0 { | |
611 | compatible = "i2c-gpio"; | |
612 | gpios = <&pioA 30 0 /* sda */ | |
613 | &pioA 31 0 /* scl */ | |
614 | >; | |
615 | i2c-gpio,sda-open-drain; | |
616 | i2c-gpio,scl-open-drain; | |
617 | i2c-gpio,delay-us = <2>; /* ~100 kHz */ | |
618 | #address-cells = <1>; | |
619 | #size-cells = <0>; | |
620 | status = "disabled"; | |
621 | }; | |
622 | ||
623 | i2c@1 { | |
624 | compatible = "i2c-gpio"; | |
625 | gpios = <&pioC 0 0 /* sda */ | |
626 | &pioC 1 0 /* scl */ | |
627 | >; | |
628 | i2c-gpio,sda-open-drain; | |
629 | i2c-gpio,scl-open-drain; | |
630 | i2c-gpio,delay-us = <2>; /* ~100 kHz */ | |
631 | #address-cells = <1>; | |
632 | #size-cells = <0>; | |
633 | status = "disabled"; | |
634 | }; | |
635 | ||
636 | i2c@2 { | |
637 | compatible = "i2c-gpio"; | |
638 | gpios = <&pioB 4 0 /* sda */ | |
639 | &pioB 5 0 /* scl */ | |
640 | >; | |
641 | i2c-gpio,sda-open-drain; | |
642 | i2c-gpio,scl-open-drain; | |
643 | i2c-gpio,delay-us = <2>; /* ~100 kHz */ | |
644 | #address-cells = <1>; | |
645 | #size-cells = <0>; | |
646 | status = "disabled"; | |
647 | }; | |
467f1cf5 | 648 | }; |