[deliverable/linux.git] / arch / arm / boot / dts / at91sam9x5.dtsi

/*
 * at91sam9x5.dtsi - Device Tree Include file for AT91SAM9x5 family SoC
 *                   applies to AT91SAM9G15, AT91SAM9G25, AT91SAM9G35,
 *                   AT91SAM9X25, AT91SAM9X35 SoC
 *
 *  Copyright (C) 2012 Atmel,
 *                2012 Nicolas Ferre <nicolas.ferre@atmel.com>
 *
 * Licensed under GPLv2 or later.
 */

/include/ "skeleton.dtsi"

/ {
	model = "Atmel AT91SAM9x5 family SoC";
	compatible = "atmel,at91sam9x5";
	interrupt-parent = <&aic>;

	aliases {
		serial0 = &dbgu;
		serial1 = &usart0;
		serial2 = &usart1;
		serial3 = &usart2;
		gpio0 = &pioA;
		gpio1 = &pioB;
		gpio2 = &pioC;
		gpio3 = &pioD;
		tcb0 = &tcb0;
		tcb1 = &tcb1;
		i2c0 = &i2c0;
		i2c1 = &i2c1;
		i2c2 = &i2c2;
	};
	cpus {
		cpu@0 {
			compatible = "arm,arm926ejs";
		};
	};

	memory {
		reg = <0x20000000 0x10000000>;
	};

	ahb {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		apb {
			compatible = "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

			aic: interrupt-controller@fffff000 {
				#interrupt-cells = <3>;
				compatible = "atmel,at91rm9200-aic";
				interrupt-controller;
				reg = <0xfffff000 0x200>;
				atmel,external-irqs = <31>;
			};

			ramc0: ramc@ffffe800 {
				compatible = "atmel,at91sam9g45-ddramc";
				reg = <0xffffe800 0x200>;
			};

			pmc: pmc@fffffc00 {
				compatible = "atmel,at91rm9200-pmc";
				reg = <0xfffffc00 0x100>;
			};

			rstc@fffffe00 {
				compatible = "atmel,at91sam9g45-rstc";
				reg = <0xfffffe00 0x10>;
			};

			shdwc@fffffe10 {
				compatible = "atmel,at91sam9x5-shdwc";
				reg = <0xfffffe10 0x10>;
			};

			pit: timer@fffffe30 {
				compatible = "atmel,at91sam9260-pit";
				reg = <0xfffffe30 0xf>;
				interrupts = <1 4 7>;
			};

			tcb0: timer@f8008000 {
				compatible = "atmel,at91sam9x5-tcb";
				reg = <0xf8008000 0x100>;
				interrupts = <17 4 0>;
			};

			tcb1: timer@f800c000 {
				compatible = "atmel,at91sam9x5-tcb";
				reg = <0xf800c000 0x100>;
				interrupts = <17 4 0>;
			};

			dma0: dma-controller@ffffec00 {
				compatible = "atmel,at91sam9g45-dma";
				reg = <0xffffec00 0x200>;
				interrupts = <20 4 0>;
			};

			dma1: dma-controller@ffffee00 {
				compatible = "atmel,at91sam9g45-dma";
				reg = <0xffffee00 0x200>;
				interrupts = <21 4 0>;
			};

			pioA: gpio@fffff400 {
				compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
				reg = <0xfffff400 0x100>;
				interrupts = <2 4 1>;
				#gpio-cells = <2>;
				gpio-controller;
				interrupt-controller;
				#interrupt-cells = <2>;
			};

			pioB: gpio@fffff600 {
				compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
				reg = <0xfffff600 0x100>;
				interrupts = <2 4 1>;
				#gpio-cells = <2>;
				gpio-controller;
				interrupt-controller;
				#interrupt-cells = <2>;
			};

			pioC: gpio@fffff800 {
				compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
				reg = <0xfffff800 0x100>;
				interrupts = <3 4 1>;
				#gpio-cells = <2>;
				gpio-controller;
				interrupt-controller;
				#interrupt-cells = <2>;
			};

			pioD: gpio@fffffa00 {
				compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
				reg = <0xfffffa00 0x100>;
				interrupts = <3 4 1>;
				#gpio-cells = <2>;
				gpio-controller;
				interrupt-controller;
				#interrupt-cells = <2>;
			};

			dbgu: serial@fffff200 {
				compatible = "atmel,at91sam9260-usart";
				reg = <0xfffff200 0x200>;
				interrupts = <1 4 7>;
				status = "disabled";
			};

			usart0: serial@f801c000 {
				compatible = "atmel,at91sam9260-usart";
				reg = <0xf801c000 0x200>;
				interrupts = <5 4 5>;
				atmel,use-dma-rx;
				atmel,use-dma-tx;
				status = "disabled";
			};

			usart1: serial@f8020000 {
				compatible = "atmel,at91sam9260-usart";
				reg = <0xf8020000 0x200>;
				interrupts = <6 4 5>;
				atmel,use-dma-rx;
				atmel,use-dma-tx;
				status = "disabled";
			};

			usart2: serial@f8024000 {
				compatible = "atmel,at91sam9260-usart";
				reg = <0xf8024000 0x200>;
				interrupts = <7 4 5>;
				atmel,use-dma-rx;
				atmel,use-dma-tx;
				status = "disabled";
			};

			macb0: ethernet@f802c000 {
				compatible = "cdns,at32ap7000-macb", "cdns,macb";
				reg = <0xf802c000 0x100>;
				interrupts = <24 4 3>;
				status = "disabled";
			};

			macb1: ethernet@f8030000 {
				compatible = "cdns,at32ap7000-macb", "cdns,macb";
				reg = <0xf8030000 0x100>;
				interrupts = <27 4 3>;
				status = "disabled";
			};

			i2c0: i2c@f8010000 {
				compatible = "atmel,at91sam9x5-i2c";
				reg = <0xf8010000 0x100>;
				interrupts = <9 4 6>;
				#address-cells = <1>;
				#size-cells = <0>;
				status = "disabled";
			};

			i2c1: i2c@f8014000 {
				compatible = "atmel,at91sam9x5-i2c";
				reg = <0xf8014000 0x100>;
				interrupts = <10 4 6>;
				#address-cells = <1>;
				#size-cells = <0>;
				status = "disabled";
			};

			i2c2: i2c@f8018000 {
				compatible = "atmel,at91sam9x5-i2c";
				reg = <0xf8018000 0x100>;
				interrupts = <11 4 6>;
				#address-cells = <1>;
				#size-cells = <0>;
				status = "disabled";
			};

			adc0: adc@f804c000 {
				compatible = "atmel,at91sam9260-adc";
				reg = <0xf804c000 0x100>;
				interrupts = <19 4 0>;
				atmel,adc-use-external;
				atmel,adc-channels-used = <0xffff>;
				atmel,adc-vref = <3300>;
				atmel,adc-num-channels = <12>;
				atmel,adc-startup-time = <40>;
				atmel,adc-channel-base = <0x50>;
				atmel,adc-drdy-mask = <0x1000000>;
				atmel,adc-status-register = <0x30>;
				atmel,adc-trigger-register = <0xc0>;

				trigger@0 {
					trigger-name = "external-rising";
					trigger-value = <0x1>;
					trigger-external;
				};

				trigger@1 {
					trigger-name = "external-falling";
					trigger-value = <0x2>;
					trigger-external;
				};

				trigger@2 {
					trigger-name = "external-any";
					trigger-value = <0x3>;
					trigger-external;
				};

				trigger@3 {
					trigger-name = "continuous";
					trigger-value = <0x6>;
				};
			};
		};

		nand0: nand@40000000 {
			compatible = "atmel,at91rm9200-nand";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0x40000000 0x10000000
			      >;
			atmel,nand-addr-offset = <21>;
			atmel,nand-cmd-offset = <22>;
			gpios = <&pioD 5 0
				 &pioD 4 0
				 0
				>;
			status = "disabled";
		};

		usb0: ohci@00600000 {
			compatible = "atmel,at91rm9200-ohci", "usb-ohci";
			reg = <0x00600000 0x100000>;
			interrupts = <22 4 2>;
			status = "disabled";
		};

		usb1: ehci@00700000 {
			compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
			reg = <0x00700000 0x100000>;
			interrupts = <22 4 2>;
			status = "disabled";
		};
	};

	i2c@0 {
		compatible = "i2c-gpio";
		gpios = <&pioA 30 0 /* sda */
			 &pioA 31 0 /* scl */
			>;
		i2c-gpio,sda-open-drain;
		i2c-gpio,scl-open-drain;
		i2c-gpio,delay-us = <2>;	/* ~100 kHz */
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
	};

	i2c@1 {
		compatible = "i2c-gpio";
		gpios = <&pioC 0 0 /* sda */
			 &pioC 1 0 /* scl */
			>;
		i2c-gpio,sda-open-drain;
		i2c-gpio,scl-open-drain;
		i2c-gpio,delay-us = <2>;	/* ~100 kHz */
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
	};

	i2c@2 {
		compatible = "i2c-gpio";
		gpios = <&pioB 4 0 /* sda */
			 &pioB 5 0 /* scl */
			>;
		i2c-gpio,sda-open-drain;
		i2c-gpio,scl-open-drain;
		i2c-gpio,delay-us = <2>;	/* ~100 kHz */
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
	};
};
Commit	Line	Data
467f1cf5 NF	1	/*
	2	* at91sam9x5.dtsi - Device Tree Include file for AT91SAM9x5 family SoC
	3	* applies to AT91SAM9G15, AT91SAM9G25, AT91SAM9G35,
	4	* AT91SAM9X25, AT91SAM9X35 SoC
	5	*
	6	* Copyright (C) 2012 Atmel,
	7	* 2012 Nicolas Ferre <nicolas.ferre@atmel.com>
	8	*
	9	* Licensed under GPLv2 or later.
	10	*/
	11
	12	/include/ "skeleton.dtsi"
	13
	14	/ {
	15	model = "Atmel AT91SAM9x5 family SoC";
	16	compatible = "atmel,at91sam9x5";
	17	interrupt-parent = <&aic>;
	18
	19	aliases {
	20	serial0 = &dbgu;
	21	serial1 = &usart0;
	22	serial2 = &usart1;
	23	serial3 = &usart2;
	24	gpio0 = &pioA;
	25	gpio1 = &pioB;
	26	gpio2 = &pioC;
	27	gpio3 = &pioD;
	28	tcb0 = &tcb0;
	29	tcb1 = &tcb1;
05dcd361 LD	30	i2c0 = &i2c0;
	31	i2c1 = &i2c1;
	32	i2c2 = &i2c2;
467f1cf5 NF	33	};
	34	cpus {
	35	cpu@0 {
	36	compatible = "arm,arm926ejs";
	37	};
	38	};
	39
dcce6ce8	40	memory {
467f1cf5 NF	41	reg = <0x20000000 0x10000000>;
	42	};
	43
	44	ahb {
	45	compatible = "simple-bus";
	46	#address-cells = <1>;
	47	#size-cells = <1>;
	48	ranges;
	49
	50	apb {
	51	compatible = "simple-bus";
	52	#address-cells = <1>;
	53	#size-cells = <1>;
	54	ranges;
	55
	56	aic: interrupt-controller@fffff000 {
f8a073ee	57	#interrupt-cells = <3>;
467f1cf5 NF	58	compatible = "atmel,at91rm9200-aic";
467f1cf5 NF	59	interrupt-controller;
467f1cf5	60	reg = <0xfffff000 0x200>;
c6573943	61	atmel,external-irqs = <31>;
467f1cf5 NF	62	};
467f1cf5 NF	63
a7776ec6 JCPV	64	ramc0: ramc@ffffe800 {
	65	compatible = "atmel,at91sam9g45-ddramc";
	66	reg = <0xffffe800 0x200>;
	67	};
	68
eb5e76ff JCPV	69	pmc: pmc@fffffc00 {
	70	compatible = "atmel,at91rm9200-pmc";
	71	reg = <0xfffffc00 0x100>;
	72	};
	73
c8082d34 JCPV	74	rstc@fffffe00 {
	75	compatible = "atmel,at91sam9g45-rstc";
	76	reg = <0xfffffe00 0x10>;
	77	};
	78
82015c4e JCPV	79	shdwc@fffffe10 {
	80	compatible = "atmel,at91sam9x5-shdwc";
	81	reg = <0xfffffe10 0x10>;
	82	};
	83
467f1cf5 NF	84	pit: timer@fffffe30 {
	85	compatible = "atmel,at91sam9260-pit";
	86	reg = <0xfffffe30 0xf>;
f8a073ee	87	interrupts = <1 4 7>;
467f1cf5 NF	88	};
	89
	90	tcb0: timer@f8008000 {
	91	compatible = "atmel,at91sam9x5-tcb";
	92	reg = <0xf8008000 0x100>;
f8a073ee	93	interrupts = <17 4 0>;
467f1cf5 NF	94	};
	95
	96	tcb1: timer@f800c000 {
	97	compatible = "atmel,at91sam9x5-tcb";
	98	reg = <0xf800c000 0x100>;
f8a073ee	99	interrupts = <17 4 0>;
467f1cf5 NF	100	};
	101
	102	dma0: dma-controller@ffffec00 {
	103	compatible = "atmel,at91sam9g45-dma";
	104	reg = <0xffffec00 0x200>;
f8a073ee	105	interrupts = <20 4 0>;
467f1cf5 NF	106	};
	107
	108	dma1: dma-controller@ffffee00 {
	109	compatible = "atmel,at91sam9g45-dma";
	110	reg = <0xffffee00 0x200>;
f8a073ee	111	interrupts = <21 4 0>;
467f1cf5 NF	112	};
	113
	114	pioA: gpio@fffff400 {
582d5fbd	115	compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
467f1cf5	116	reg = <0xfffff400 0x100>;
f8a073ee	117	interrupts = <2 4 1>;
467f1cf5 NF	118	#gpio-cells = <2>;
467f1cf5 NF	119	gpio-controller;
21f81872	120	interrupt-controller;
51ac51a6	121	#interrupt-cells = <2>;
467f1cf5 NF	122	};
	123
	124	pioB: gpio@fffff600 {
582d5fbd	125	compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
467f1cf5	126	reg = <0xfffff600 0x100>;
f8a073ee	127	interrupts = <2 4 1>;
467f1cf5 NF	128	#gpio-cells = <2>;
467f1cf5 NF	129	gpio-controller;
21f81872	130	interrupt-controller;
51ac51a6	131	#interrupt-cells = <2>;
467f1cf5 NF	132	};
	133
	134	pioC: gpio@fffff800 {
582d5fbd	135	compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
467f1cf5	136	reg = <0xfffff800 0x100>;
f8a073ee	137	interrupts = <3 4 1>;
467f1cf5 NF	138	#gpio-cells = <2>;
467f1cf5 NF	139	gpio-controller;
21f81872	140	interrupt-controller;
51ac51a6	141	#interrupt-cells = <2>;
467f1cf5 NF	142	};
	143
	144	pioD: gpio@fffffa00 {
582d5fbd	145	compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
467f1cf5	146	reg = <0xfffffa00 0x100>;
f8a073ee	147	interrupts = <3 4 1>;
467f1cf5 NF	148	#gpio-cells = <2>;
467f1cf5 NF	149	gpio-controller;
21f81872	150	interrupt-controller;
51ac51a6	151	#interrupt-cells = <2>;
467f1cf5 NF	152	};
	153
	154	dbgu: serial@fffff200 {
	155	compatible = "atmel,at91sam9260-usart";
	156	reg = <0xfffff200 0x200>;
f8a073ee	157	interrupts = <1 4 7>;
467f1cf5 NF	158	status = "disabled";
	159	};
	160
	161	usart0: serial@f801c000 {
	162	compatible = "atmel,at91sam9260-usart";
	163	reg = <0xf801c000 0x200>;
f8a073ee	164	interrupts = <5 4 5>;
467f1cf5 NF	165	atmel,use-dma-rx;
	166	atmel,use-dma-tx;
	167	status = "disabled";
	168	};
	169
	170	usart1: serial@f8020000 {
	171	compatible = "atmel,at91sam9260-usart";
	172	reg = <0xf8020000 0x200>;
f8a073ee	173	interrupts = <6 4 5>;
467f1cf5 NF	174	atmel,use-dma-rx;
	175	atmel,use-dma-tx;
	176	status = "disabled";
	177	};
	178
	179	usart2: serial@f8024000 {
	180	compatible = "atmel,at91sam9260-usart";
	181	reg = <0xf8024000 0x200>;
f8a073ee	182	interrupts = <7 4 5>;
467f1cf5 NF	183	atmel,use-dma-rx;
	184	atmel,use-dma-tx;
	185	status = "disabled";
	186	};
	187
	188	macb0: ethernet@f802c000 {
	189	compatible = "cdns,at32ap7000-macb", "cdns,macb";
	190	reg = <0xf802c000 0x100>;
f8a073ee	191	interrupts = <24 4 3>;
467f1cf5 NF	192	status = "disabled";
	193	};
	194
	195	macb1: ethernet@f8030000 {
	196	compatible = "cdns,at32ap7000-macb", "cdns,macb";
	197	reg = <0xf8030000 0x100>;
f8a073ee	198	interrupts = <27 4 3>;
467f1cf5 NF	199	status = "disabled";
467f1cf5 NF	200	};
d029f371	201
05dcd361 LD	202	i2c0: i2c@f8010000 {
	203	compatible = "atmel,at91sam9x5-i2c";
	204	reg = <0xf8010000 0x100>;
	205	interrupts = <9 4 6>;
	206	#address-cells = <1>;
	207	#size-cells = <0>;
	208	status = "disabled";
	209	};
	210
	211	i2c1: i2c@f8014000 {
	212	compatible = "atmel,at91sam9x5-i2c";
	213	reg = <0xf8014000 0x100>;
	214	interrupts = <10 4 6>;
	215	#address-cells = <1>;
	216	#size-cells = <0>;
	217	status = "disabled";
	218	};
	219
	220	i2c2: i2c@f8018000 {
	221	compatible = "atmel,at91sam9x5-i2c";
	222	reg = <0xf8018000 0x100>;
	223	interrupts = <11 4 6>;
	224	#address-cells = <1>;
	225	#size-cells = <0>;
	226	status = "disabled";
	227	};
	228
d029f371 MR	229	adc0: adc@f804c000 {
	230	compatible = "atmel,at91sam9260-adc";
	231	reg = <0xf804c000 0x100>;
f8a073ee	232	interrupts = <19 4 0>;
d029f371 MR	233	atmel,adc-use-external;
	234	atmel,adc-channels-used = <0xffff>;
	235	atmel,adc-vref = <3300>;
	236	atmel,adc-num-channels = <12>;
	237	atmel,adc-startup-time = <40>;
	238	atmel,adc-channel-base = <0x50>;
	239	atmel,adc-drdy-mask = <0x1000000>;
	240	atmel,adc-status-register = <0x30>;
	241	atmel,adc-trigger-register = <0xc0>;
	242
	243	trigger@0 {
	244	trigger-name = "external-rising";
	245	trigger-value = <0x1>;
	246	trigger-external;
	247	};
	248
	249	trigger@1 {
	250	trigger-name = "external-falling";
	251	trigger-value = <0x2>;
	252	trigger-external;
	253	};
	254
	255	trigger@2 {
	256	trigger-name = "external-any";
	257	trigger-value = <0x3>;
	258	trigger-external;
	259	};
	260
	261	trigger@3 {
	262	trigger-name = "continuous";
	263	trigger-value = <0x6>;
	264	};
	265	};
467f1cf5	266	};
86a89f4f JCPV	267
	268	nand0: nand@40000000 {
	269	compatible = "atmel,at91rm9200-nand";
	270	#address-cells = <1>;
	271	#size-cells = <1>;
	272	reg = <0x40000000 0x10000000
	273	>;
	274	atmel,nand-addr-offset = <21>;
	275	atmel,nand-cmd-offset = <22>;
4352808c NF	276	gpios = <&pioD 5 0
4352808c NF	277	&pioD 4 0
86a89f4f JCPV	278	0
	279	>;
	280	status = "disabled";
	281	};
6a062459 JCPV	282
	283	usb0: ohci@00600000 {
	284	compatible = "atmel,at91rm9200-ohci", "usb-ohci";
	285	reg = <0x00600000 0x100000>;
f8a073ee	286	interrupts = <22 4 2>;
6a062459 JCPV	287	status = "disabled";
6a062459 JCPV	288	};
62c5553a JCPV	289
	290	usb1: ehci@00700000 {
	291	compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
	292	reg = <0x00700000 0x100000>;
f8a073ee	293	interrupts = <22 4 2>;
62c5553a JCPV	294	status = "disabled";
62c5553a JCPV	295	};
467f1cf5	296	};
10f71c28 JCPV	297
	298	i2c@0 {
	299	compatible = "i2c-gpio";
	300	gpios = <&pioA 30 0 /* sda */
	301	&pioA 31 0 /* scl */
	302	>;
	303	i2c-gpio,sda-open-drain;
	304	i2c-gpio,scl-open-drain;
	305	i2c-gpio,delay-us = <2>; /* ~100 kHz */
	306	#address-cells = <1>;
	307	#size-cells = <0>;
	308	status = "disabled";
	309	};
	310
	311	i2c@1 {
	312	compatible = "i2c-gpio";
	313	gpios = <&pioC 0 0 /* sda */
	314	&pioC 1 0 /* scl */
	315	>;
	316	i2c-gpio,sda-open-drain;
	317	i2c-gpio,scl-open-drain;
	318	i2c-gpio,delay-us = <2>; /* ~100 kHz */
	319	#address-cells = <1>;
	320	#size-cells = <0>;
	321	status = "disabled";
	322	};
	323
	324	i2c@2 {
	325	compatible = "i2c-gpio";
	326	gpios = <&pioB 4 0 /* sda */
	327	&pioB 5 0 /* scl */
	328	>;
	329	i2c-gpio,sda-open-drain;
	330	i2c-gpio,scl-open-drain;
	331	i2c-gpio,delay-us = <2>; /* ~100 kHz */
	332	#address-cells = <1>;
	333	#size-cells = <0>;
	334	status = "disabled";
	335	};
467f1cf5	336	};